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CN102398886B - Encapsulation structure with microelectromechanical components and its manufacturing method - Google Patents

Encapsulation structure with microelectromechanical components and its manufacturing method Download PDF

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Publication number
CN102398886B
CN102398886B CN201010287096.6A CN201010287096A CN102398886B CN 102398886 B CN102398886 B CN 102398886B CN 201010287096 A CN201010287096 A CN 201010287096A CN 102398886 B CN102398886 B CN 102398886B
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dielectric layer
packaging
encapsulating structure
microcomputer electric
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CN102398886A (en
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黄君安
廖信一
邱世冠
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

The invention relates to a packaging structure with a micro-electromechanical element and a manufacturing method thereof, wherein the packaging structure with the micro-electromechanical element comprises: the packaging substrate is provided with a first circuit layer and a second circuit layer on two surfaces respectively, and a chip is embedded in the packaging substrate; the first dielectric layer is arranged on the packaging substrate and the chip; a third circuit layer disposed on the first dielectric layer; the second dielectric layer is arranged on the first dielectric layer and the third circuit layer, and a concave part is arranged on the surface of the second dielectric layer; a cover body arranged on the inner edge of the concave part and the top surface of the second dielectric layer at the periphery of the concave part, wherein the cover body part on the top surface of the second dielectric layer forms a cover body frame; the adhesive material is arranged on the frame of the cover body; and the surface of the substrate is provided with a micro-electromechanical element, and the micro-electromechanical element is jointed on the packaging substrate in a way of corresponding to the concave part. The packaging structure has smaller size, lower cost and better electrical property.

Description

具微机电元件的封装结构及其制法Encapsulation structure with microelectromechanical components and its manufacturing method

技术领域technical field

本发明涉及一种封装结构及其制法,特别是涉及一种具微机电元件的封装结构及其制法。The invention relates to a packaging structure and its manufacturing method, in particular to a packaging structure with micro-electromechanical components and its manufacturing method.

背景技术Background technique

微机电系统(Micro Electro Mechanical System,简称MEMS)是一种兼具电子与机械功能的微小装置,在制造上则通过各种微细加工技术来达成,可将微机电元件设置于芯片的表面上,且以保护罩或底胶进行封装保护,从而使内部的微机电元件不受外界环境的破坏,而得到一微机电封装结构。Micro Electro Mechanical System (MEMS for short) is a tiny device with both electronic and mechanical functions. In manufacturing, it is achieved through various micro-fabrication technologies. Micro Electro Mechanical components can be placed on the surface of the chip. In addition, a protective cover or primer is used for encapsulation and protection, so that the internal micro-electro-mechanical components are not damaged by the external environment, and a micro-electro-mechanical encapsulation structure is obtained.

请参阅图1,为现有具微机电元件的封装结构的剖视图。如图所示,现有的具微机电元件的封装结构包括例如为四边扁平无接脚(Quad FlatNo Lead,简称QFN)型式的导线架10;芯片11,设于该导线架10上;微机电元件12,设于该芯片11上;盖体13,设于该芯片11上并封盖该芯片11;铝层14,设于该盖体13的顶面;焊线15,电性连接该芯片11与导线架10以及电性连接该铝层14与导线架10;以及封装材料16,包覆该导线架10、芯片11、盖体13、铝层14与焊线15。Please refer to FIG. 1 , which is a cross-sectional view of a conventional packaging structure with MEMS components. As shown in the figure, the existing package structure of micro-electromechanical components includes, for example, a lead frame 10 of a Quad Flat No Lead (QFN) type; a chip 11 is arranged on the lead frame 10; The element 12 is arranged on the chip 11; the cover 13 is arranged on the chip 11 and covers the chip 11; the aluminum layer 14 is arranged on the top surface of the cover 13; the bonding wire 15 is electrically connected to the chip 11 and the lead frame 10 and electrically connecting the aluminum layer 14 and the lead frame 10 ;

但是,上述现有的微机电元件12需设置于一具有相当厚度的导线架10上,且需另加盖体13以保护微机电元件12,而此盖体13也具有一相当厚度,导致封装结构的整体厚度过大。However, the above-mentioned existing MEMS element 12 needs to be arranged on a lead frame 10 with a considerable thickness, and an additional cover body 13 is required to protect the MEMS element 12, and this cover body 13 also has a considerable thickness, resulting in packaging The overall thickness of the structure is too large.

此外,现有的具微机电元件的封装结构是通过打金线方式电性连接微机电元件与导线架,从而导致两者间的电讯传输迟缓与灵敏度下降,且以金线作为电讯传输路径亦会使具微机电元件的封装结构的制造成本大幅提高,又最终仍需以封装材料包覆整个微机电元件及金线,而该封装材料也会增加整体封装结构的厚度,如此的具微机电元件的封装结构并不符合终端产品朝向较轻薄短小的体积及较低的生产成本的趋势。In addition, the existing packaging structure with MEMS components is electrically connected to the MEMS components and the lead frame by means of gold wires, which results in slow telecommunication transmission and decreased sensitivity between the two, and using gold wires as the telecommunication transmission path is also It will greatly increase the manufacturing cost of the packaging structure with MEMS components, and finally still need to cover the entire MEMS components and gold wires with packaging materials, and the packaging material will also increase the thickness of the overall packaging structure, such MEMS The packaging structure of components does not conform to the trend of end products towards lighter, thinner, smaller volume and lower production cost.

因此,如何避免上述现有技术中的种种问题,而制作出可大幅缩小整体体积、大幅降低制作成本、及大幅提高电讯传输效率的具微机电元件的封装结构,实已成为目前急欲解决的问题。Therefore, how to avoid the various problems in the above-mentioned prior art, and make a packaging structure with micro-electromechanical components that can greatly reduce the overall volume, greatly reduce the production cost, and greatly improve the efficiency of telecommunication transmission has become an urgent problem to be solved at present. question.

发明内容Contents of the invention

有鉴于上述现有技术的缺陷,本发明的主要目的是提供一种具有较小尺寸且电性较佳的微机电元件的封装结构及其制法。In view of the above-mentioned defects in the prior art, the main purpose of the present invention is to provide a packaging structure and manufacturing method of a micro-electromechanical element with a smaller size and better electrical performance.

本发明的另一目的是提供一种微机电元件的封装结构及其制法,可降低制作成本并简化工艺步骤。Another object of the present invention is to provide a micro-electromechanical device packaging structure and its manufacturing method, which can reduce manufacturing costs and simplify process steps.

为达到上述目的,本发明提供一种具微机电元件的封装结构,包括:具有相对第一表面与第二表面的封装基板,且该封装基板具有:第一线路层,形成于第一表面上;第二线路层,形成于第二表面上;以及导电通孔,贯穿该封装基板并电性连接该第一线路层与第二线路层;芯片,嵌埋于该封装基板中,且该芯片上具有多个外露于该封装基板第一表面的电极垫;第一介电层,设于该第一表面与芯片上,并外露出该第一线路层及电极垫;第三线路层,设于该第一介电层上并电性连接该第一线路层及电极垫;第二介电层,设于该第一介电层与第三线路层上,该第二介电层表面具有凹部及贯穿该第一及第二介电层的穿孔;盖体,设于该凹部内缘、与凹部周缘的第二介电层顶表面,其中,在该第二介电层顶表面上的盖体部分构成盖体边框;第一电性连接垫,设于该第二介电层上;第一导电盲孔,设于该穿孔中并电性连接该第一线路层与第一电性连接垫;接着材料,设于该第一电性连接垫与该盖体边框上;以及基材,具有设于基材表面上的微机电元件与第二电性连接垫,且该基材以该微机电元件对应该凹部的方式接合于该封装基板上。To achieve the above object, the present invention provides a packaging structure with micro-electromechanical components, including: a packaging substrate having a first surface opposite to a second surface, and the packaging substrate has: a first circuit layer formed on the first surface The second circuit layer is formed on the second surface; and the conductive via penetrates the package substrate and electrically connects the first circuit layer and the second circuit layer; the chip is embedded in the package substrate, and the chip There are a plurality of electrode pads exposed on the first surface of the packaging substrate; the first dielectric layer is arranged on the first surface and the chip, and exposes the first circuit layer and electrode pads; the third circuit layer is provided on the first dielectric layer and electrically connected to the first circuit layer and the electrode pad; the second dielectric layer is arranged on the first dielectric layer and the third circuit layer, and the surface of the second dielectric layer has The recess and the perforation through the first and second dielectric layers; the cover body is arranged on the inner edge of the recess and the top surface of the second dielectric layer on the periphery of the recess, wherein the top surface of the second dielectric layer The cover part constitutes the frame of the cover; the first electrical connection pad is arranged on the second dielectric layer; the first conductive blind hole is arranged in the through hole and electrically connects the first circuit layer and the first electrical layer a connection pad; a bonding material disposed on the first electrical connection pad and the frame of the cover; and a base material having a microelectromechanical element and a second electrical connection pad disposed on the surface of the base material, and the base material is formed by The MEMS element is bonded to the packaging substrate in a manner corresponding to the recess.

本发明还提供一种具微机电元件的封装结构的制法,包括:准备一具有相对第一表面与第二表面的封装基板,该封装基板的第一表面与第二表面分别形成有第一线路层与第二线路层,且通过贯穿该封装基板的导电通孔电性连接该第一线路层与第二线路层,该封装基板中嵌埋有芯片,该芯片上具有多个外露于该封装基板第一表面的电极垫;在该第一表面与芯片上依序形成第一介电层及电性连接该电极垫及第一线路层的第三线路层;在该第一介电层与第三线路层上形成第二介电层;移除部分该第二介电层以形成凹部及形成贯穿该第一及第二介电层的穿孔;在该凹部内缘、与凹部周缘的第二介电层顶表面形成盖体,其中,在该第二介电层顶表面上的盖体部分构成盖体边框,并在该第二介电层上形成第一电性连接垫,且在该穿孔中形成电性连接该第一线路层与第一电性连接垫的第一导电盲孔;在该第一电性连接垫与该盖体边框上形成接着材料;提供一表面上设有微机电元件与第二电性连接垫的基材;以及以该微机电元件对应该凹部的方式接合该基材与封装基板。The present invention also provides a method for manufacturing a packaging structure with micro-electromechanical components, comprising: preparing a packaging substrate having a first surface and a second surface opposite to each other, and the first surface and the second surface of the packaging substrate are respectively formed with first The circuit layer and the second circuit layer are electrically connected to the first circuit layer and the second circuit layer through the conductive vias penetrating the package substrate. A chip is embedded in the package substrate, and the chip has a plurality of exposed on the The electrode pads on the first surface of the packaging substrate; the first dielectric layer and the third circuit layer electrically connected to the electrode pads and the first circuit layer are sequentially formed on the first surface and the chip; on the first dielectric layer forming a second dielectric layer on the third circuit layer; removing part of the second dielectric layer to form a recess and forming a through hole through the first and second dielectric layers; on the inner edge of the recess and the periphery of the recess A cover is formed on the top surface of the second dielectric layer, wherein the cover portion on the top surface of the second dielectric layer constitutes a frame of the cover, and a first electrical connection pad is formed on the second dielectric layer, and A first conductive blind hole electrically connecting the first circuit layer and the first electrical connection pad is formed in the through hole; an adhesive material is formed on the first electrical connection pad and the frame of the cover; a surface is provided There is a base material with the micro-electro-mechanical element and the second electrical connection pad; and the base material and the packaging substrate are bonded in such a way that the micro-electro-mechanical element corresponds to the recess.

由上可知,本发明的具微机电元件的封装结构是直接将芯片嵌埋于封装基板中,因此可减少整体封装结构的厚度与体积。再者,本发明是通过嵌埋线路以电性连接芯片、微机电元件与封装基板,其电讯传输效率较现有打线方式高,且其制作成本较打线方式低;又本发明的盖体可与第一电性连接垫和第一导电盲孔同时形成,故可简化工艺步骤。此外,相比于现有的四边扁平无接脚型式导线架,本发明所形成的阵列式焊球可提供较多且较密集的电性连接点,进而扩大其应用范围。It can be seen from the above that the packaging structure with MEMS components of the present invention directly embeds chips in the packaging substrate, so the thickness and volume of the overall packaging structure can be reduced. Furthermore, the present invention electrically connects the chips, micro-electromechanical components, and the packaging substrate by embedding lines, and its telecommunication transmission efficiency is higher than that of the existing wire-bonding method, and its manufacturing cost is lower than that of the wire-bonding method; and the cover of the present invention The body can be formed simultaneously with the first electrical connection pad and the first conductive blind hole, so the process steps can be simplified. In addition, compared with the existing four-sided flat lead frame without pins, the arrayed solder balls formed by the present invention can provide more and denser electrical connection points, thereby expanding its application range.

附图说明Description of drawings

图1为现有技术具微机电元件的封装结构的剖视图;1 is a cross-sectional view of a prior art packaging structure with micro-electromechanical components;

图2A至图2E为本发明的具微机电元件的封装结构及其制法的剖视图,其中,图2C’为显示形成第一防焊层的制法示意图。2A to FIG. 2E are cross-sectional views of the packaging structure with micro-electromechanical components and its manufacturing method of the present invention, wherein FIG. 2C' is a schematic diagram showing the manufacturing method of forming the first solder mask layer.

主要元件符号说明:Description of main component symbols:

10  导线架10 lead frame

11、22  芯片11, 22 chips

12、41  微机电元件12, 41 microelectromechanical components

13、28  盖体13, 28 cover body

14  铝层14 aluminum layers

15  焊线15 welding wire

16  封装材料16 Packaging material

2   封装结构2 package structure

20  封装基板20 package substrate

20a 第一表面20a First surface

20b 第二表面20b second surface

200 导电通孔200 conductive vias

21a 第一线路层21a The first line layer

21b 第二线路层21b second line layer

221 电极垫221 electrode pad

23  第一介电层23 The first dielectric layer

24  第三线路层24 Third line layer

241 第三导电盲孔241 The third conductive blind hole

25  第二介电层25 second dielectric layer

250 凹部250 concave

26  增层结构26 Build-up structure

261 第三介电层261 third dielectric layer

262 第四线路层262 fourth line layer

263 第二导电盲孔263 The second conductive blind hole

264 焊球垫264 Ball Pad

27  第二防焊层27 Second solder mask layer

270 防焊层开孔270 Solder mask opening

281 盖体边框281 Cover frame

29  第一电性连接垫29 The first electrical connection pad

290 穿孔290 perforations

291 第一导电盲孔291 The first conductive blind hole

30  接着材料30 Adhesive materials

31  焊球31 solder balls

32  第一防焊层32 The first solder mask

40  基材40 substrate

401 第二电性连接垫401 Second electrical connection pad

402 金属框402 metal frame

具体实施方式Detailed ways

以下通过特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容可能涵盖的范围内。同时,本说明书中所引用的如“上、下”及“一”等用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification, for those skilled in the art to understand and read, and are not used to limit the implementation of the present invention. condition, so it has no technical substantive meaning, and any modification of structure, change of proportional relationship or adjustment of size shall still fall within the scope of the present invention without affecting the effect and purpose of the present invention. The disclosed technical content may cover the range. At the same time, terms such as "upper, lower" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the applicable scope of the present invention. Without substantive changes in technical content, it should also be regarded as the scope of the present invention that can be implemented.

请参阅图2A至图2E,为本发明的具微机电元件的封装结构及其制法的剖视图。Please refer to FIG. 2A to FIG. 2E , which are cross-sectional views of the packaging structure with MEMS components and its manufacturing method of the present invention.

首先,如图2A所示,准备一封装基板20,该封装基板20具有第一表面20a与第二表面20b,该第一表面20a与第二表面20b分别形成有第一线路层21a与第二线路层21b,且通过贯穿该封装基板20的导电通孔200电性连接该第一线路层21a与第二线路层21b。又该封装基板20中嵌埋有芯片22,其中,该芯片22上具有多个外露于该封装基板20第一表面20a的电极垫221,该芯片22可为特定用途集成电路(ASIC)芯片。接着,在该第一表面20a与芯片22上形成第一介电层23,并在该第一介电层23上形成第三线路层24,其中,可通过激光穿孔的方式在第一介电层23中形成第三导电盲孔241以电性连接该电极垫221及第一线路层21a;然后,在该第一介电层23与第三线路层24上形成第二介电层25,该第二介电层25的材料可为防焊材料或感光介电材料。并且,所提供的封装基板20第二表面上可具有增层结构26,或者,也可在工艺过程中于该封装基板20的第二表面20b上形成增层结构26,该增层结构26包括至少一第三介电层261、形成于该第三介电层261上的第四线路层262、及多个形成于该第三介电层261中并电性连接该第四线路层262与第二线路层21b的第二导电盲孔263,再于该增层结构26上形成第二防焊层27。First, as shown in FIG. 2A, a package substrate 20 is prepared. The package substrate 20 has a first surface 20a and a second surface 20b, and the first surface 20a and the second surface 20b are respectively formed with a first circuit layer 21a and a second circuit layer. The wiring layer 21b is electrically connected to the first wiring layer 21a and the second wiring layer 21b through the conductive via 200 penetrating through the packaging substrate 20 . A chip 22 is embedded in the packaging substrate 20 , wherein the chip 22 has a plurality of electrode pads 221 exposed on the first surface 20 a of the packaging substrate 20 , and the chip 22 can be an application specific integrated circuit (ASIC) chip. Next, a first dielectric layer 23 is formed on the first surface 20a and the chip 22, and a third circuit layer 24 is formed on the first dielectric layer 23, wherein the first dielectric layer 24 can be formed by laser perforation. A third conductive blind hole 241 is formed in the layer 23 to electrically connect the electrode pad 221 and the first wiring layer 21a; then, a second dielectric layer 25 is formed on the first dielectric layer 23 and the third wiring layer 24, The material of the second dielectric layer 25 can be a solder resist material or a photosensitive dielectric material. Moreover, the provided package substrate 20 may have a build-up structure 26 on the second surface, or may also form a build-up structure 26 on the second surface 20b of the package substrate 20 during the process, and the build-up structure 26 includes At least one third dielectric layer 261, a fourth circuit layer 262 formed on the third dielectric layer 261, and a plurality of circuits formed in the third dielectric layer 261 and electrically connected to the fourth circuit layer 262 and The second conductive blind hole 263 of the second circuit layer 21 b forms a second solder resist layer 27 on the build-up structure 26 .

如图2B所示,利用光微影(photo-lithography)工艺或激光工艺移除部分该第二介电层25以形成凹部250及形成贯穿该第一介电层23及第二介电层25的穿孔290,接着,在该凹部250内缘、与凹部250周缘的第二介电层25顶表面形成盖体28,其中,在该第二介电层25顶表面上的盖体28部分构成盖体边框281,并通过镀覆工艺或沉积的方式在该第二介电层25上形成第一电性连接垫29,且在该穿孔290中形成电性连接该第一线路层21a与第一电性连接垫29的第一导电盲孔291,其中,该盖体28的材料可为金属、硅、玻璃或陶瓷。As shown in FIG. 2B , a portion of the second dielectric layer 25 is removed by photolithography or a laser process to form a concave portion 250 and to form a hole through the first dielectric layer 23 and the second dielectric layer 25. The perforation 290, and then, the cover 28 is formed on the inner edge of the recess 250 and the top surface of the second dielectric layer 25 on the periphery of the recess 250, wherein the part of the cover 28 on the top surface of the second dielectric layer 25 constitutes cover frame 281, and form a first electrical connection pad 29 on the second dielectric layer 25 by plating process or deposition, and form an electrical connection pad 29 in the through hole 290 to connect the first circuit layer 21a and the second circuit layer 21a. A first conductive blind hole 291 is electrically connected to the pad 29 , wherein the material of the cover 28 can be metal, silicon, glass or ceramics.

如图2C所示,在该第一电性连接垫29与该盖体边框281上形成接着材料30,该接着材料30为设置于该第一电性连接垫29上的焊料凸块、以及植设于该盖体边框281上环状的焊料凸块、焊锡膏或玻璃粘胶。As shown in FIG. 2C , an adhesive material 30 is formed on the first electrical connection pad 29 and the cover frame 281. The adhesive material 30 is a solder bump disposed on the first electrical connection pad 29 and an implant. A ring-shaped solder bump, solder paste or glass glue is provided on the cover frame 281 .

另外,如图2C’所示,在形成接着材料30之前,也可在该第二介电层25与第一电性连接垫29上形成第一防焊层32,并形成多个对应外露该第一电性连接垫29的开孔,且该接着材料30形成于该开孔中,该第一防焊层32的材料可为防焊材料或感光介电材料。In addition, as shown in FIG. 2C', before forming the bonding material 30, the first solder resist layer 32 may also be formed on the second dielectric layer 25 and the first electrical connection pad 29, and a plurality of correspondingly exposed solder resist layers 32 may be formed. The opening of the first electrical connection pad 29 , and the bonding material 30 is formed in the opening, and the material of the first solder resist layer 32 can be a solder resist material or a photosensitive dielectric material.

如图2D所示,提供一表面上设有微机电元件41与第二电性连接垫401的基材40,该基材40的材料可为硅质材料,该第二电性连接垫401通过该接着材料30以电性连接至该第一电性连接垫29,与该微机电元件41同侧的该基材40表面还包括有金属框402,且通过该接着材料30以该微机电元件41对应该凹部250的方式接合该基材40与封装基板20,也就是通过该接着材料30对应连接该盖体边框281与金属框402。与该盖体边框281连接的金属框402围绕该微机电元件41四周,以将该微机电元件41密封于封装结构内部,该微机电元件41可为陀螺仪(gyroscope)、加速度计(accelerometer)或射频微机电(RF MEMS)元件。As shown in FIG. 2D , a substrate 40 is provided with a microelectromechanical element 41 and a second electrical connection pad 401 on its surface. The material of the substrate 40 can be a silicon material, and the second electrical connection pad 401 passes through The adhesive material 30 is electrically connected to the first electrical connection pad 29, and the surface of the substrate 40 on the same side as the MEMS element 41 also includes a metal frame 402, and the MEMS element is connected to the MEMS element through the adhesive material 30. 41 is bonded to the base material 40 and the packaging substrate 20 in a manner corresponding to the concave portion 250 , that is, the cover frame 281 and the metal frame 402 are connected correspondingly through the bonding material 30 . The metal frame 402 connected to the cover frame 281 surrounds the MEMS element 41 to seal the MEMS element 41 inside the packaging structure. The MEMS element 41 can be a gyroscope (gyroscope), an accelerometer (accelerometer) or radio frequency microelectromechanical (RF MEMS) components.

如图2E所示,该增层结构26最外层的第四线路层262还可具有多个焊球垫264,在该第二防焊层27中形成多个对应外露各该焊球垫264的防焊层开孔270,并在各该焊球垫264上形成焊球31,最后,进行切单工艺(singulation),以得到多个具微机电元件的封装结构2。As shown in FIG. 2E, the fourth circuit layer 262 of the outermost layer of the build-up structure 26 can also have a plurality of solder ball pads 264, and a plurality of corresponding exposed solder ball pads 264 are formed in the second solder resist layer 27. Holes 270 are opened in the solder resist layer, and solder balls 31 are formed on each of the solder ball pads 264. Finally, a singulation process (singulation) is performed to obtain a plurality of packaging structures 2 with MEMS components.

本发明还提供一种具微机电元件的封装结构2,包括:具有相对第一表面20a与第二表面20b的封装基板20,且该封装基板20具有:第一线路层21a,形成于第一表面20a上;第二线路层21b,形成于第二表面20b上;以及导电通孔200,贯穿该封装基板20并电性连接该第一线路层21a与第二线路层21b;芯片22,嵌埋于该封装基板20中,且该芯片22上具有多个外露于该封装基板20第一表面20a的电极垫221;第一介电层23,设于该第一表面20a与芯片22上,并外露出该第一线路21a层及电极垫221;第三线路层24,设于该第一介电层23上并电性连接该第一线路层21a及电极垫221;第二介电层25,设于该第一介电层23与第三线路层24上,该第二介电层25表面具有凹部250及贯穿该第一介电层23及第二介电层25的穿孔290;盖体28,设于该凹部250内缘、与凹部250周缘的第二介电层25顶表面,其中,在该第二介电层25顶表面上的盖体28部分构成盖体边框281;第一电性连接垫29,设于该第二介电层25上;第一导电盲孔291,设于该穿孔250中并电性连接该第一线路层21a与第一电性连接垫29;接着材料30,设于该第一电性连接垫29与该盖体边框281上;以及基材40,具有设于基材40表面上的微机电元件41与第二电性连接垫401,且该基材40以该微机电元件41对应该凹部250的方式接合于该封装基板20上。The present invention also provides a packaging structure 2 with micro-electromechanical components, including: a packaging substrate 20 having an opposite first surface 20a and a second surface 20b, and the packaging substrate 20 has: a first circuit layer 21a formed on the first on the surface 20a; the second circuit layer 21b is formed on the second surface 20b; and the conductive via 200 penetrates the package substrate 20 and electrically connects the first circuit layer 21a and the second circuit layer 21b; the chip 22 is embedded Buried in the packaging substrate 20, and the chip 22 has a plurality of electrode pads 221 exposed on the first surface 20a of the packaging substrate 20; the first dielectric layer 23 is provided on the first surface 20a and the chip 22, and expose the first circuit layer 21a and the electrode pad 221; the third circuit layer 24 is arranged on the first dielectric layer 23 and electrically connected to the first circuit layer 21a and the electrode pad 221; the second dielectric layer 25, disposed on the first dielectric layer 23 and the third circuit layer 24, the surface of the second dielectric layer 25 has a concave portion 250 and a through hole 290 penetrating through the first dielectric layer 23 and the second dielectric layer 25; The cover 28 is arranged on the inner edge of the recess 250 and the top surface of the second dielectric layer 25 on the periphery of the recess 250, wherein the part of the cover 28 on the top surface of the second dielectric layer 25 forms a cover frame 281; The first electrical connection pad 29 is disposed on the second dielectric layer 25; the first conductive blind hole 291 is disposed in the through hole 250 and electrically connects the first circuit layer 21a and the first electrical connection pad 29 the bonding material 30 is disposed on the first electrical connection pad 29 and the cover frame 281; and the substrate 40 has a microelectromechanical element 41 and a second electrical connection pad 401 disposed on the surface of the substrate 40, And the base material 40 is bonded to the packaging substrate 20 in such a way that the MEMS element 41 corresponds to the concave portion 250 .

在上述的具微机电元件的封装结构2中,与该微机电元件41同侧的该基材40表面还包括有金属框402,且通过该接着材料30对应连接该盖体边框281与该金属框第二电性连接垫402。此外,上述的具微机电元件的封装结构2还可包括第一防焊层32(如图2C’所示),设于该第二介电层25与第一电性连接垫29上,该第一防焊层32的材料可为防焊材料或感光介电材料,且该第一防焊层32具有多个对应外露该第一电性连接垫29的开孔,且该接着材料形成于该开孔中。In the above-mentioned package structure 2 with microelectromechanical components, the surface of the substrate 40 on the same side as the microelectromechanical component 41 also includes a metal frame 402, and the cover frame 281 is connected to the metal frame 402 through the bonding material 30 correspondingly. frame the second electrical connection pad 402 . In addition, the above-mentioned package structure 2 with MEMS components may further include a first solder resist layer 32 (as shown in FIG. 2C ′), which is disposed on the second dielectric layer 25 and the first electrical connection pad 29, the The material of the first solder resist layer 32 can be a solder resist material or a photosensitive dielectric material, and the first solder resist layer 32 has a plurality of corresponding openings exposing the first electrical connection pad 29, and the bonding material is formed on in this opening.

又在前述的封装结构中,还可包括增层结构26,设于该封装基板20第二表面20a上,该增层结构26包括至少一第三介电层261、形成于该第三介电层261上的第四线路层262、及多个形成于该第三介电层261中并电性连接该第四线路层262与第二线路层21b的第二导电盲孔263,且该增层结构26最外层的第四线路层262还具有多个焊球垫264。Furthermore, in the aforementioned package structure, a build-up structure 26 may also be included, which is disposed on the second surface 20a of the package substrate 20, and the build-up structure 26 includes at least one third dielectric layer 261 formed on the third dielectric layer. The fourth circuit layer 262 on the layer 261, and a plurality of second conductive blind holes 263 formed in the third dielectric layer 261 and electrically connecting the fourth circuit layer 262 and the second circuit layer 21b, and the increased The fourth circuit layer 262 on the outermost layer of the layer structure 26 also has a plurality of solder ball pads 264 .

在所述的具微机电元件的封装结构中,还可包括第二防焊层27,设于该增层结构26上,该第二防焊层27中具有多个对应外露各该焊球垫264的防焊层开孔270,又还可包括焊球31,设于各该焊球垫264上。In the package structure with micro-electromechanical components, a second solder resist layer 27 may also be included on the build-up structure 26, and the second solder resist layer 27 has a plurality of corresponding exposed solder ball pads. The solder mask openings 270 at 264 may further include solder balls 31 disposed on each of the solder ball pads 264 .

所述的具微机电元件的封装结构中,该芯片22可为特定用途集成电路(ASIC)芯片,该第二介电层25的材料可为防焊材料或感光介电材料,该盖体28的材料可为金属、硅、玻璃或陶瓷,该微机电元件41可为陀螺仪、加速度计或射频微机电元件,且该基材40的材料可为硅质材料。In the package structure with MEMS components, the chip 22 can be an application-specific integrated circuit (ASIC) chip, the material of the second dielectric layer 25 can be a solder resist material or a photosensitive dielectric material, and the cover 28 The material of the substrate 40 can be metal, silicon, glass or ceramics, the MEMS element 41 can be a gyroscope, an accelerometer or a radio frequency MEMS element, and the material of the substrate 40 can be a silicon material.

综上所述,本发明的具微机电元件的封装结构是直接将芯片嵌埋于封装基板中,因此可减少整体封装结构的厚度与体积。再者,本发明是通过嵌埋线路以电性连接芯片、微机电元件与封装基板,其电讯传输效率较打线方式高,且其制作成本较打线方式低。又本发明的盖体可与第一电性连接垫和第一导电盲孔同时形成,故可简化工艺步骤;而且,相比于现有的QFN型式导线架,本发明所形成的阵列式焊球可提供较多且较密集的电性连接点,进而扩大其应用范围。To sum up, the packaging structure with MEMS components of the present invention directly embeds chips in the packaging substrate, so the thickness and volume of the overall packaging structure can be reduced. Furthermore, the present invention electrically connects the chip, the micro-electromechanical element and the package substrate by embedding lines, and its telecommunication transmission efficiency is higher than that of the wire-bonding method, and its manufacturing cost is lower than that of the wire-bonding method. Moreover, the cover body of the present invention can be formed simultaneously with the first electrical connection pad and the first conductive blind hole, so the process steps can be simplified; moreover, compared with the existing QFN type lead frame, the array soldering formed by the present invention Balls can provide more and denser electrical connection points, thereby expanding its application range.

上述实施例是用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应以权利要求书的范围为依据。The above-mentioned embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope of the claims.

Claims (19)

1. an encapsulating structure for tool microcomputer electric component, is characterized in that, comprising:
There is the base plate for packaging of relative first surface and second surface, and this base plate for packaging has:
The first line layer, is formed on first surface;
The second line layer, is formed on second surface;
Conductive through hole, runs through this base plate for packaging and is electrically connected this first line layer and the second line layer;
Chip, is embedded in this base plate for packaging, and on this chip, has multiple electronic padses that expose to this base plate for packaging first surface;
The first dielectric layer, is located on this first surface and chip, and exposes outside this first line layer and electronic pads;
Tertiary circuit layer, is located on this first dielectric layer and is electrically connected this first line layer and electronic pads;
The second dielectric layer, is located on this first dielectric layer and tertiary circuit layer, the perforation that this second dielectric layer surface has recess and runs through this first and second dielectric layer;
Lid, be located at this recess inner edge, with the second dielectric layer top surface of recess periphery, wherein, the cap portion on this second dielectric layer top surface forms lid frame;
The first electric connection pad, is located on this second dielectric layer;
The first conductive blind hole, is located in this perforation and is electrically connected this first line layer and the first electric connection pad;
Then material, is located on this first electric connection pad and this lid frame; And
Base material, has microcomputer electric component and the second electric connection pad be located on substrate surface, and this base material is engaged on this base plate for packaging mode that should recess with this microcomputer electric component.
2. the encapsulating structure of tool microcomputer electric component according to claim 1, is characterized in that, also includes metal frame with this substrate surface of this microcomputer electric component homonymy, and by following corresponding this lid frame that connects of material.
3. the encapsulating structure of tool microcomputer electric component according to claim 1, it is characterized in that, also comprise welding resisting layer, be located on this second dielectric layer and the first electric connection pad, and this welding resisting layer has multiple correspondences exposes the perforate of this first electric connection pad, and then material is formed in this perforate.
4. the encapsulating structure of tool microcomputer electric component according to claim 1, it is characterized in that, also comprise layer reinforced structure, be located on this base plate for packaging second surface, this layer reinforced structure comprises at least one the 3rd dielectric layer, is formed at the 4th line layer and multiple the second conductive blind hole that is formed in the 3rd dielectric layer and is electrically connected the 4th line layer and the second line layer on the 3rd dielectric layer, and outermost the 4th line layer of this layer reinforced structure also has multiple solder ball pads.
5. the encapsulating structure of tool microcomputer electric component according to claim 4, is characterized in that, also comprises welding resisting layer, is located on this layer reinforced structure, has multiple correspondences and expose the respectively welding resisting layer perforate of this solder ball pad in this welding resisting layer.
6. the encapsulating structure of tool microcomputer electric component according to claim 5, is characterized in that, also comprises soldered ball, is located at respectively on this solder ball pad.
7. the encapsulating structure of tool microcomputer electric component according to claim 1, is characterized in that, the material of this second dielectric layer is anti-welding material or photosensitive dielectric material.
8. the encapsulating structure of tool microcomputer electric component according to claim 3, is characterized in that, the material of this welding resisting layer is anti-welding material or photosensitive dielectric material.
9. the encapsulating structure of tool microcomputer electric component according to claim 1, is characterized in that, the material of this base material is siliceous material.
10. a method for making for the encapsulating structure of tool microcomputer electric component, is characterized in that, comprising:
Preparation one has the base plate for packaging of relative first surface and second surface, the first surface of this base plate for packaging and second surface are formed with respectively the first line layer and the second line layer, and be electrically connected this first line layer and the second line layer by running through the conductive through hole of this base plate for packaging, in this base plate for packaging, be embedded with chip, on this chip, there are multiple electronic padses that expose to this base plate for packaging first surface;
On this first surface and chip, sequentially form the first dielectric layer and be electrically connected this electronic pads and the tertiary circuit layer of the first line layer;
On this first dielectric layer and tertiary circuit layer, form the second dielectric layer;
Remove this second dielectric layer of part runs through this first and second dielectric layer perforation to form recess and formation;
This recess inner edge, with recess periphery second dielectric layer top surface form lid, wherein, cap portion on this second dielectric layer top surface forms lid frame, and form the first electric connection pad on this second dielectric layer, and form the first conductive blind hole that is electrically connected this first line layer and the first electric connection pad in this perforation;
On this first electric connection pad and this lid frame, form then material;
Provide a surface to be provided with the base material of microcomputer electric component and the second electric connection pad; And
With this microcomputer electric component, mode that should recess is engaged to this base material and base plate for packaging.
The method for making of the encapsulating structure of 11. tool microcomputer electric components according to claim 10, is characterized in that, also includes metal frame with this substrate surface of this microcomputer electric component homonymy, and by following corresponding this lid frame that connects of material.
The method for making of the encapsulating structure of 12. tool microcomputer electric components according to claim 10, it is characterized in that, before being also included in and forming then material, on this second dielectric layer and the first electric connection pad, form welding resisting layer, and form multiple correspondences and expose the perforate of this first electric connection pad, and then material is formed in this perforate.
The method for making of the encapsulating structure of 13. tool microcomputer electric components according to claim 10, it is characterized in that, also be included on this base plate for packaging second surface and form layer reinforced structure, this layer reinforced structure comprises at least one the 3rd dielectric layer, is formed at the 4th line layer and multiple the second conductive blind hole that is formed in the 3rd dielectric layer and is electrically connected the 4th line layer and the second line layer on the 3rd dielectric layer, and outermost the 4th line layer of this layer reinforced structure also has multiple solder ball pads.
The method for making of the encapsulating structure of 14. tool microcomputer electric components according to claim 13, is characterized in that, is also included on this layer reinforced structure and forms welding resisting layer, and in this welding resisting layer, form multiple correspondences and expose the respectively welding resisting layer perforate of this solder ball pad.
The method for making of the encapsulating structure of 15. tool microcomputer electric components according to claim 14, is characterized in that, is also included in respectively and forms soldered ball on this solder ball pad.
The method for making of the encapsulating structure of 16. tool microcomputer electric components according to claim 15, is characterized in that, also comprises and cuts single technique, to obtain the encapsulating structure of multiple tool microcomputer electric components.
The method for making of the encapsulating structure of 17. tool microcomputer electric components according to claim 10, is characterized in that, the material of this second dielectric layer is anti-welding material or photosensitive dielectric material.
The method for making of the encapsulating structure of 18. tool microcomputer electric components according to claim 12, is characterized in that, the material of this welding resisting layer is anti-welding material or photosensitive dielectric material.
The method for making of the encapsulating structure of 19. tool microcomputer electric components according to claim 10, is characterized in that, the material of this base material is siliceous material.
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