CN106971976B - Array substrate and preparation method thereof - Google Patents

Abstract

The present invention provides an array substrate and a manufacturing method thereof, comprising: manufacturing a second metal layer of the array substrate, the second metal layer is formed by a metal thin film layer after the first yellow light process; covering the second metal layer with a transparent electrode Floor. In the method for manufacturing the above-mentioned array substrate and the array substrate, the transparent electrode layer is directly fabricated on the second metal layer of the array substrate, and the conduction is realized through the direct contact between the second metal layer and the transparent electrode layer, so as to reduce the excessive passivation layer in the prior art. Hole production, thereby reducing a yellow light process to save costs and improve production efficiency.

Description

Array substrate and manufacturing method thereof

technical field

The invention relates to the technical field of liquid crystal displays, in particular to an array substrate and a manufacturing method thereof.

Background technique

Polymer Stabilized Vertically Aligned (Polmer Stabilized Vertically Aligned, PSVA for short) liquid crystal is a new type of liquid crystal display technology. In the traditional PSVA design, the main film layer of the array substrate needs 5 times of yellow light process, which are M1 (ie, the first metal layer), AS (amorphous silicon), M2 (ie, the second metal layer), PV (passivation layer) and ITO, wherein a via hole is provided on the PV layer for conducting M2 and ITO.

In the above-mentioned traditional PSVA design, the manufacturing process of the array substrate has many passes, the manufacturing process is complicated, and the efficiency is low. Therefore, a new method is urgently needed to improve the above-mentioned process.

Contents of the invention

The invention provides an array substrate and a manufacturing method thereof, which are used to solve the technical problems of complex manufacturing process and low efficiency of the array substrate in the prior art.

A method for manufacturing an array substrate provided in one aspect of the present invention includes:

Fabricating the second metal layer of the array substrate, the second metal layer is formed after the metal thin film layer is treated by the first yellow light process;

The transparent electrode layer is covered on the second metal layer.

Further, after covering the transparent electrode layer on the second metal layer, it also includes:

The transparent electrode layer is treated with a second yellow light process, and the pattern of the second mask used in the second yellow light process includes the pattern used when the first yellow light process is performed on the metal thin film layer. The pattern of the first mask plate.

Further, the portion of the second metal layer in contact with the transparent electrode layer includes a portion that has not been etched after the first yellow light process is performed on the metal thin film layer.

Further, before making the second metal layer of the array substrate, it also includes:

A first metal layer is fabricated on the base substrate, and an isolation layer is fabricated on the first metal layer, and the isolation layer covers the grid in the first metal layer.

Further, the isolation layer is an amorphous silicon layer.

Another aspect of the present invention provides an array substrate, including: a second metal layer and a transparent electrode layer directly covering the second metal layer, wherein the second metal layer is composed of a metal thin film layer through a first yellow light layer. Formed after processing.

Further, the pattern of the second mask used when the transparent electrode layer is subjected to the second yellow light process includes the pattern of the first mask used when the metal thin film layer is subjected to the first yellow light process .

Further, the portion of the transparent electrode layer in contact with the second metal layer includes a portion of the metal thin film layer that has not been etched after the first yellow light treatment.

Further, it further includes a first metal layer on the base substrate and an isolation layer on the gate of the first metal layer, and the second metal layer is on the isolation layer.

Further, the isolation layer is an amorphous silicon layer.

In the array substrate manufacturing method and the array substrate provided by the present invention, the transparent electrode layer is directly fabricated on the second metal layer of the array substrate, and conduction is realized through the direct contact between the second metal layer and the transparent electrode layer, so as to reduce bluntness in the prior art. The production of via holes in the chemical layer can reduce a yellow light process to save costs and improve production efficiency.

Description of drawings

Hereinafter, the present invention will be described in more detail based on the embodiments with reference to the accompanying drawings. in:

FIG. 1 is a schematic flow chart of an array substrate manufacturing method provided by Embodiment 1 of the present invention;

FIG. 2 is another schematic flowchart of the method for manufacturing an array substrate provided by Embodiment 1 of the present invention;

FIG. 3 is another schematic flowchart of the method for manufacturing an array substrate provided by Embodiment 1 of the present invention;

FIG. 4 is a schematic structural diagram of the first mask plate of the array substrate provided by Embodiment 2 of the present invention;

FIG. 5 is a schematic structural diagram of a second mask plate of the array substrate provided by Embodiment 2 of the present invention.

In the figures, the same parts are given the same reference numerals. The figures are not drawn to scale.

Detailed ways

The present invention will be further described below in conjunction with accompanying drawing.

Embodiment one

As shown in FIG. 1 , Embodiment 1 of the present invention provides a method for manufacturing an array substrate, including:

In step 101, a second metal layer of the array substrate is fabricated, and the second metal layer is formed by a metal thin film layer treated by a first yellow light process. In the semiconductor industry, silicon wafers or metal thin films are coated, soft-baked, exposed, developed, and hard-baked to make certain patterns. This process is called yellow light, which is one of the fine circuit manufacturing processes. Specifically, the yellow light process (including the first yellow light process and the second yellow light process hereinafter) is a process of processing the metal thin film layer to include at least one pattern, and the specific steps include coating a photoresist on the metal thin film layer, Then use the first mask to expose the photoresist, then use the developer to wash away the photoresist to be etched, and then etch away the metal film part that is not covered with the photoresist, and finally the remaining The lower photoresist is stripped, in this way to obtain the second metal layer, the second metal layer includes the data lines.

Step 102, covering the second metal layer with a transparent electrode layer.

The transparent electrode layer is directly covered on the second metal layer and can be directly connected to the second metal layer. Compared with the prior art, the connection between the second metal layer and the transparent electrode layer is no longer through the second metal layer and the second metal layer. The via holes on the passivation layer between the transparent electrode layers are conducted, therefore, the step of performing yellow light treatment on the passivation layer to form the via holes is reduced, therefore, the array substrate manufacturing method in this embodiment is reduced by one time. The yellow light process saves the cost and improves the production efficiency.

Further, when performing the second yellow light process on the transparent electrode layer, first coat the photoresist on the transparent electrode layer, then use the second mask plate to expose the photoresist, and then use the developing solution to The photoresist to be etched is washed away, and then the part of the transparent electrode layer not covered by the photoresist is further etched away. Since the transparent electrode layer is directly covered on the second metal layer, the photoresist not covered When etching the part of the transparent electrode layer, the second metal layer partially covered by the transparent electrode layer may be damaged, thereby causing damage to the second metal layer and further affecting the performance of the array substrate. Therefore, in order to avoid this problem, as follows: As shown in Figure 2, in a specific embodiment of the present invention, after covering the transparent electrode layer on the second metal layer, it also includes:

Step 103, adopting the second yellow light process to the transparent electrode layer, the pattern of the second mask used in the second yellow light process includes the first mask used in the first yellow light process for the metal thin film layer. Diaphragm graphics.

Since the pattern of the second mask plate includes the pattern of the first mask plate, the transparent electrode layer will not be damaged when the transparent electrode layer part that is not covered with photoresist is etched away. The second metal layer (that is, the unetched part of the second metal layer is covered by the transparent electrode layer).

Further, in another specific embodiment of the present invention, the portion of the second metal layer in contact with the transparent electrode layer includes a portion that is not etched after the first yellow light process is performed on the metal thin film layer. This arrangement means that when the transparent electrode layer is etched, the transparent electrode layer in contact with the second metal layer is not etched to avoid damage to the second metal layer.

Further, as shown in FIG. 3, in a specific embodiment of the present invention, before making the second metal layer of the array substrate, it also includes:

Step a, forming a first metal layer on the base substrate, and forming an isolation layer on the first metal layer, the isolation layer covering the gate in the first metal layer. The first metal layer is formed after the metal thin film layer is treated by a yellow light process, and includes gates and gate lines. After step a is completed, a second metal layer is formed on the first metal layer and the isolation layer. The isolation layer is an amorphous silicon layer to isolate the gate in the first metal layer from the second metal layer.

Embodiment two

An embodiment of the present invention provides an array substrate, including: a second metal layer and a transparent electrode layer directly covering the second metal layer, wherein the second metal layer is formed by a metal thin film layer treated by a first yellow light process.

Further, the pattern of the second mask 2 used when the transparent electrode layer is subjected to the second yellow light process includes the pattern of the first mask 1 used when the metal thin film layer is subjected to the first yellow light process. As shown in Fig. 4 and Fig. 5, Fig. 4 is the figure of the first mask plate 1, and Fig. 5 is the figure of the second mask plate 2, and this figure includes the figure of the first mask plate 1 (the first mask plate The pattern of the plate 1 is composed of the part of the second metal layer that has not been etched away), so that the second metal layer will not be damaged when the transparent electrode layer is etched.

Furthermore, in another specific embodiment of the present invention, the portion of the transparent electrode layer in contact with the second metal layer includes a portion of the metal thin film layer that has not been etched after the first yellow light process.

Further, in another specific embodiment of the present invention, the above-mentioned array substrate further includes a first metal layer on the base substrate and an isolation layer on the gate of the first metal layer, and the second metal layer is located on the isolation layer. above. This part is consistent with the setting of the prior art, and will not be repeated here. Further, the isolation layer is an amorphous silicon layer to isolate the second metal layer from the gate of the first metal layer.

While the invention has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for parts thereof without departing from the scope of the invention. In particular, as long as there is no structural conflict, the technical features mentioned in the various embodiments can be combined in any manner. The present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims (8)

1. A method for manufacturing an array substrate, comprising: Fabricating the second metal layer of the array substrate, the second metal layer is formed after the metal thin film layer is treated by the first yellow light process; A transparent electrode layer is covered on the second metal layer, and a second yellow light process is used for the transparent electrode layer. The pattern of the second mask used in the second yellow light process includes the metal The pattern of the first mask plate used when the thin film layer is processed by the first yellow light process. 2. The method for manufacturing the array substrate according to claim 1, wherein the part where the second metal layer is in contact with the transparent electrode layer includes the metal thin film layer that has not been treated by the first yellow light process. etched part. 3. The method for fabricating an array substrate according to any one of claims 1 or 2, further comprising: before fabricating the second metal layer of the array substrate: A first metal layer is fabricated on the base substrate, and an isolation layer is fabricated on the first metal layer, and the isolation layer covers the grid in the first metal layer. 4. The method for manufacturing the array substrate according to claim 3, wherein the isolation layer is an amorphous silicon layer. 5. An array substrate, characterized in that it comprises: a second metal layer and a transparent electrode layer directly covering the second metal layer, wherein the second metal layer is composed of a metal thin film layer through the first yellow light Formed after process treatment, the transparent electrode layer is treated by a second yellow light process, and the pattern of the second mask used in the second yellow light process includes performing the first yellow light process on the metal thin film layer The pattern of the first mask plate used at the time. 6. The array substrate according to claim 5, wherein the part of the transparent electrode layer in contact with the second metal layer includes that the metal thin film layer has not been etched after the first yellow light process. part. 7. The array substrate according to any one of claims 5-6, further comprising a first metal layer on the base substrate and an isolation layer on the gate in the first metal layer , the second metal layer is located on the isolation layer. 8. The array substrate according to claim 7, wherein the isolation layer is an amorphous silicon layer.