CN103295961B - Array base palte, its manufacture method and display unit - Google Patents

Abstract

The embodiment of the invention discloses an array substrate, its manufacturing method and a display device, which relate to the field of liquid crystal display technology, and solve the problem of using semi-permeable masks or gray masks in order to reduce the number of common masks used in the prior art when manufacturing array substrates. The problem of increased process control difficulty caused by step mask plates. The method includes: forming a gate metal layer on a substrate, forming a pattern including a gate and a gate line through a patterning process; sequentially forming an insulating layer, a semiconductor material layer, and a source/drain on the substrate on which the gate and gate line patterns are formed The metal layer is formed into a pattern comprising a semiconductor layer, a source/drain electrode and a data line through a patterning process, wherein the pattern of the source/drain electrode is consistent with the pattern of the semiconductor layer; A first transparent conductive layer is formed on the substrate, a pattern of the first transparent electrode is formed through a patterning process, and a gap is formed on the pattern of the source/drain electrode to form a pattern of the source electrode and the drain electrode.

Description

Array substrate, its manufacturing method and display device

technical field

The invention relates to the technical field of liquid crystal display, in particular to an array substrate, a manufacturing method thereof and a display device.

Background technique

The liquid crystal panel of a thin film transistor liquid crystal display device includes an array substrate as shown in FIG. 1, wherein the structure of the array substrate is shown in FIG. A pixel area is defined between 12, and a thin film transistor (as shown in a dotted circle in FIG. 1 ) and a pixel electrode 13 are arranged in the pixel area. The gate 14 of the thin film transistor is electrically connected to the gate line 11 , the source (not shown in the figure) is connected to the data line 12 , and the drain (not shown in the figure) is electrically connected to the pixel electrode 13 .

The prior art usually adopts a 5MASK (five times mask) patterning process to prepare the array substrate. In the first patterning process, the first common mask plate is used to form the pattern of the gate 14 and the grid line 11, and the second patterning process The second common mask plate is used in the process to form the pattern of the semiconductor layer, the third patterning process uses the third common mask plate to form the pattern of the drain electrode, the source electrode and the data line 12, and the fourth patterning process uses The fourth common mask is used to form the pattern of the drain via hole, and the fifth patterning process uses the fifth common mask to form the pattern of the pixel electrode 13 .

In order to reduce the number of masks used to reduce the cost of the process, the prior art proposes to use a semi-permeable mask or a grayscale mask to replace the ordinary mask, that is, the second part of the 5MASK patterning process The ordinary mask and the third ordinary mask are replaced by a semi-permeable mask or a grayscale mask, and only one patterning process is required to form the patterns of the semiconductor layer, drain, source and data lines, The number of mask books used to prepare the array substrate is reduced to four.

However, due to the use of a semi-permeable mask or a grayscale mask in the above method, the difficulty of process control is significantly increased, so the process cost has not been significantly reduced.

Contents of the invention

Embodiments of the present invention provide an array substrate, its manufacturing method, and a display device, which solve the problems caused by the use of semi-transparent masks or grayscale masks in order to reduce the number of common masks used in the manufacture of array substrates in the prior art. The problem of increased difficulty in process control.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

A method for manufacturing an array substrate, comprising: forming a gate metal layer on a substrate, forming a pattern including a gate and a gate line through a patterning process; Insulating layer, semiconductor material layer and source/drain metal layer, forming a pattern including semiconductor layer, source/drain electrode and data line through a patterning process, wherein the pattern of the source/drain electrode is consistent with the pattern of the semiconductor layer; A first transparent conductive layer is formed on the substrate on which the semiconductor layer, source/drain electrodes and data line patterns are formed, a pattern of the first transparent electrode is formed through a patterning process, and gaps are formed on the pattern of the source/drain electrodes to Pattern the source and drain electrodes.

Further, the manufacturing method of the array substrate further includes: forming a passivation layer on the substrate on which the patterns of the source electrode, the drain electrode and the first transparent electrode are formed, and forming a passivation layer including an exposed gate line in the peripheral lead area through a patterning process. The via hole of the lead wire and the pattern of the via hole exposing the lead wire of the data line; the second transparent conductive layer is formed on the passivation layer formed with the via hole pattern of the gate line lead wire and the data line lead wire, and is formed by a patterning process The pattern of the second transparent electrode, wherein the second transparent electrode is a slit-shaped electrode.

Wherein, an insulating layer, a semiconductor material layer, and a source/drain metal layer are sequentially formed on the substrate on which the gate and the gate line patterns are formed, and the semiconductor layer, source/drain electrodes, and data lines are formed through a patterning process. The pattern of the source/drain electrode is consistent with the pattern of the semiconductor layer, specifically including: forming an insulating layer, a semiconductor layer, and a source electrode at a time on the substrate on which the gate and the gate line patterns are formed. /drain metal layer; coating photoresist on the substrate with the source/drain metal layer, exposing and developing the photoresist through a common mask, wherein the photoresist is completely reserved and correspondingly formed The region of the source/drain electrode pattern and the region where the data line pattern is formed, and other regions are completely removed regions of photoresist; etching is performed on the completely removed regions of photoresist, and the source/drain metal is sequentially removed Layer and semiconductor layer; strip the photoresist in the completely reserved area of the photoresist to form the pattern of the semiconductor layer, the pattern of the source/drain electrode, and the pattern of the data line, wherein the source/drain The pattern of the poles is consistent with the pattern of the semiconductor layer.

In addition, the first transparent conductive layer is formed on the substrate on which the semiconductor layer, source/drain electrodes and data line patterns are formed, the pattern of the first transparent electrode is formed through a patterning process, and the pattern of the first transparent electrode is formed on the source/drain electrodes. gaps are formed on the pattern to form the pattern of the source electrode and the drain electrode, and the specific process includes: forming a first transparent conductive layer on the substrate on which the semiconductor layer, source/drain electrodes and data line patterns are formed; A photoresist is coated on the substrate of the first transparent conductive layer, and the photoresist is exposed and developed through a common mask plate, wherein the photoresist completely reserved area corresponds to the area where the first transparent electrode pattern is formed, Other areas are photoresist completely removed regions; first etching is performed on the photoresist completely removed regions, and the first transparent conductive layer is removed to form the first transparent electrodes; the photoresist is completely removed Performing a second etching on the removed area to remove the semiconductor layer not covered by the data line pattern; performing a third etching on the completely removed area of the photoresist to form a gap on the pattern of the source/drain electrode to form the source and drain patterns.

Preferably, after sequentially forming an insulating layer and a semiconductor layer on the substrate on which the gate and the gate line patterns are formed, and before forming the source/drain metal layer, further comprising: forming the semiconductor material layer An ohmic contact layer is formed on the substrate; the pattern of the ohmic contact layer is consistent with the pattern of the source electrode and the drain electrode.

Further, when forming the pattern including the gate and the gate line through the patterning process, it also includes forming the pattern of the common electrode line.

An array substrate, made by the above-mentioned method for manufacturing an array substrate, comprising a pattern of a gate and a gate line; a pattern of a semiconductor layer; a pattern of a source electrode, a drain electrode, and a data line, and a pattern of a transparent electrode formed sequentially on the substrate. pattern, the transparent electrode directly overlaps the drain.

Preferably, a drain ohmic contact layer is formed between the drain and the semiconductor layer.

Further, the array substrate further includes a pattern of common electrode lines, and the pattern of the common electrode lines is formed on the same layer as the patterns of the gate and gate lines.

Moreover, a passivation layer and a slit-shaped second transparent electrode are also arranged on the first transparent electrode.

A display device includes the above-mentioned array substrate.

In the array substrate, its manufacturing method, and display device provided by the embodiments of the present invention, since the first transparent conductive layer is directly formed on the substrate with source/drain electrodes and data lines, the first transparent electrodes, The patterns of the source and the drain allow the first transparent electrode to directly overlap the drain, eliminating the need for a mask for making pixel electrode via holes in the prior art. In addition, since only a common mask is used Just in the patterning process of forming the first transparent electrode, the source and drain electrodes are formed by forming gaps on the pattern of the source/drain electrodes, so this method only uses three common masks, compared to In the prior art, not only one less mask is used, but also grayscale masks are unnecessary, so that the difficulty and cost of process control are significantly reduced.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings that are required in the description of the embodiments or the prior art.

FIG. 1 is a top view of an existing array substrate;

FIG. 2 is a flow chart of a method for manufacturing an array substrate provided by an embodiment of the present invention;

FIG. 3 is a flowchart of another method for manufacturing an array substrate provided by an embodiment of the present invention;

4 is a cross-sectional view of a thin film transistor region on a substrate provided with a gate and a gate line pattern according to an embodiment of the present invention;

5 is a cross-sectional view of a thin film transistor region on a substrate formed with semiconductor layers and source/drain electrode patterns provided by an embodiment of the present invention;

6 is a cross-sectional view of a data line region on a substrate formed with data lines provided by an embodiment of the present invention;

7 is a cross-sectional view of a thin film transistor region on a substrate provided with a first transparent electrode pattern according to an embodiment of the present invention;

8 is a cross-sectional view of a data line region on a substrate formed with a first transparent electrode pattern provided by an embodiment of the present invention;

9 is a cross-sectional view of the data line region on the substrate with the semiconductor layer wings removed according to an embodiment of the present invention;

FIG. 10 is a cross-sectional view of a thin film transistor region on a substrate formed with a source and a drain provided by an embodiment of the present invention.

detailed description

An embodiment of the present invention provides a method for manufacturing an array substrate, as shown in FIG. 2 , including the following steps. The patterning process mentioned therein includes processes such as photoresist coating, masking, exposure, etching and photoresist stripping, and the photoresist is an example of a positive photoresist.

201. Form a gate metal layer on a substrate, and form a pattern including a gate and a gate line through a patterning process.

Specifically, a first common mask is used in the patterning process of this step, so as to form the pattern of the gate and the pattern of the gate line.

202. Form an insulating layer, a semiconductor material layer, and a source/drain metal layer sequentially on the substrate on which the gate and gate line patterns are formed, and form a pattern including the semiconductor layer, source/drain electrodes, and data lines through a patterning process, wherein the source/drain The pattern of the drain electrode coincides with the pattern of the semiconductor layer.

In the patterning process of this step, a second common mask is used, and the source/drain metal layer and the semiconductor layer are sequentially etched through the patterning process to form patterns including the semiconductor layer and patterns of the source/drain electrodes and data lines, specifically Specifically, in the area where the thin film transistor is formed, the etched source/drain metal layer forms the pattern of the source/drain electrode, and forms the pattern of the semiconductor layer below it, and the two patterns are consistent. Outside the region where the thin film transistor is formed, the etched source/drain metal layer forms the pattern of the data line.

203. Form a first transparent conductive layer on the substrate on which the semiconductor layer, source/drain electrodes, and data line patterns are formed, form the pattern of the first transparent electrode through a patterning process, and form gaps on the pattern of the source/drain electrodes to form Patterns of source and drain electrodes.

Specifically, a third common mask is used in the patterning process of this step, and a photoresist is coated on the substrate on which the first transparent conductive layer is formed. After exposing and developing through the third mask, a photoresist is formed. The glue completely removed region, the photoresist completely reserved region corresponds to the pattern of the first transparent electrode, the completely removed region corresponds to the region including the gap between the source electrode and the drain electrode to be formed, and other regions.

Firstly, the first transparent conductive layer in the region where the photoresist is completely removed is etched to form a pattern of the first first transparent electrode.

Then etch the semiconductor layer not covered by the source/drain metal layer in the region where the photoresist is completely removed, to remove the redundant semiconductor layer, especially for the semiconductor layer below the data line, etch to make the semiconductor layer The width of the layer is equal to the width of the data lines.

Etching the source/drain metal layer in the region where the photoresist is completely removed, including etching the gap region between the source electrode and the drain electrode to be formed, forming on the pattern of the source/drain electrode Gap to form the pattern of the source and drain electrodes. Specifically, when etching the source/drain electrode, the pattern of the source/drain electrode is divided into two parts by forming a gap on the pattern of the source/drain electrode, thereby forming the source electrode pattern and the pattern of the drain.

In the manufacturing method of the array substrate provided by the embodiment of the present invention, since the first transparent conductive layer is directly formed on the substrate with source/drain electrodes and data lines, the first transparent electrodes, source electrodes, and drain electrodes are formed after the patterning process. pole pattern, so that the first transparent electrode can be directly overlapped on the top of the drain electrode, eliminating the need for a mask plate for making pixel electrode via holes in the prior art. In addition, since only a common mask plate is used to form the second In the patterning process of a transparent electrode, the source electrode and the drain electrode are formed by forming a gap on the pattern of the source/drain electrode, so this method only uses three common mask plates, compared with the prior art, Not only one less mask is used but also no gray-scale mask is needed, which significantly reduces the difficulty and cost of process control.

Because in general, for the process of forming the data line and the semiconductor layer at the same time, the width of the data line will be smaller than the width of the semiconductor layer below it, especially when the first transparent conductive layer is etched, it will be affected by the etching solution. , the width of the data line will decrease again, so that the semiconductor layer under the data line will be exposed more, which will affect the design width of the subsequent pixel electrode and data line, that is, in order to avoid poor process, only the data line and the pixel electrode The gap (interval) design is wider. In addition, in the general process, when forming the source/drain electrode layer and the pattern of the data line, the source and drain are directly formed, so that if the semiconductor layer under the data line is etched again, the source and drain The semiconductor in the gap (channel part) will also be affected, and the result is that the characteristics of the thin film transistor are affected or even unable to work.

However, in the preparation method of the array substrate provided by the embodiment of the present invention, especially in the patterning process of the first transparent electrode, before the source electrode and the drain electrode are formed, the semiconductor layer below it is formed by the source/drain electrode pattern. At the same time of protection, the semiconductor layer under the data line that is not protected by the source/drain metal layer is etched to eliminate the redundant semiconductor layer, which can reduce the design restrictions of the pixel electrode and the data line, and increase the aperture ratio.

The manufacturing method will be described in detail below with reference to FIGS. 3 to 10 .

301. Form a gate metal layer on the substrate 31, and form a pattern including the gate 32, gate lines and common electrode lines through a patterning process.

FIG. 4 is a cross-sectional view of the TFT region after the patterning process. A gate metal layer is deposited on a substrate 31 (such as a glass substrate or a quartz substrate) by magnetron sputtering or thermal evaporation, and a common mask plate is used to form a patterning process including a gate 32 and a grid line (Fig. not shown in the figure) and the pattern of the common electrode line (not shown in the figure). The gate 32 is connected to the gate line, and the common electrode line is parallel to the gate line. Among them, the function of the common electrode line is to make the common electrode have a smaller signal delay. The common electrode can be formed on the array substrate or the color filter substrate. Of course, the common electrode line is not a necessary structure, and it can be formed according to actual Setup is required.

302 . Form an insulating layer, a semiconductor material layer, and a source/drain metal layer at one time on the substrate 31 formed with gate and gate line patterns.

303. Coat photoresist on the substrate 31 on which the semiconductor material layer and the source/drain metal layer are formed, and expose and develop the photoresist through a common mask, in which the photoresist completely reserved area corresponds to the formation of the source/drain The area where the pattern of the drain electrode 34 and the area where the pattern of the data line 35 is formed, and the other areas are areas where the photoresist is completely removed.

304. Etching the photoresist completely removed region, and sequentially removing the source/drain metal layer and the semiconductor layer.

305, peel off the photoresist in the photoresist completely reserved area, form the pattern of the semiconductor layer 33, the pattern of the source/drain electrode 34, and the pattern of the data line 35, wherein the pattern of the source/drain electrode 34 is consistent with the pattern of the semiconductor layer 33 unanimous.

Through the patterning process from step 303 to step 305, the semiconductor layer and the source/drain metal layer formed in step 302 are patterned to form the pattern of the source/drain electrode 34 and the pattern of the semiconductor layer 33 in FIG. The pattern of the data line 35 in FIG. 6 is defined, and the pattern of the source/drain electrode 34 forms a protective layer for the semiconductor layer 33 in a subsequent process.

306 , forming a first transparent conductive layer on the substrate 31 on which patterns of the semiconductor layer 33 , source/drain electrodes 34 and data lines 35 are formed.

307. Coat photoresist 37 on the substrate on which the first transparent conductive layer is formed, expose and develop the photoresist 37 through a common mask plate, wherein the photoresist completely reserved area corresponds to the first transparent electrode pattern area, and other areas are photoresist completely removed areas.

308 . Perform a first etching on the region where the photoresist is completely removed, and remove the first transparent conductive layer, so as to form the first transparent electrode 36 .

FIG. 7 is a cross-sectional view of the thin film transistor region after the first etching process, and FIG. 8 is a cross-sectional view of the data line region after the first etching process. In FIG. 8 , a pattern of the first transparent electrode 36 is formed under the photoresist completely reserved area, below the pattern is the pattern of the data line 35 formed in steps 302 to 305 , and the semiconductor layer 38 below the pattern. There is a part not covered by the data line 35 on both sides of the semiconductor layer 38, and this part is called the semiconductor layer wing (ActiveWing). For signal interference on the first transparent electrode 36 , when designing the size of the first transparent electrode 36 , it must be ensured that there is a certain distance between it and the semiconductor layer wing. This makes the size design of the first transparent electrode 36 limited by the semiconductor layer wing, thereby affecting the pixel aperture ratio of the array substrate, and further degrading the performance of the liquid crystal panel using the array substrate.

In order to avoid the above adverse effects caused by the existence of the semiconductor layer wings, the embodiment of the present invention adopts the following step 309 to remove the semiconductor layer wings without damaging the formed structure of the thin film transistor region.

309 , performing a second etching on the region where the photoresist is completely removed, and removing the semiconductor layer 38 not covered by the pattern of the data line 35 .

FIG. 9 is a cross-sectional view of the data line region after the second etching process. Wherein, the semiconductor layer wing is the semiconductor layer 38 not covered by the pattern of the data line 35 in this figure.

In this step, the photoresist 37 that forms the pattern of the first transparent electrode 36 is still used, and the semiconductor layer 38 that is not covered by the pattern of the data line 35 is etched. The material reacts, therefore, in the thin film transistor region shown in FIG. 7 , even if part of the source/drain gold electrode 34 is not covered by the photoresist 37 , it will not be etched. Therefore, in this step, only the exposed semiconductor layer 38 in the data line region will be etched away, so that the width of the data line 35 is equal to that of the semiconductor layer 381 after removing the semiconductor layer wings.

310 , perform a third etching on the photoresist completely removed region, and form a gap on the pattern of the source/drain electrode to form the pattern of the source electrode and the drain electrode.

FIG. 10 is a cross-sectional view of the TFT region after the third etching process. In this step, the photoresist 37 for forming the pattern of the first transparent electrode 36 is still used. In FIG. 10 , the photoresist 37 has an opening, and the source/drain electrode 34 exposed by the opening is etched. Since all metal layers (data lines 35 and first transparent electrodes 36) are covered by photoresist 37 in the data line region shown in FIG. Parts of the structure of the district will not be affected. When the exposed source/drain electrode 34 is etched away, a gap 39 is formed on the pattern of the source/drain electrode 34, so that the source/drain electrode 34 is divided into two parts, which are respectively the source electrode 341 and the drain electrode of the thin film transistor. Pole 342.

311. Form a passivation layer on the substrate 31 on which the patterns of the source electrode 341, the drain electrode 342, and the first transparent electrode 36 are formed, and form via holes including exposed gate line leads and exposed data line leads in the peripheral lead area through a patterning process The pattern of the vias.

312. Form a second transparent conductive layer on the passivation layer formed with patterns of gate line via holes and data line via holes, and form a pattern of a second transparent electrode through a patterning process, wherein the second transparent electrode is a slit-shaped electrode .

Through steps 311 and 312 , a second transparent electrode is formed on the first transparent electrode 36 via a passivation layer, and the second transparent electrode is a slit-shaped electrode. The array substrate with this structure is called a horizontal electric field driven array substrate. When a voltage is applied to the two transparent electrodes, an electric field parallel to the direction of the substrate will be formed on the second transparent electrode. Usually, the first transparent electrode is called a pixel electrode, which can be a slit-shaped electrode or a plate-shaped electrode, and the second transparent electrode is called a common electrode, which must be a slit-shaped electrode.

When the common electrode lines are formed in step 301, by connecting the common electrode lines to the common electrodes, the signal delay of the common electrodes can be reduced.

In step 302 of the manufacturing method of the array substrate provided in the above embodiment, after forming the insulating layer and the semiconductor material layer, and before forming the source/drain metal layer, it may further include: forming an ohmic contact layer on the substrate on which the semiconductor material layer is formed .

Then in step 304, the source/drain metal layer, the ohmic contact layer and the semiconductor material layer are sequentially removed by etching, and then the photoresist in the completely reserved region of the photoresist is stripped in step 305, and the semiconductor layer and the semiconductor layer are formed. The pattern of the ohmic contact layer between the source/drain electrode layers also coincides with the pattern of the semiconductor layer.

Then in step 310, after forming a gap on the pattern of the source/drain electrode to form the pattern of the source electrode and the drain electrode, the etching is continued to remove the ohmic contact layer exposed under the gap on the source/drain electrode pattern, so that the ohmic A gap is formed on the pattern of the contact layer, and the gap divides the ohmic contact layer into two parts, namely a drain ohmic contact layer located between the drain and the semiconductor layer and a source ohmic contact layer located between the source and the semiconductor layer, Thus, the pattern of the finally formed ohmic contact layer is consistent with the pattern of the source and drain.

The contact resistance between the semiconductor layer and the drain can be reduced by providing the drain ohmic contact layer, and similarly, the contact resistance between the semiconductor layer and the source can be reduced by providing the source ohmic contact layer.

The embodiment of the present invention also provides an array substrate, which is manufactured by the method for manufacturing the array substrate provided in the above embodiment. As shown in FIG. 10 , the array substrate includes gates sequentially formed on the substrate 31 32 and the pattern of the gate line; the pattern of the semiconductor layer 33; the pattern of the source electrode 341, the drain electrode 342 and the data line 35 and the pattern of the first transparent electrode 36, and the first transparent electrode 36 directly overlaps the drain electrode 342.

In the array substrate provided in the embodiments of the present invention, the cost is significantly reduced due to the adoption of the method for manufacturing the array substrate provided in the above embodiments.

In the array substrate provided in the above embodiments, a drain ohmic contact layer may be formed between the drain 342 and the semiconductor layer 33 , and the contact resistance between the semiconductor layer 33 and the drain 342 may be reduced by providing the drain ohmic contact layer.

The array substrate provided in the above embodiments may further include a pattern of common electrode lines, and the pattern of the common electrode lines is formed in the same layer as the patterns of the gate and gate lines. By connecting the common electrode line to the common electrode, the signal delay of the common electrode can be reduced.

In the array substrate provided in the above embodiments, a passivation layer and a slit-shaped second transparent electrode may also be disposed on the first transparent electrode 36 . The second transparent electrode is the common electrode.

An embodiment of the present invention also provides a display device, which includes the array substrate described in the above embodiments. Due to the use of the array substrate described in the above embodiments, the display device also has a lower manufacturing cost.

The embodiments of the present invention are mainly used in the manufacture of liquid crystal display products.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (10)

1. A method for manufacturing an array substrate, comprising: Form a gate metal layer on the substrate, and form a pattern including a gate and a gate line through a patterning process; An insulating layer, a semiconductor material layer, and a source/drain metal layer are sequentially formed on the substrate on which the gate and the gate line patterns are formed, and a pattern including the semiconductor layer, source/drain electrodes, and data lines is formed through a patterning process, wherein The pattern of the source/drain electrode is consistent with the pattern of the semiconductor layer; Form a first transparent conductive layer on the substrate on which the semiconductor layer, source/drain electrodes and data line patterns are formed, form a pattern of the first transparent electrode through a patterning process, and form gaps on the pattern of the source/drain electrodes to form source and drain patterns; The first transparent conductive layer is formed on the substrate on which the semiconductor layer, source/drain electrodes and data line patterns are formed, the pattern of the first transparent electrode is formed through a patterning process, and the pattern of the source/drain electrode is formed on the pattern of the source/drain electrode. Forming gaps to form source and drain patterns, the specific process includes: forming a first transparent conductive layer on the substrate formed with the semiconductor layer, source/drain electrodes and data line patterns; A photoresist is coated on the substrate on which the first transparent conductive layer is formed, and the photoresist is exposed and developed through a common mask plate, wherein the photoresist completely reserved area corresponds to the formation of the first transparent The area of the electrode pattern, and the other areas are the areas where the photoresist is completely removed; Performing a first etching on the photoresist completely removed region to remove the first transparent conductive layer to form the first transparent electrode; performing a second etching on the completely removed region of the photoresist to remove the semiconductor layer not covered by the data line pattern; A third etching is performed on the completely removed region of the photoresist, and a gap is formed on the pattern of the source/drain electrode to form a pattern of the source electrode and the drain electrode. 2. The method for manufacturing an array substrate according to claim 1, further comprising: A passivation layer is formed on the substrate on which the patterns of the source electrode, the drain electrode, and the first transparent electrode are formed, and a via hole exposing the gate line lead and a pass exposing the data line lead are formed in the peripheral lead area through a patterning process. hole pattern; A second transparent conductive layer is formed on the passivation layer formed with patterns of the gate line via holes and data line via holes, and a pattern of a second transparent electrode is formed through a patterning process, wherein the second transparent electrode is Slit electrodes. 3. The method for manufacturing an array substrate according to claim 1, wherein an insulating layer, a semiconductor material layer, and a source/drain metal layer are sequentially formed on the substrate on which the gate electrode and the gate line pattern are formed. layer, forming a pattern including a semiconductor layer, a source/drain electrode and a data line through a patterning process, wherein the pattern of the source/drain electrode is consistent with the pattern of the semiconductor layer, specifically including: forming an insulating layer, a semiconductor layer and a source/drain metal layer at one time on the substrate on which the gate and the gate line pattern are formed; Coat photoresist on the substrate on which the source/drain metal layer is formed, and expose and develop the photoresist through a common mask plate, wherein the completely reserved area of photoresist corresponds to the formation of the source/drain The area of the electrode pattern and the area where the data line pattern is formed, and the other areas are completely removed areas of photoresist; Etching the region where the photoresist is completely removed, sequentially removing the source/drain metal layer and the semiconductor layer; stripping the photoresist in the completely reserved region of the photoresist, forming the pattern of the semiconductor layer, the pattern of the source/drain electrode, and the pattern of the data line, wherein the pattern of the source/drain electrode is consistent with the pattern of the The pattern of the above-mentioned semiconductor layer is the same. 4. The method for manufacturing an array substrate according to any one of claims 1-3, wherein an insulating layer and a semiconductor material layer are sequentially formed on the substrate on which the gate electrode and the gate line pattern are formed. After that, before forming the source/drain metal layer, the method further includes: forming an ohmic contact layer on the substrate on which the semiconductor material layer is formed; the pattern of the ohmic contact layer is consistent with the pattern of the source electrode and the drain electrode. 5. The method for manufacturing the array substrate according to any one of claims 1-3, characterized in that, when forming the pattern including the gate and the gate line through the patterning process, it further comprises forming the pattern of the common electrode line. 6. An array substrate, characterized in that it is made by the manufacturing method of the array substrate according to any one of claims 1-5, comprising the pattern of the gate and the gate line sequentially formed on the substrate; the pattern of the semiconductor layer ; the pattern of the source electrode, the drain electrode and the data line and the pattern of the first transparent electrode, and the first transparent electrode directly overlaps the drain electrode. 7. The array substrate according to claim 6, wherein a drain ohmic contact layer is formed between the drain and the semiconductor layer. 8 . The array substrate according to claim 6 , further comprising a pattern of common electrode lines, and the pattern of the common electrode lines is formed in the same layer as the patterns of the gate and gate lines. 9 . The array substrate according to claim 6 , wherein a passivation layer and a slit-shaped second transparent electrode are further disposed on the first transparent electrode. 10. A display device, comprising the array substrate according to any one of claims 6-9.