CN106847874A - The forming method of the semiconductor devices with different threshold voltages - Google Patents

Abstract

A method for forming a semiconductor device having different threshold voltages, comprising: providing a substrate including a first region and a second region, the first region and the second region having the same region type; performing a first threshold voltage adjustment on the first region substrate Doping treatment; forming a gate dielectric layer on the substrate surface of the first region and the second region; forming a first work function layer covering the surface of the gate dielectric layer in the first region and the second region, and the first work function layer has a first thickness; Thinning the first work function layer in the first region, so that the first work function layer in the first region has a second thickness; forming a first gate electrode layer on the surface of the first work function layer with the second thickness; A second gate electrode layer is formed on the surface of the first work function layer in the second region. The present invention increases the threshold voltage difference between the MOS transistors formed in the first region and the MOS transistors formed in the second region, thereby improving the threshold voltage difference of the semiconductor device and meeting the requirements of device performance.

Description

Method for forming semiconductor devices with different threshold voltages

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming semiconductor devices with different threshold voltages.

Background technique

The main semiconductor device of an integrated circuit, especially a very large scale integrated circuit, is a metal-oxide-semiconductor field effect transistor (MOS transistor). With the continuous development of integrated circuit manufacturing technology, the technology nodes of semiconductor devices are continuously reduced, and the geometric dimensions of semiconductor structures are continuously reduced following Moore's law. When the size of the semiconductor structure is reduced to a certain extent, various secondary effects caused by the physical limit of the semiconductor structure appear one after another, and it becomes more and more difficult to scale down the feature size of the semiconductor structure. Among them, in the field of semiconductor manufacturing, the most challenging thing is how to solve the problem of large leakage current in semiconductor structures. The large leakage current of the semiconductor structure is mainly caused by the continuous reduction of the thickness of the traditional gate dielectric layer.

The currently proposed solution is to replace the traditional silicon dioxide gate dielectric material with a high-k gate dielectric material, and use metal as the gate electrode to avoid the Fermi level pinning effect between the high-k material and the traditional gate electrode material and boron penetration effect. The introduction of the high-k metal gate reduces the leakage current of the semiconductor structure.

Threshold voltage (Vt) is one of the important parameters of MOS transistors, and there are different requirements for threshold voltages of different MOS transistors in the prior art. However, in the semiconductor devices formed in the prior art, the threshold voltage difference of different MOS transistors is small, and the range of the threshold voltage difference in the semiconductor device is not enough to meet the requirements of the device.

Although the introduction of a high-k metal gate can improve the electrical performance of the semiconductor structure to a certain extent, the electrical performance of the semiconductor structure formed in the prior art still needs to be improved.

Contents of the invention

The problem to be solved by the present invention is to provide a method for forming semiconductor devices with different threshold voltages, which increases the threshold voltage difference between the devices formed in the first region and the second region, thereby obtaining a semiconductor device with a larger threshold voltage difference.

In order to solve the above problems, the present invention provides a method for forming a semiconductor device with different threshold voltages, including: providing a substrate, the substrate includes a first region and a second region, and the region types of the first region and the second region Same; perform first threshold voltage adjustment doping treatment on the base of the first region; form a gate dielectric layer on the substrate surface of the first region and the second region; form a gate covering the first region and the second region The first work function layer on the surface of the dielectric layer, the first work function layer has a first thickness; the first work function layer in the first region is thinned, so that the first work function layer in the first region has second thickness; forming a first gate electrode layer on the surface of the first work function layer with the second thickness; forming a second gate electrode layer on the surface of the first work function layer in the second region.

Optionally, before forming the first work function layer, a capping layer is formed on the surface of the gate dielectric layer; an etching stop layer is formed on the surface of the capping layer.

Optionally, a dry etching process is used to thin the first work function layer in the first region.

Optionally, the process step of performing the thinning treatment includes: forming a pattern layer on the surface of the first work function layer in the second region; using the pattern layer as a mask, The work function layer is subjected to a dry etching process; the pattern layer is removed.

Optionally, the first region is a PMOS region; the second region is a PMOS region; the dopant ions in the first threshold voltage adjustment doping treatment are N-type ions; the material of the first work function layer It is a P-type work function material.

Optionally, the doping ions of the first threshold voltage adjustment doping treatment are P or As; the material of the first work function layer is one or more of Ta, TiN, TaSiN or TiSiN.

Optionally, the first region is an NMOS region; the second region is an NMOS region; the dopant ions in the threshold voltage adjustment doping treatment are P-type ions; the material of the first work function layer is N work function materials.

Optionally, the doping ions of the threshold voltage adjustment doping treatment are B, Ga or In; the material of the first work function layer is one of TiAl, TiAlC, TaAlN, TiAlN, MoN, TaCN or AlN or several.

Optionally, the first thickness is 30 angstroms to 60 angstroms; the second thickness is 15 angstroms to 30 angstroms.

Optionally, the first region further includes several subregions, wherein the substrates of the several subregions are subjected to the first threshold voltage adjustment doping treatment, and the substrates of the several subregions are subjected to the first threshold voltage The doping concentration of the adjustment doping process varies.

Optionally, the several sub-regions include a pull-up transistor region, an input-output transistor region, a standard threshold voltage region, and a low threshold voltage region; the second region is an ultra-low threshold voltage region.

Optionally, the several sub-regions include a pull-down transistor region, an input-output transistor region, a pass-gate transistor region, a standard threshold voltage region, and a low threshold voltage region; the second region is an ultra-low threshold voltage region.

Optionally, among the gate dielectric layers on the base surface of the several sub-regions, the gate dielectric layer located on the base surface of the input-output transistor region has the thickest thickness.

Optionally, the gate dielectric layer in the input-output transistor region includes an oxide layer and a high-k gate dielectric layer located on the surface of the oxide layer; the gate dielectric layer outside the input-output transistor region in the first region includes an interface layer and a A high-k gate dielectric layer on the surface of the interface layer, wherein the thickness of the oxide layer is greater than the thickness of the interface layer.

Optionally, the first work function layers of the several sub-regions of the first region are thinned to the same thickness; or, the first work function layers of the several sub-regions of the first region are thinned. The thinning thickness of the thinning process is not the same.

Optionally, the base further includes a third area and a fourth area, the area types of the third area and the fourth area are the same, and the area types of the third area and the fourth area are the same as those of the first area and the second area It is different; it also includes the steps of: performing a second threshold voltage adjustment doping treatment on the substrate of the third region; the gate dielectric layer is also located on the surface of the substrate of the third region and the fourth region; forming a first layer covering the gate dielectric layer Two work function layers, the second work function layer has a third thickness; thinning the second work function layer in the third region, so that the second work function layer in the third region has a fourth thickness; A third gate electrode layer is formed on the surface of the second work function layer with a fourth thickness; a fourth gate electrode layer is formed on the surface of the second work function layer in the fourth region.

Optionally, the first area and the second area are PMOS areas; the third area and the fourth area are NMOS areas; wherein, the first area includes several sub-areas, and the several sub-areas of the first area include The pull-up transistor area, the first input and output transistor area, the first standard threshold voltage area and the first low threshold voltage area; the second area is the first ultra-low threshold voltage area; the third area includes several sub-areas, Several sub-areas of the third area include a pull-down transistor area, a second input-output transistor area, a transfer gate transistor area, a second standard threshold voltage area, and a second low threshold voltage area; the fourth area is the second ultra-low threshold voltage region.

Optionally, performing the first threshold voltage adjusting doping treatment on the substrates of the several subregions of the first region, and performing the first threshold voltage adjusting doping treatment on the substrates of the several subregions of the first region The doping concentration is different; the second threshold voltage adjustment doping treatment is performed on the substrates of the several subregions of the third region, and the second threshold voltage adjustment doping treatment is performed on the substrates of the several subregions of the third region. The doping concentrations of the doping treatments vary.

Optionally, the base includes a substrate and discrete fins located on the surface of the substrate.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the method for forming semiconductor devices with different threshold voltages provided by the present invention, a first threshold voltage adjustment doping treatment is performed on the base of the first region; a gate dielectric layer is formed on the substrate surfaces of the first region and the second region ; forming a first work function layer covering the surface of the gate dielectric layer in the first region and the second region, the first work function layer having a first thickness; then, thinning the first work function layer in the first region , so that the first work function layer in the first region has a second thickness; then a first gate electrode layer is formed on the surface of the first work function layer with the second thickness, and a second gate electrode layer is formed on the surface of the first work function layer in the second region. gate electrode layer. Since the first region has undergone the first threshold voltage adjustment doping treatment, and the thickness of the first work function layer of the first region is smaller than the thickness of the first work function layer of the second region, the relationship between the metal and the semiconductor material in the first region The work function difference between them is larger than the difference between the metal and the semiconductor material in the second region, so the threshold voltage of the MOS transistor formed in the first region is much higher than the threshold voltage of the MOS transistor formed in the second region, so that The threshold voltage difference of different MOS transistors in the formed semiconductor device is relatively large, which meets the performance requirement of the device.

Further, the first region also includes several subregions, the first threshold voltage adjustment doping treatment is performed on the substrates of the several subregions, and the first threshold voltage adjustment doping treatment is performed on the substrates of the several subregions The doping concentrations of the MOS tubes are different, so that the MOS transistors formed in the first region also have different threshold voltages.

Further, the thicknesses of the first work function layers in the several sub-regions of the first region are different, so that the MOS transistors formed in the first region have different threshold voltages.

Furthermore, the substrate provided by the present invention also includes a third region and a fourth region with the same region type, and the region types of the third region and the fourth region are different from those of the first region and the second region, and the third region The substrate is subjected to the second threshold voltage adjustment doping treatment; the second work function layer covering the gate dielectric layer is formed; the second work function layer in the third region is thinned so that the thickness of the second work function layer in the third region is reducing from the third thickness to the fourth thickness; forming a third gate electrode layer on the surface of the second work function layer with the fourth thickness; forming a fourth gate electrode on the surface of the second work function layer in the fourth region Floor. Similarly, the threshold voltage difference of the devices formed in the third region and the fourth region of the present invention is relatively large.

Description of drawings

1 to 25 are schematic cross-sectional structural diagrams of a semiconductor device forming process provided by an embodiment of the present invention.

detailed description

It can be seen from the background art that the threshold voltage difference in the semiconductor device formed in the prior art is small, and it is difficult to meet the requirement of the device.

It has been found through research that in the semiconductor devices with different threshold voltages formed in the prior art, the difference between the maximum value and the minimum value of the threshold voltage is about 150mV, but with the development of technology, the The threshold voltage difference is usually greater than 200mV. Therefore, it is urgent to provide a new method for forming a semiconductor device that increases the difference between the maximum value and the minimum value of the threshold voltage to meet the requirements of the device.

In order to solve the above problems, the present invention provides a method for forming a semiconductor device with different threshold voltages, comprising: providing a substrate, the substrate at least including a first region and a second region, the regions of the first region and the second region the same type; perform a first threshold voltage adjustment doping treatment on the substrate of the first region; form a gate dielectric layer on the substrate surface of the first region and the second region; form a gate dielectric layer covering the first region and the second region The first work function layer on the surface of the gate dielectric layer, the first work function layer has a first thickness; the first work function layer in the first region is thinned, so that the first work function layer in the first region It has a second thickness; a first gate electrode layer is formed on the surface of the first work function layer with the second thickness; and a second gate electrode layer is formed on the surface of the first work function layer in the second region. In the present invention, the first threshold voltage adjustment doping treatment is performed on the base of the first region, and the first work function layer in the first region is thinned, so that the thickness of the first work function layer in the first region is reduced by the first One thickness is reduced to the second thickness, therefore, the threshold voltage value of the device formed in the first region is much higher than the threshold voltage value of the device formed in the second region, thereby increasing the threshold voltage difference of the MOS transistor in the semiconductor device, satisfying device performance requirements.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

1 to 25 illustrate a method for forming semiconductor devices with different threshold voltages according to an embodiment of the present invention.

Referring to FIG. 1 , a substrate is provided, and the substrate includes at least a first region (not labeled) and a second region II.

Subsequent devices formed in the first region and the second region II respectively have different threshold voltages. The area types of the first area and the second area II are the same. The first area is a PMOS area, and the second area II is a PMOS area; or, the first area is an NMOS area, and the second area II is an NMOS area.

The first region further includes several sub-regions, and the devices subsequently formed in each of the several sub-regions also have different threshold voltages. The second region II is an ultra-low threshold voltage (ULVT, Ultra-low VT) region. In another embodiment, the first area can only include one sub-area.

In one embodiment, when the first region is a PMOS region, the several subregions include a pull-up (PU, Pull Up) transistor region, an input-output transistor (IO, Input Output) region, a standard threshold voltage (SVT, Standard VT) region and low threshold voltage (LVT, Low VT) region. In another embodiment, when the first region is an NMOS region, several subregions in the first region include a pull-down (PD, Pull Down) transistor region, an input and output transistor region, a transfer gate (PG, Pass Gate ) transistor region, standard threshold voltage region, and low threshold voltage region.

In one embodiment, the formed semiconductor device only includes NMOS transistors. In another embodiment, the formed semiconductor device only includes PMOS transistors.

In this embodiment, the formed semiconductor device includes NMOS transistors and PMOS transistors, wherein the threshold voltages of different NMOS transistors are different, and the threshold voltages of different PMOS transistors are different. The substrate also includes a third area (not marked) and a fourth area IV, the third area and the fourth area IV are of the same area type, and the third area, the fourth area IV are the same as the first area and the second area II has a different type of region. In this embodiment, the first region and the second region II are PMOS regions, and the third region and fourth region IV are NMOS regions. Wherein, the first region includes several subregions, and the several subregions of the first region include a first low threshold voltage region 11, a first standard threshold voltage region 12, a pull-up transistor region 13 and a first input-output transistor region 14; The second region II is the first ultra-low threshold voltage region; the third region includes several subregions, and the several subregions of the third region include the second low threshold voltage region 21, the second standard threshold voltage region 22, the pull-down The transistor region 23 , the transfer gate transistor region 24 and the second input-output transistor region 25 ; the fourth region is the second ultra-low threshold voltage region. In other embodiments, it is also possible that the first area and the second area are NMOS areas, and the third area and the fourth area are PMOS areas.

In this embodiment, the semiconductor device formed is a FinFET as an example, and the base includes a substrate 101 and discrete fins 102 located on the surface of the substrate 101 .

In another embodiment, the semiconductor device is a planar transistor, the substrate is a planar substrate, and the planar substrate is a silicon substrate, a germanium substrate, a silicon germanium substrate or a silicon carbide substrate, or a silicon-on-insulator substrate. Or a germanium-on-insulator substrate, a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), and the gate structure is formed on the surface of the planar substrate.

The material of the substrate 101 is silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate 101 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; The material of the fin portion 102 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. In this embodiment, the substrate 101 is a silicon substrate, and the material of the fins 102 is silicon.

In this embodiment, the process steps of forming the substrate 101 and the fin portion 102 include: providing an initial substrate; forming a patterned hard mask layer 103 on the surface of the initial substrate; The initial substrate is etched as a mask, the etched initial substrate is used as the substrate 101 , and the protrusions on the surface of the substrate 101 are used as the fins 102 .

In one embodiment, the process steps of forming the hard mask layer 103 include: first forming an initial hard mask; forming a patterned photoresist layer on the surface of the initial hard mask; The resist layer is used as a mask to etch the initial hard mask to form a hard mask layer 103 on the surface of the initial substrate; and remove the patterned photoresist layer. In other embodiments, the formation process of the hard mask layer can also include: self-aligned double patterning (SADP, Self-aligned Double Patterned) process, self-aligned triple patterning (Self-aligned Triple Patterned) process , or self-aligned quadruple patterning (Self-aligned Double Double Patterned) process. The double patterning process includes LELE (Litho-Etch-Litho-Etch) process or LLE (Litho-Litho-Etch) process.

In this embodiment, after the fin portion 102 is formed, the hard mask layer 103 on the top surface of the fin portion 102 remains. The material of the hard mask layer 103 is silicon nitride, and the top surface of the hard mask layer 103 can be used as a stop position of the planarization process to protect the top of the fin portion 102 when the subsequent planarization process is performed. In this embodiment, the top size of the fin 102 is smaller than the bottom size. In other embodiments, the sidewall of the fin can also be perpendicular to the substrate surface, that is, the top dimension of the fin is equal to the bottom dimension.

Referring to FIG. 2 , an isolation film 104 covering the surface of the substrate 101 and the surface of the fin portion 102 is formed, and the top of the isolation film 104 is higher than the top of the hard mask layer 103 .

Before forming the isolation film 104 , a step is further included: performing oxidation treatment on the substrate 101 and the fin portion 102 , and forming a linear oxide layer on the surface of the substrate 101 and the surface of the fin portion 102 .

The isolation film 104 provides a process basis for subsequent formation of an isolation layer; the material of the isolation film 104 is an insulating material, such as silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation film 104 is silicon oxide.

In order to improve the gap-filling capability of the process for forming the isolation film 104 , the isolation film 104 is formed by using flowable chemical vapor deposition (FCVD, Flowable CVD) or high aspect ratio chemical vapor deposition process (HARPCVD).

After the isolation film 104 is formed, a step is further included: annealing the isolation film 104 to increase the density of the isolation film 104 .

Referring to FIG. 3 , removing part of the thickness of the isolation film 104 (refer to FIG. 2 ) to form an isolation layer 114, the isolation layer 114 is located on the surface of the substrate 101 and covers part of the sidewall surface of the fin 102, and the top of the isolation layer 114 is lower than the fin. Section 102 top.

The material of the isolation layer 114 is silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation layer 114 is silicon oxide.

In one embodiment, a dry etching process is used to etch and remove part of the thickness of the isolation film 104 . In another embodiment, a wet etching process is used to etch and remove part of the thickness of the isolation film 104 .

A step is also included: removing the hard mask layer 103 by etching (refer to FIG. 2 ). It can also include the step of: forming a shielding layer on the top and sidewall surfaces of the fin portion 102 and the surface of the isolation layer 114, the material of the shielding layer is silicon oxide or silicon oxynitride, and its function is: in the subsequent doping process During the process, the shielding layer can reduce the lattice damage caused by the doping process to the fin portion 102 .

Referring to FIG. 4, the substrates of the first region and the second region II are subjected to a first well region doping treatment, and a first well region (not shown) is formed in the substrates of the first region and the second region II .

In this embodiment, the first well region doping treatment is performed on the substrate 101 in the first region and the second region II. The first region and the second region II are PMOS regions, and the dopant ions in the first well region doping treatment are N-type ions, and the N-type ions are P, As or Sb.

The process steps of performing the first well region doping treatment include: forming a first pattern layer 105 on the surface of the isolation layer 114 and the surface of the fin portion 102 in the third region and the fourth region IV, and the first pattern layer 105 The top is higher than the top of the fin portion 102; using the first pattern layer 105 as a mask, perform a first well doping treatment on the substrate 101 in the first region and the second region II; then, remove the first A graphics layer 105 .

The material of the first pattern layer 105 is hard mask material or photoresist material.

Referring to FIG. 5 , the substrates of the third region and the fourth region IV are subjected to a second well region doping treatment, and a second well region (not shown) is formed in the substrates of the third region and the fourth region IV. .

In this embodiment, the second well region doping treatment is performed on the substrate 101 in the third region and the fourth region IV. The third region and the fourth region IV are NMOS regions, and the doping ions in the second well region are P-type ions, and the P-type ions are B, Ga or In.

The process step of performing the second well region doping treatment includes: forming a second pattern layer 106 on the surface of the isolation layer 114 and the surface of the fin portion 102 in the first region and the second region II, and the second pattern layer 106 The top is higher than the top of the fin portion 102; using the second pattern layer 106 as a mask, perform a second well doping treatment on the substrate 101 in the third region and the fourth region IV; then, remove the first Two graphic layers 106 .

The material of the second pattern layer 106 is hard mask material or photoresist material.

The subsequent step further includes the step of performing a first threshold voltage adjustment treatment on the substrate of the first region, since the first region also includes several subregions, performing the first threshold voltage adjustment doping treatment on the substrates of the several subregions, And the doping concentration of the first threshold voltage adjustment doping treatment performed on the substrates of the several sub-regions is different. The details will be described below with reference to the accompanying drawings. The first threshold voltage adjustment doping treatment is actually performed on the fin portion 102 .

Referring to FIG. 6 , a first threshold voltage adjustment doping treatment is performed on the substrate of the first low threshold voltage region 11 in the first region.

When the first region is a PMOS region, the dopant ions of the first threshold voltage adjustment doping treatment are N-type ions, and the doping ions of the first threshold voltage adjustment doping treatment are P or As; When the first region is an NMOS region, the dopant ions in the first threshold voltage adjusting doping treatment are P-type ions, and the doping ions in the first threshold voltage adjusting doping treatment are B or Ga.

In this embodiment, the first region is a PMOS region, and the process steps of performing the first threshold voltage adjustment doping treatment on the first low threshold voltage region 11 include: in the second region II, the third region, The third pattern layer 107 is formed on the surface of the isolation layer 114 and the surface of the fin portion 102 in the fourth region IV, and the region except the first low threshold voltage region 11 in the first region; the third pattern layer 107 is used as a mask , performing N-type ion implantation on the first low-threshold voltage region 11 ; then, removing the third pattern layer 107 .

In this embodiment, according to the required threshold voltage range of the device formed in the first low threshold voltage region 11 , the doping concentration for performing the first threshold voltage adjustment doping treatment is determined.

Referring to FIG. 7 , the substrate of the first standard threshold voltage region 12 in the first region is subjected to a first threshold voltage adjustment doping treatment.

In this embodiment, the first region is a PMOS region, and dopant ions in the first threshold voltage adjustment doping treatment are N-type ions.

The process step of performing the first threshold voltage adjustment doping treatment on the substrate of the first standard threshold voltage region 12 includes: removing the second region II, the third region, the fourth region IV, and the first region A fourth pattern layer 108 is formed on the surface of the isolation layer 114 and the surface of the fin portion 102 outside the standard threshold voltage region 12; using the fourth pattern layer 108 as a mask, the first standard threshold voltage region 12 is N-type ion implantation; then, removing the fourth pattern layer 108 .

According to the required threshold voltage range of the device formed in the first standard threshold voltage region 12 , the doping concentration for performing the first threshold voltage adjustment doping treatment is determined. In this embodiment, the doping concentrations of the first threshold voltage adjusting doping treatment performed on the first standard threshold voltage region 12 and the first low threshold voltage region 11 are different.

Referring to FIG. 8 , a first threshold voltage adjustment doping treatment is performed on the base of the pull-up transistor region 13 in the first region.

In this embodiment, the first region is a PMOS region, and dopant ions in the first threshold voltage adjustment doping treatment are N-type ions.

The process step of performing the first threshold voltage adjustment doping treatment on the base of the pull-up transistor region 13 includes: removing the pull-up transistor in the second region II, the third region, the fourth region IV, and the first region A fifth pattern layer 109 is formed on the surface of the isolation layer 114 and the surface of the fin portion 102 outside the region 13; using the fifth pattern layer 109 as a mask, perform N-type ion implantation on the pull-up transistor region 13; then , removing the fifth graphic layer 109 .

According to the required threshold voltage range of the device formed in the pull-up transistor region 13 , the doping concentration for performing the first threshold voltage adjustment doping treatment is determined. In this embodiment, the doping concentrations of the first threshold voltage adjusting doping treatment performed on the pull-up transistor region 13 , the first standard threshold voltage region 12 and the first low threshold voltage region 11 are different.

Referring to FIG. 9 , a first threshold voltage adjustment doping treatment is performed on the substrate of the first input-output transistor region 14 in the first region.

In this embodiment, the first region is a PMOS region, and dopant ions in the first threshold voltage adjustment doping treatment are N-type ions.

The process step of performing the first threshold voltage adjustment doping treatment on the substrate of the first input-output transistor region 14 includes: the second region II, the third region, the fourth region IV, and the first region except the first region A sixth pattern layer 110 is formed on the surface of the isolation layer 114 and the surface of the fin portion 102 other than the input-output transistor region 14; using the sixth pattern layer 110 as a mask, the first input-output transistor region 14 is N-type ion implantation; then, removing the sixth pattern layer 110 .

According to the required threshold voltage range of the device formed in the first input-output transistor region 14 , the doping concentration for performing the first threshold voltage adjustment doping treatment is determined. In this embodiment, the doping of the first threshold voltage adjustment doping process performed on the first input and output transistor region 14, the pull-up transistor region 13, the first standard threshold voltage region 12 and the first low threshold voltage region 11 is Concentrations are not the same.

By adjusting the concentration of doping ions in the base of each sub-region in the first region, the threshold voltage values of correspondingly formed devices are different. Generally, the lower the concentration of dopant ions in the substrate of the sub-region, the smaller the threshold voltage value of the corresponding formed device.

Subsequent steps also include performing a second threshold voltage adjustment process on the base of the third region. Since the third region includes several sub-regions, the second threshold voltage adjustment process is subsequently performed on the bases of the several sub-regions of the third region. , and the doping concentrations of the second threshold voltage adjusting doping treatment performed on the substrates of the several sub-regions of the third region are different. The details will be described below with reference to the accompanying drawings. The second threshold voltage adjustment doping treatment is actually performed on the fin portion 102 .

Referring to FIG. 10 , a second threshold voltage adjustment doping treatment is performed on the substrate of the second low threshold voltage region 21 in the third region.

When the third region is a PMOS region, the dopant ions of the second threshold voltage adjustment doping treatment are N-type ions, and the dopant ions of the second threshold voltage adjustment doping treatment are P or As; When the third region is an NMOS region, the dopant ions in the second threshold voltage adjustment doping treatment are P-type ions, and the dopant ions in the second threshold voltage adjustment doping treatment are B or Ga.

In this embodiment, the third region is an NMOS region, and the process step of performing the second threshold voltage adjustment doping treatment on the substrate of the second low threshold voltage region 21 includes: II, fourth region IV, the surface of the isolation layer 114 and the surface of the fin portion 102 in the third region except the second low threshold voltage region 21 forms a seventh pattern layer 111; using the seventh pattern layer 111 as a mask film, performing P-type ion implantation on the second low-threshold voltage region 21; then, removing the seventh pattern layer 111.

According to the required threshold voltage range of the device formed in the second low threshold voltage region 21 , the doping concentration for performing the second threshold voltage adjustment doping treatment is determined.

Referring to FIG. 11 , the substrate of the second standard threshold voltage region 22 in the third region is subjected to a second threshold voltage adjusting doping treatment.

In this embodiment, the third region is an NMOS region, and dopant ions in the second threshold voltage adjustment doping treatment are P-type ions.

The process step of performing the second threshold voltage adjustment doping treatment on the substrate of the second standard threshold voltage region 22 includes: removing the second Form the eighth pattern layer 112 on the surface of the isolation layer 114 and the surface of the fin portion 102 outside the standard threshold voltage region 22; use the eighth pattern layer 112 as a mask to perform P type ion implantation; then, removing the eighth pattern layer 112 .

According to the required threshold voltage range of the device formed in the second standard threshold voltage region 22 , the doping concentration for performing the second threshold voltage adjustment doping treatment is determined. In this embodiment, the doping concentration of the second threshold voltage adjusting doping treatment performed on the second standard threshold voltage region 22 and the second low threshold voltage region 21 is different.

Referring to FIG. 12 , a second threshold voltage adjustment doping treatment is performed on the base of the pull-down transistor region 23 in the third region.

In this embodiment, the third region is an NMOS region, and dopant ions in the second threshold voltage adjustment doping treatment are P-type ions.

The process step of performing the second threshold voltage adjustment doping treatment on the base of the pull-down transistor region 23 includes: removing the pull-down transistor region 23 from the first region, the second region II, the fourth region IV, and the third region. Form the ninth pattern layer 113 on the surface of the isolation layer 114 and the surface of the fin portion 102 in the area outside the region; use the ninth pattern layer 113 as a mask to perform P-type ion implantation on the pull-down transistor region 23; then, remove all Describe the ninth graphics layer 113.

According to the required threshold voltage range of the device formed in the pull-down transistor region 23 , the doping concentration for performing the second threshold voltage adjustment doping treatment is determined. In this embodiment, the doping concentrations of the second threshold voltage adjusting doping treatment performed on the pull-down transistor region 23 , the second standard threshold voltage region 22 and the second low threshold voltage region 21 are different.

Referring to FIG. 13 , a second threshold voltage adjustment doping treatment is performed on the base of the transfer gate transistor region 24 in the third region.

In this embodiment, the third region is an NMOS region, and dopant ions in the second threshold voltage adjustment doping treatment are P-type ions.

The process step of performing the second threshold voltage adjustment doping treatment on the substrate of the transfer gate transistor region 24 includes: removing transfer gate transistors in the first region, the second region II, the fourth region IV, and the third region. A tenth pattern layer 115 is formed on the surface of the isolation layer 114 and the surface of the fin portion 102 outside the region 24; using the tenth pattern layer 115 as a mask, perform P-type ion implantation on the transfer gate transistor region 24; then , removing the tenth graphics layer 115 .

According to the required threshold voltage range of the device formed by the transfer gate transistor region 24 , the doping concentration for performing the second threshold voltage adjustment doping treatment is determined. In this embodiment, the doping concentration of the second threshold voltage adjustment doping treatment performed on the transfer gate transistor region 24, the pull-down transistor region 23, the second standard threshold voltage region 22 and the second low threshold voltage region 21 is different. .

Referring to FIG. 14 , a second threshold voltage adjustment doping treatment is performed on the base of the second input-output transistor region 25 in the third region.

In this embodiment, the third region is an NMOS region, and dopant ions in the second threshold voltage adjustment doping treatment are P-type ions.

The process step of performing the second threshold voltage adjustment doping treatment on the substrate of the second input-output transistor region 25 includes: removing the second threshold voltage in the first region, the second region II, the fourth region IV, and the third region. A first mask layer 116 is formed on the surface of the isolation layer 114 and the surface of the fin portion 102 outside the two-input-output transistor region 25; using the first mask layer 116 as a mask, the transfer gate transistor region 24 is P-type ion implantation; next, removing the first mask layer 116 .

According to the required threshold voltage range of the device formed by the second input-output transistor region 25 , the doping concentration for performing the second threshold voltage adjustment doping treatment is determined. In this embodiment, the second threshold voltage adjustment doping performed on the second input and output transistor region 25, the transfer gate transistor region 24, the pull-down transistor region 23, the second standard threshold voltage region 22 and the second low threshold voltage region 21 is The doping concentration of doping treatment is different.

By adjusting the concentration of dopant ions in the base of each sub-region in the third region, the threshold voltage values of correspondingly formed devices are different. Generally, the lower the concentration of dopant ions in the substrate of the sub-region, the smaller the threshold voltage value of the corresponding formed device.

The subsequent steps further include: forming a first gate structure on the surface of the substrate in the first region; forming a second gate structure on the surface of the substrate in the second region; forming a third gate structure on the surface of the substrate in the third region; A fourth gate structure is formed on the surface of the substrate in the fourth region. Specifically, the subsequent steps further include: forming a gate dielectric layer on the substrate surface of the first region and the second region; forming a first work function layer covering the surface of the gate dielectric layer in the first region and the second region, the The first work function layer has a first thickness; the first work function layer in the first region is thinned so that the first work function layer in the first region has a second thickness; the gate dielectric layer is also located in the first region. The substrate surface of the third region and the fourth region; forming a second work function layer covering the surface of the gate dielectric layer in the third region and the fourth region, the second work function layer having a third thickness; for the third region The second work function layer is thinned so that the second work function layer in the third region has a fourth thickness; a first gate electrode layer is formed on the surface of the first work function layer with the second thickness; The second gate electrode layer is formed on the surface of the first work function layer in the second region; the third gate electrode layer is formed on the surface of the second work function layer with a fourth thickness; the second work function layer in the fourth region A fourth gate electrode layer is formed on the surface.

Wherein, the first gate structure, the second gate structure, the third gate structure or the fourth gate structure can be fabricated by a gate first process (gate first), and can also be produced by a gate last process. In this embodiment, among the gate dielectric layers on the base surface of the several sub-regions of the first region, the gate dielectric layer located on the base surface of the first input-output transistor region has the thickest thickness. Among the gate dielectric layers on the base surface of the several sub-regions of the third region, the gate dielectric layer located on the base surface of the second input-output transistor region has the thickest thickness.

The first gate structure will be described below with reference to the accompanying drawings. The formation process of the second gate structure, the third gate structure and the fourth gate structure will be described in detail, taking the gate-last process as an example.

Referring to FIG. 15 , an oxide film is formed on the substrate surface of the first region, the second region II, the third region and the fourth region IV; a dummy gate film is formed on the surface of the oxide film; the dummy gate film is patterned and the oxide film is film, forming an oxide layer 201 on the substrate surface of the first region, the second region II, the third region and the fourth region IV, and forming a dummy gate layer 202 on the surface of the oxide layer 201 .

The dummy gate layer 202 occupies the spatial positions of the subsequently formed first gate structure, second gate structure, third gate structure and fourth gate structure.

The material of the oxide layer 201 is silicon oxide or silicon oxynitride. In this embodiment, the thickness of the oxide layer 201 is relatively thick, and the oxide layer 201 located in the first input-output transistor region 14 and the second input-output transistor region 25 is subsequently retained, so that the first region in each sub-region of the first region The first I/O transistor region 14 has the thickest gate dielectric layer, and the second I/O transistor region 25 has the thickest gate dielectric layer in each sub-region of the third region.

The material of the dummy gate layer 202 is polysilicon, amorphous silicon or amorphous carbon. In this embodiment, the material of the dummy gate layer 202 is polysilicon.

It also includes the steps of: forming offset sidewalls on the sidewall surface of the dummy gate layer 202; performing light doping treatment on the fins 102 in the first region on both sides of the dummy gate layer 202 to form the first LDD region. In this example, it includes lightly doping the fins 102 of each sub-region in the first region; lightly doping the fins 102 in the second region II on both sides of the dummy gate layer 202 to form the second LDD region lightly doping the fins 102 of the third region on both sides of the dummy gate layer 202 to form the third LDD region, in this embodiment, lightly doping the fins 102 of each sub-region in the third region Doping treatment: performing light doping treatment on the fins 102 in the fourth region IV on both sides of the dummy gate layer 202 to form a fourth LDD region.

It also includes the steps of: forming main sidewalls on the sidewall surfaces of the offset sidewalls; performing heavy doping treatment on the fins 102 in the first region on both sides of the dummy gate layer 202 to form a first S/D region. In the embodiment, it includes performing heavy doping treatment on the fins 102 of each sub-region in the first region; performing heavy doping treatment on the fins 102 in the second region II on both sides of the dummy gate layer 202 to form the second S /D region: perform heavy doping treatment on the fins 102 of the third region on both sides of the dummy gate layer 202 to form the third S/D region. In this embodiment, fins for each subregion in the third region are included. The heavy doping treatment is performed on the portion 102; the heavy doping treatment is performed on the fourth region IV fin portion 102 on both sides of the dummy gate layer 202 to form the fourth S/D region.

Referring to FIG. 16 , the dummy gate layer 202 (refer to FIG. 15 ) is removed.

Before removing the dummy gate layer 202 , a step is further included: forming an interlayer dielectric layer (not shown) on the surface of the substrate, and the interlayer dielectric layer covers the sidewall surface of the dummy gate layer 202 .

The dummy gate layer 202 is etched and removed by using a dry etching process, a wet etching process or a SiCoNi etching system.

Referring to FIG. 17 , the oxide layer 201 located outside the first I/O transistor region 14 and the second I/O transistor region 25 is removed by etching.

In this embodiment, a third mask layer 203 is formed on the surface of the oxide layer 201 of the first input-output transistor region 14 and the second input-output transistor region 25, exposing the second region II, the fourth region IV, the first The oxide layer 201 of the low threshold voltage region 11, the first standard threshold voltage region 12, the pull-up transistor region 13, the second low threshold voltage region 21, the second standard threshold voltage region 22, the pull-down transistor region 23 and the transfer gate transistor region 24 surface: using the third mask layer 203 as a mask, etching and removing the oxide layer 201 exposed by the third mask layer 203 ; then, removing the third mask layer 203 .

18, in the second region II, the fourth region IV, the first low threshold voltage region 11, the first standard threshold voltage region 12, the pull-up transistor region 13, the second low threshold voltage region 21, the second standard The base surfaces of the threshold voltage region 22 , the pull-down transistor region 23 and the transfer gate transistor region 24 form an interface layer 204 .

The material of the interface layer 204 is silicon oxide or silicon oxynitride. In this embodiment, the interface layer 204 is formed by an oxidation process, the oxidation process is dry oxygen oxidation, wet oxygen oxidation or water vapor oxidation, and the formed interface layer 204 is only located on the exposed top surface and sidewall surface of the fin portion 102 , the thickness of the interface layer 204 is smaller than the thickness of the oxide layer 202 . The interface layer 204 and the oxide layer 202 are part of the gate dielectric layer; since the thickness of the oxide layer 202 is greater than the thickness of the interface layer 204, the subsequent gate dielectric layer of the first input-output transistor region 14 and the second input-output transistor region 25 The thickness of the gate dielectric layer is thicker than that of other regions.

In other embodiments, the interface layer is formed by a deposition process, the deposition process is chemical vapor deposition, physical vapor deposition or atomic layer deposition, and the formed interface layer is also located on the surface of the oxide layer. Similarly, the thickness of the gate dielectric layer in the subsequent first input-output transistor region and the second input-output transistor region is thicker than that in other regions.

Referring to FIG. 19 , a high-k gate dielectric layer 205 is formed on the surface of the interface layer 204 and the surface of the oxide layer 202 .

The material of the high-k gate dielectric layer 205 is a high-k gate dielectric material, wherein the high-k gate dielectric material refers to a gate dielectric material with a relative permittivity greater than that of silicon oxide, and the high-k gate dielectric The material of layer 205 is HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO ₂ or Al ₂ O ₃ .

The high-k gate dielectric layer 205 is formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In this embodiment, the material of the high-k gate dielectric layer 205 is HfO ₂ , the thickness of the high-k gate dielectric layer 205 is 5 angstroms to 15 angstroms, and the high-k gate dielectric layer 205 is formed by atomic layer deposition process .

For the first input-output transistor region 14 and the second input-output transistor region 25 , the gate dielectric layer includes: an oxide layer 202 and a high-k gate dielectric layer 205 located on the surface of the oxide layer 202 . For regions other than the first I/O transistor region 14 and the second I/O transistor region 25 , the gate dielectric layer includes: an interface layer 204 and a high-k gate dielectric layer 205 located on the surface of the interface layer 204 . From the foregoing analysis, it can be seen that among the subregions of the first region, the thickness of the gate dielectric layer of the first input-output transistor region 14 is the thickest; among the subregions of the third region, the thickness of the gate dielectric layer of the second input-output transistor region 25 is thickest.

Continuing to refer to FIG. 19 , a first work function layer 208 covering the surface of the gate dielectric layer in the first region and the second region II is formed.

Before forming the first work function layer 208 , further steps are included: forming a capping layer 206 on the surface of the high-k gate dielectric layer 205 ; forming an etching stop layer (not shown) on the surface of the capping layer 206 .

The capping layer 206 plays a role in protecting the high-k gate dielectric layer 205, preventing the subsequent etching process from causing unnecessary etching loss to the high-k gate dielectric layer 205, and the capping layer 206 is also conducive to blocking metal ions from diffusion in the high-k gate dielectric layer 205 .

The material of the capping layer 206 is TiN; the capping layer 206 is formed by chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process.

The material of the etching stop layer is different from that of the subsequently formed first work function layer and the second work function layer, so that the etching rate of the etching stop layer in the subsequent etching process of etching the first work function layer is small, The subsequent etching process for etching the second work function layer has a small etching rate for the etching stop layer, so as to avoid etching damage to the high-k gate dielectric layer 205 . In this embodiment, the material of the etching stop layer is TaN, and the etching stop layer is formed by an atomic layer deposition process.

In this embodiment, the first work function layer 208 is located in the first area, the second area II, the third area, and the fourth area IV, and the first work function layer 208 located in the third area and the fourth area IV will be etched and removed later. Function layer 208 . The first work function layer 208 is located on the surface of the etch stop layer.

The first region and the second region II are PMOS regions, the material of the first work function layer 208 is a P-type work function material, and the material of the first work function layer 208 is Ta, TiN, TaSiN or TiSiN. one or more of. The first work function layer 208 is formed by chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process.

In this embodiment, the material of the first work function layer 208 is TiN, and the first work function layer 208 has a first thickness, and the first thickness is 30 angstroms to 60 angstroms.

Referring to FIG. 20 , the first work function layer 208 in the first region is thinned so that the first work function layer 208 in the first region has a second thickness.

The thinner the thickness of the first work function layer 208, the greater the work function difference between the metal and the semiconductor material in the area where the first work function layer 208 is located, and the greater the threshold voltage value of the device formed in the corresponding area. .

In this embodiment, since the second region II is an ultra-low threshold voltage region, the threshold voltage value of the device formed in the second region II is very small, and in order to meet the requirements of semiconductor devices, the threshold voltage of the device formed in the second region II The difference between the threshold voltage and the threshold voltage of the device formed in the first region is large, and it is difficult to obtain a threshold voltage with a large difference in the above-mentioned first threshold voltage adjustment doping treatment. For this reason, this embodiment further thins the first work function layer 208 in the first region, so that the threshold voltage value of the device formed in the first region is further increased, so that the threshold voltage of the device formed in the second region II is the same as The difference between the threshold voltages of the devices formed in the first region is relatively large.

In this embodiment, the second thickness is 15 angstroms to 30 angstroms. A dry etching process, a wet etching process or a SiCoNi etching system is used to etch and remove the first work function layer 208 with a partial thickness of the first region. Specifically, a fourth mask layer 209 is formed on the surface of the first work function layer 208 in the second region II, the third region and the fourth region IV; using the fourth mask layer 209 as a mask, etching Partial thickness of the first work function layer 208 in the first region is removed, so that the thickness of the first work function layer 208 in the first region is reduced from the first thickness to the second thickness. In this embodiment, the fourth mask layer 209 also covers the surface of the first work function layer 208 of the first input-output transistor region 14 .

In this embodiment, the thinning thickness of the first work function layer 208 in each subregion of the first region is the same, that is, the second thickness of the first work function layer 208 in each subregion of the first region same. In other embodiments, the thinning thickness of the first work function layer of each sub-region in the first region can also be different, that is, the first work function layer of each sub-region in the first region Two thicknesses vary.

Referring to FIG. 21 , the first work function layer 208 located in the third region and the fourth region IV is removed.

Specifically, a fifth mask layer 210 is formed on the surface of the first work function layer 208 in the first region and the second region II; using the fifth mask layer 210 as a mask, etching removes the and the first work function layer 208 in the fourth region IV; then, the fifth mask layer 210 is removed.

In other embodiments, the first work function layer located in the third region and the fourth region can also be removed first, and then the first work function layer in the first region is thinned.

Referring to FIG. 22 , a second work function layer 211 covering the gate dielectric layer is formed.

In this embodiment, the second work function layer 211 is located in the first region, the second region II, the third region and the fourth region IV, and the second work function layer 211 is located between the first region and the second region II The surface of the first work function layer 208 is also located on the surface of the etching stop layer in the third region and the fourth region IV. Subsequent etching removes the second work function layer 211 located in the first region and the second region II.

The third region and the fourth region IV are NMOS regions, the material of the second work function layer 211 is an N-type work function material, and the material of the second work function layer 211 is TiAl, TiAlC, TaAlN, TiAlN, One or more of MoN, TaCN or AlN. The second work function layer 211 is formed by chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process.

In this embodiment, the material of the second work function layer 211 is TiAlC, and the second work function layer 211 has a third thickness, and the third thickness is 30 angstroms to 60 angstroms.

Referring to FIG. 23 , the second work function layer 211 in the third region is thinned so that the second work function layer 211 in the third region has a fourth thickness.

The thinner the second work function layer 211 is, the greater the work function difference between the metal and the semiconductor material in the area where the second work function layer 211 is located, and the greater the threshold voltage value of the device formed in the corresponding area. .

In this embodiment, since the fourth region IV is an ultra-low threshold voltage region, the threshold voltage value of the device formed in the fourth region IV is very small, and in order to meet the requirements of semiconductor devices, the threshold voltage of the device formed in the fourth region IV The difference between the threshold voltage and the threshold voltage of the device formed in the third region is large, and it is difficult to obtain a threshold voltage with a large difference in the second threshold voltage adjustment doping treatment performed above. For this reason, this embodiment further thins the second work function layer 211 in the third region, so that the threshold voltage value of the device formed in the third region is further increased, so that the threshold voltage of the device formed in the fourth region IV is the same as The difference between the threshold voltages of the devices formed in the third region is larger.

In this embodiment, the fourth thickness is 15 angstroms to 30 angstroms. A dry etching process, a wet etching process or a SiCoNi etching system is used to etch and remove the second work function layer 211 partially thick in the third region. Specifically, a fifth mask layer 212 is formed on the surface of the second work function layer 211 in the first region, the second region II, and the fourth region IV; using the fifth mask layer 212 as a mask, etching Partial thickness of the second work function layer 211 in the third region is removed, so that the thickness of the second work function layer 211 in the third region is reduced from the third thickness to the fourth thickness. In this embodiment, the fifth mask layer 212 also covers the transfer gate transistor region 23 and the second I/O transistor region 25 .

In this embodiment, the thinned thickness of the second work function layer 211 in each sub-region of the third region is the same, that is, the fourth thickness of the second work function layer 211 in each sub-region of the third region same. In other embodiments, the thinning thickness of the second work function layer of each subregion in the third region can also be different, that is, the second work function layer of each subregion in the third region The fourth thickness of the functional layer varies.

Referring to FIG. 24, the second work function layer 211 located in the first region and the second region II is removed.

Specifically, a sixth mask layer 213 is formed on the surface of the second work function layer 211 in the third region and the fourth region IV; using the sixth mask layer 213 as a mask, etch and remove and the second work function layer 211 in the second region II; then, removing the sixth mask layer 213 .

In other embodiments, the second work function layer located in the first region and the second region can also be removed first, and then the second work function layer in the third region is thinned.

In other embodiments, when the first area and the second area are PMOS areas, and when the third area and the fourth area are NMOS areas, the second work function layer located in the first area and the second area can also be reserved, and the second work function layer located in the first area can also be reserved. The second work function layer in the region and the second region has little influence on the threshold voltage of the MOS transistor formed in the first region and the second region.

Referring to FIG. 25 , a first gate electrode layer 302 is formed on the surface of the first work function layer 208 having a second thickness; a second gate electrode layer 301 is formed on the surface of the first work function layer 208 in the second region II; A third gate electrode layer 304 is formed on the surface of the second work function layer 211 having a fourth thickness; a fourth gate electrode layer 303 is formed on the surface of the second work function layer 211 in the fourth region IV.

The material of the first gate electrode layer 302 includes one or more of Al, Cu, Ag, Au, Pt, Ni, Ti or W; the material of the second gate electrode layer 301 includes Al, Cu, Ag One or more of Au, Pt, Ni, Ti or W; the material of the third gate electrode layer 304 includes one or more of Al, Cu, Ag, Au, Pt, Ni, Ti or W species; the material of the fourth gate electrode layer 303 includes one or more of Al, Cu, Ag, Au, Pt, Ni, Ti or W.

In this embodiment, the materials of the first gate electrode layer 302 , the second gate electrode layer 301 , the third gate electrode layer 304 and the fourth gate electrode layer 303 are the same. The first gate electrode layer 302 , the second gate electrode layer 301 , the third gate electrode layer 304 and the fourth gate electrode layer 303 are formed in the same process step.

The process steps of forming the first gate electrode layer 302, the second gate electrode layer 301, the third gate electrode layer 304 and the fourth gate electrode layer 303 include: forming the first work function layer 208 surface and the second work function layer A gate electrode film is formed on the surface of layer 211, and the top of the gate electrode film is higher than the top surface of the interlayer dielectric layer; the gate film higher than the top of the interlayer dielectric layer is removed by grinding, and the first gate electrode layer 302, the second gate electrode layer 302, and the second gate electrode layer are formed accordingly. The gate electrode layer 301 , the third gate electrode layer 304 and the fourth gate electrode layer 303 .

Since the base of the second region II is not subjected to the first threshold voltage adjustment doping treatment, and the thickness of the first work function layer 208 in the second region II is greater than the thickness of the first work function layer 208 in the first region, so that the second The threshold voltage of the device formed in the region II is much lower than the threshold voltage of the device formed in the first region, so the device formed in the second region II and the device formed in the first region have a larger threshold voltage difference, thereby satisfying Semiconductor device performance requirements. Similarly, because the substrate of the fourth region IV is not only not subjected to the second threshold voltage adjustment doping treatment, but also the thickness of the second work function layer 211 of the fourth region IV is greater than the thickness of the second work function layer 211 of the third region, The threshold voltage of the device formed in the fourth region IV is much lower than the threshold voltage of the device formed in the third region, so the device formed in the fourth region IV and the device formed in the third region have a larger difference in threshold voltage , so as to meet the performance requirements of semiconductor devices.

It should be noted that, in other embodiments, a gate-first process can also be used to form the first work function layer with the first thickness, the first work function layer with the second thickness, and the second work function layer with the third thickness. A work function layer and a second work function layer having a fourth thickness.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. A method for forming a semiconductor device with different threshold voltages, characterized in that it comprises: providing a substrate, the substrate comprising a first region and a second region, the first region and the second region being of the same region type; performing a first threshold voltage adjustment doping treatment on the substrate in the first region; forming a gate dielectric layer on the substrate surface of the first region and the second region; forming a first work function layer covering the surface of the gate dielectric layer in the first region and the second region, the first work function layer having a first thickness; Thinning the first work function layer in the first region, so that the first work function layer in the first region has a second thickness; forming a first gate electrode layer on the surface of the first work function layer having a second thickness; A second gate electrode layer is formed on the surface of the first work function layer in the second region. 2. The forming method according to claim 1, wherein the step of performing the thinning treatment comprises: forming a mask layer on the surface of the first work function layer in the second region; The layer is a mask, and a dry etching process is performed on the first work function layer in the first region; and the mask layer is removed. 3. The forming method according to claim 1, wherein the first region is a PMOS region; the second region is a PMOS region; the dopant ion of the first threshold voltage adjustment doping process is N type ions; the material of the first work function layer is a P type work function material. 4. The forming method according to claim 3, wherein the dopant ions of the first threshold voltage adjustment doping treatment are P or As; the material of the first work function layer is Ta, TiN, TaSiN Or one or more of TiSiN. 5. The forming method according to claim 1, wherein the first region is an NMOS region; the second region is an NMOS region; and the dopant ions in the threshold voltage adjustment doping process are P-type ions ; The material of the first work function layer is an N-type work function material. 6. The forming method according to claim 5, characterized in that, the dopant ion of the threshold voltage adjustment doping treatment is B, Ga or In; the material of the first work function layer is TiAl, TiAlC, TaAlN , TiAlN, MoN, TaCN or one or more of AlN. 7. The forming method according to claim 1, wherein the first thickness is 30 angstroms to 60 angstroms; the second thickness is 15 angstroms to 30 angstroms. 8. The forming method according to claim 1, wherein the first region further includes several subregions, wherein the bases of the several subregions are subjected to a first threshold voltage adjustment doping treatment, and the The doping concentrations of the first threshold voltage adjustment doping treatment performed on the substrates of the several sub-regions are different. 9. The forming method according to claim 8, wherein the plurality of sub-regions include a pull-up transistor region, an input-output transistor region, a standard threshold voltage region, and a low threshold voltage region; the second region is an ultra-low Threshold voltage region; or, the several subregions include pull-down transistor region, input and output transistor region, transfer gate transistor region, standard threshold voltage region and low threshold voltage region; the second region is an ultra-low threshold voltage region. 10 . The forming method according to claim 9 , wherein, among the gate dielectric layers on the base surface of the several sub-regions, the gate dielectric layer located on the base surface of the input-output transistor region has the thickest thickness. 11 . 11. The forming method according to claim 9, wherein the gate dielectric layer in the input-output transistor region includes an oxide layer and a high-k gate dielectric layer located on the surface of the oxide layer; the input-output transistor in the first region The gate dielectric layer outside the region includes an interface layer and a high-k gate dielectric layer located on the surface of the interface layer, wherein the thickness of the oxide layer is greater than that of the interface layer. 12. The forming method according to claim 8, characterized in that the thinning thickness of the first work function layer in several sub-regions of the first region is the same; or, the first region of the first region The first work function layer of several sub-regions undergoes thinning treatment with different thinning thicknesses. 13. The forming method according to claim 1, wherein before forming the first work function layer, a capping layer is formed on the surface of the gate dielectric layer; and an etch stop layer is formed on the surface of the capping layer. 14. The forming method according to claim 13, wherein the material of the capping layer is TiN; the material of the etching stop layer is TaN. 15. The forming method according to claim 1, wherein the substrate further comprises a third area and a fourth area, the area types of the third area and the fourth area are the same, and the third area, the fourth area The region is different from the region type of the first region and the second region; it also includes the step of: performing a second threshold voltage adjustment doping treatment on the base of the third region; the gate dielectric layer is also located in the third region and the fourth region the substrate surface; forming a second work function layer covering the gate dielectric layer, the second work function layer having a third thickness; thinning the second work function layer in the third region, so that the third region The second work function layer has a fourth thickness; a third gate electrode layer is formed on the surface of the second work function layer with the fourth thickness; a fourth gate electrode is formed on the surface of the second work function layer in the fourth region Floor. 16. The forming method according to claim 15, wherein the first work function layer is also located in the third area and the fourth area, and before forming the second work function layer, the layer located in the third area and the fourth area is removed. The first work function layer in the fourth area; the second work function layer is also located in the first area and the second area, and before forming the first gate electrode layer, the second work function layer located in the first area and the second area is removed. work function layer. 17. The forming method according to claim 15, wherein the first region and the second region are PMOS regions; the third region and the fourth region are NMOS regions; wherein the first region includes Several sub-regions, the several sub-regions of the first region include the pull-up transistor region, the first input and output transistor region, the first standard threshold voltage region and the first low threshold voltage region; the second region is the first ultra-low threshold voltage area; the third area includes several sub-areas, and the several sub-areas of the third area include a pull-down transistor area, a second input-output transistor area, a transfer gate transistor area, a second standard threshold voltage area, and a second low threshold voltage area; the fourth area is the second ultra-low threshold voltage area. 18. The forming method according to claim 17, wherein the material of the first work function layer is a P-type work function material; the material of the second work function layer is an N-type work function material. 19. The forming method according to claim 17, wherein the first threshold voltage adjustment doping treatment is performed on the substrates of the several sub-regions of the first region, and the substrates of the several sub-regions of the first region The doping concentration of the first threshold voltage adjustment doping treatment performed on the substrate is different; the second threshold voltage adjustment doping treatment is performed on the substrate of several sub-regions of the third region, and the several subregions of the third region The doping concentration of the second threshold voltage adjusting doping treatment performed on the substrate of each sub-region is different. 20. The forming method according to claim 1, wherein the base comprises a substrate and discrete fins located on a surface of the substrate.