CN106847755B - Method for improving SRAM performance - Google Patents

Abstract

A method for improving SRAM performance, comprising: forming a P-type work function layer on the surface of a gate dielectric layer in a P-type logic device region, and the P-type work function layer with the largest equivalent work function value is the first P-type work function layer; A pull-up work function layer is formed on the surface of the gate dielectric layer in the pull-up transistor region, and the material and thickness of the pull-up work function layer are the same as those of the first P-type work function layer; a first threshold voltage is applied to the substrate of the pull-up transistor region Adjust doping treatment; form an N-type work function layer on the surface of the gate dielectric layer in the N-type logic device region, and the N-type work function layer with the largest equivalent work function value is the first N-type work function layer; in the transfer gate transistor region A transfer gate work function layer is formed on the surface of the gate dielectric layer, and the transfer gate work function layer has the same material and thickness as the first N-type work function layer; a second threshold voltage adjustment doping treatment is performed on the substrate of the transfer gate transistor region. The invention improves the write redundancy of the memory and improves the overall performance of the semiconductor device.

Description

Ways to Improve SRAM Performance

technical field

The present invention relates to the technical field of semiconductor fabrication, in particular to a method for improving the performance of an SRAM.

Background technique

In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory and analog circuits, among which memory devices account for a considerable proportion of integrated circuit products. With the development of semiconductor technology, the memory device is more widely used, and the memory device and other device regions need to be simultaneously formed on a chip to form an embedded semiconductor memory device. For example, if the storage device is embedded in the central processing unit, it is necessary to make the storage device compatible with the embedded central processing unit platform, and maintain the original specifications and corresponding electrical performance of the storage device.

Typically, the memory device needs to be compatible with embedded standard logic devices. For an embedded semiconductor device, it is usually divided into a logic area and a storage area, the logic area usually includes logic devices, and the storage area includes storage devices. With the development of storage technology, various types of semiconductor memories have emerged, such as static random access memory (SRAM, Static Random Access Memory), dynamic random access memory (DRAM, Dynamic Random Access Memory), erasable programmable read-only memory ( EPROM, Erasable Programmable Read-Only Memory), Electrically Erasable Programmable Read-Only Memory (EEPROM, Electrically Erasable Programmable Read-Only) and Flash Memory (Flash). Due to the advantages of low power consumption and faster working speed of SRAM, more and more attention has been paid to SRAM and its forming method.

However, the performance of the SRAM in the semiconductor device formed by the prior art needs to be further improved, so that the overall performance of the semiconductor device is poor.

SUMMARY OF THE INVENTION

The problem solved by the present invention is to provide a method for improving the performance of the SRAM, to improve the write redundancy of the memory, thereby improving the overall performance of the formed semiconductor device.

In order to solve the above problems, the present invention provides a method for improving the performance of an SRAM, comprising: providing a substrate, the substrate includes an N-type logic device region, a P-type logic device region, a pull-up transistor region and a transfer gate transistor region, wherein the The N-type logic device region includes several N-type threshold voltage regions, the P-type logic device region includes several P-type threshold voltage regions, the N-type logic device region, the P-type logic device region, the pull-up transistor region and the A gate dielectric layer is formed on the surface of part of the substrate in the transfer gate transistor region; a P-type work function layer is formed on the surface of the gate dielectric layer in the P-type logic device region, and the P-type work function layers corresponding to the plurality of P-type threshold voltage regions The equivalent work function values are different, wherein the P-type work function layer with the largest equivalent work function value is the first P-type work function layer; a pull-up work function layer is formed on the surface of the gate dielectric layer in the pull-up transistor region, And the material and thickness of the pull-up work function layer are the same as those of the first P-type work function layer; the substrate of the pull-up transistor region is subjected to a first threshold voltage adjustment doping treatment; An N-type work function layer is formed on the surface of the gate dielectric layer in the logic device region, and the equivalent work function values of the N-type work function layers corresponding to the plurality of N-type threshold voltage regions are different, wherein, the N-type work function layer with the largest equivalent work function value The work function layer is a first N-type work function layer; a transfer gate work function layer is formed on the surface of the gate dielectric layer in the transfer gate transistor region, and the material and thickness of the transfer gate work function layer are the same as the first N-type work function The material and thickness of the layers are the same; a second threshold voltage adjustment doping treatment is performed on the substrate of the transfer gate transistor region; on the surface of the N-type work function layer, the surface of the P-type work function layer, the surface of the transfer gate work function layer and A gate electrode layer is formed on the surface of the pull-up work function layer.

Optionally, in the P-type work function layers corresponding to the several P-type threshold voltage regions, the thickness of the first P-type work function layer is the thickest; In the type work function layer, the thickness of the first N type work function layer is the thinnest.

Optionally, in the same process step, the pull-up work function layer and the first P-type work function layer are formed; in the same process step, the transfer gate work function layer and the first N-type work function layer are formed Floor.

Optionally, the doping ion used in the second threshold voltage adjustment doping treatment is B, and the doping concentration is 1E12 atom/cm ³ to 1E14 atom/cm ³ .

Optionally, the doping ions of the first threshold voltage doping treatment are As, and the doping concentration is 1E12 atoms/cm ³ to 1E14 atoms/cm ³ .

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the method for improving SRAM performance provided by the present invention, a P-type work function layer is formed on the surface of the gate dielectric layer in the P-type logic device region, and the P-type work function layers corresponding to the plurality of P-type threshold voltage regions are The work function values are different, wherein, the P-type work function layer with the largest equivalent work function value is the first P-type work function layer; a pull-up work function layer is formed on the surface of the gate dielectric layer in the pull-up transistor region, and the upper The material and thickness of the pull work function layer are the same as those of the first P-type work function layer. That is to say, the equivalent work function value of the pull-up work function layer in the pull-up transistor region is the same as the maximum equivalent work function value among the equivalent work function values of several P-type work function layers. With a fixed threshold voltage value, the concentration of doping ions in the first threshold voltage adjustment doping treatment on the substrate of the pull-up transistor region is relatively high, thereby reducing the saturation current and on-state current of the formed pull-up transistor. An N-type work function layer is formed on the surface of the gate dielectric layer in the N-type logic device region, and the equivalent work function values of the N-type work function layers corresponding to the plurality of N-type threshold voltage regions are different, wherein the equivalent work function value is the largest The N-type work function layer is the first N-type work function layer; a transfer gate work function layer is formed on the surface of the gate dielectric layer in the transfer gate transistor region, and the material and thickness of the transfer gate work function layer are the same as the first N-type work function layer. The material and thickness of the functional layer are the same. That is, the equivalent work function value of the transfer gate work function layer in the transfer gate transistor region is the same as the largest equivalent work function value among the equivalent work function values of several N-type work function layers. With a fixed threshold voltage value, the doping ion concentration of the second threshold voltage adjustment doping treatment performed on the substrate of the transfer gate transistor region is relatively low, so that the saturation current and on-state current of the formed transfer gate transistor are relatively large. Therefore, the gamma ratio of the memory in the semiconductor device formed by the present invention is improved, thereby improving the write redundancy of the memory, thereby improving the electrical performance of the formed memory and improving the overall performance of the semiconductor device.

Description of drawings

1 to 15 are schematic cross-sectional structural diagrams of a semiconductor device forming process according to an embodiment of the present invention.

Detailed ways

It can be known from the background art that the performance of the SRAM in the semiconductor device formed in the prior art needs to be improved.

For static random access memory, it mainly includes a pull-up (PU, Pull Up) transistor, a pull-down (PD, PullDown) transistor and a pass gate (PG, Pass Gate) transistor, and the write margin of the memory (write margin) The memory Performance plays a key role. If the write redundancy performance of the memory can be improved, the yield of the memory will be improved, and the overall performance of the semiconductor device will be improved accordingly. The study found that the write redundancy of the memory is proportional to the gamma ratio, which is the ratio between the on-state current of the pass-gate transistor and the on-state current of the pull-up transistor. The on-state current of the transfer gate transistor is related to the dopant ion concentration in the channel region of the transfer gate transistor. The lower the dopant ion concentration in the channel region of the transfer gate transistor, the greater the on-state current of the transfer gate transistor; The on-state current is related to the dopant ion concentration in the channel region of the pull-up transistor. The higher the dopant ion concentration in the channel region of the pull-up transistor, the smaller the on-state current of the pull-up transistor. Therefore, reducing the dopant ion concentration in the channel region of the transfer gate transistor or increasing the dopant ion concentration in the channel region of the pull-up transistor can increase the gamma ratio of the memory, thereby improving the write redundancy of the memory and improving the memory yield.

Further research found that for the transfer gate transistor, the transfer gate transistor is an NMOS transistor, and the transfer gate transistor generally has a fixed threshold voltage value (Vt). If the equivalent work function value (equal In order to maintain a fixed threshold voltage of the pass gate transistor, the threshold voltage of the corresponding pass gate transistor channel region is adjusted to lower the concentration of doping ions, so that the on-state current of the pass gate transistor increases. For the pull-up transistor, the pull-up transistor is a PMOS transistor, and the pull-up transistor generally also has a fixed threshold voltage. If a work function layer with a higher equivalent work function value is used when forming the pull-up transistor, in order to make The pull-up transistor maintains a fixed threshold voltage, and the threshold voltage in the channel region of the pull-up transistor should be adjusted to have a higher concentration of doping ions, so that the on-state current of the pull-up transistor is reduced.

Therefore, the present invention provides a method for improving the performance of SRAM. In the present invention, the equivalent work function value of the pull-up work function layer in the pull-up transistor region is: the equivalent of several P-type work function layers in the P-type logic device region The largest equivalent work function value in the work function value, in order to keep the pull-up transistor with a fixed threshold voltage value, the doping ion concentration of the first threshold voltage adjustment doping treatment on the substrate of the pull-up transistor region is relatively high , so that the saturation current and on-state current of the formed pull-up transistor are smaller; the equivalent work function value of the transfer gate work function layer in the transfer gate transistor region is: the equivalent work function value of several N-type work function layers in the N-type logic device region The largest equivalent work function value in the work function value, in order to keep the transfer gate transistor with a fixed threshold voltage value, the second threshold voltage performed on the substrate of the transfer gate transistor region adjusts the doping ion concentration of the doping treatment lower, which in turn results in higher saturation current and on-state current of the resulting pass-gate transistor. Therefore, the gamma ratio of the memory in the semiconductor device formed by the present invention is improved, thereby improving the write redundancy of the memory, thereby improving the electrical performance of the formed memory and improving the overall performance of the semiconductor device.

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

1 to 15 are schematic cross-sectional structural diagrams of a semiconductor device forming process according to an embodiment of the present invention.

Referring to FIG. 1, a substrate is provided that includes an N-type logic device region (not labeled), a P-type logic device region (not labeled), a pull-up transistor region I, and a pass-gate transistor region II.

The semiconductor device formed in this embodiment includes a logic device and an SRAM device. The N-type logic device region provides a process platform for the subsequent formation of N-type logic devices, the P-type logic device region provides a process platform for the subsequent formation of P-type logic devices, and the pull-up transistor region I provides for the subsequent formation of pull-up transistors. A process platform, the transfer gate transistor region II provides a process platform for the subsequent formation of transfer gate transistors. The pull-up transistor region I is a PMOS region, and the transfer gate transistor region II is an NMOS region.

The substrate further includes a pull-down transistor region III, the pull-down transistor region III provides a process platform for subsequent formation of the pull-down transistor, and the pull-down transistor region III is an NMOS region. The pull-up transistor region I, the transfer gate transistor region II, and the pull-down transistor region III are storage regions, which provide a process platform for the subsequent formation of the SRAM.

The P-type logic device region includes several P-type threshold voltage regions, wherein the P-type threshold voltage region includes a P-type ultra-low threshold voltage region (ULVT, Ultra-low VT) 11, a P-type standard threshold voltage region ( Standard VT) 12 and P-type high threshold voltage (High VT) region 13, the order of the threshold voltages of the P-type logic devices formed in each region from low to high is: P-type ultra-low threshold voltage region 11, P-type standard threshold voltage region 12. P-type high threshold voltage region 13 . The P-type logic device region can further include a P-type low threshold voltage region (not shown) and a P-type input output device region (IO, Input Output) (not shown).

The N-type logic device region includes several N-type threshold voltage regions, wherein the N-type threshold voltage includes an N-type ultra-low threshold voltage region 21, an N-type standard threshold voltage region 22 and an N-type high threshold voltage region 23, The threshold voltages of the N-type logic devices formed in each region are sorted from low to high: N-type ultra-low threshold voltage region 21 , N-type standard threshold voltage region 22 , and N-type high threshold voltage region 23 . The N-type logic device region can further include an N-type low threshold voltage region (not shown) and an N-type input-output device region (not shown).

In this embodiment, the semiconductor device formed is a fin field effect transistor as an example, and the base includes a substrate 101 and discrete fins 102 located on the surface of the substrate 101 .

In another embodiment, the semiconductor device is a planar transistor, the base is a planar base, and the planar base is a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate Or a germanium-on-insulator substrate, a glass substrate or a III-V group compound substrate (eg, a gallium nitride substrate or a gallium arsenide substrate, etc.), and the gate structure is formed on the surface of the planar base.

The material of the substrate 101 is silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium hydride, and the substrate 101 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; The material of the fins 102 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. In this embodiment, the substrate 101 is a silicon substrate, and the material of the fins 102 is silicon.

In this embodiment, the process steps of forming the substrate 101 and the fins 102 include: providing an initial substrate; forming a patterned hard mask layer 103 on the surface of the initial substrate; using the hard mask layer 103 For mask etching of the initial substrate, the etched initial substrate is used as the substrate 101 , and the protrusions on the surface of the substrate 101 are used as the fins 102 .

In one embodiment, the process steps of forming the hard mask layer 103 include: firstly forming an initial hard mask; forming a patterned photoresist layer on the surface of the initial hard mask; The resist layer is a mask to etch the initial hard mask to form a hard mask layer 103 on the surface of the initial substrate; remove the patterned photoresist layer.

In other embodiments, the formation process of the hard mask layer may further include: a self-aligned double patterned (SADP, Self-aligned Double Patterned) process, a self-aligned triple patterned (Self-aligned Triple Patterned) process, Or self-aligned quadruple patterning (Self-aligned Double Double Patterned) process. The double patterning process includes a LLE (Litho-Etch-Litho-Etch) process or an LLE (Litho-Litho-Etch) process.

In this embodiment, after the fins 102 are formed, the hard mask layer 103 on the top surface of the fins 102 remains. The material of the hard mask layer 103 is silicon nitride. During the subsequent planarization process, the top surface of the hard mask layer 103 can be used as a stop position of the planarization process to protect the top of the fins 102 . In this embodiment, the top dimension of the fins 102 is smaller than the bottom dimension. In other embodiments, the sidewalls of the fins can also be perpendicular to the surface of the substrate, that is, the top dimension of the fins is equal to the bottom dimension.

Referring to FIG. 2 , an isolation film 104 covering the surface of the substrate 101 and the surface of the fins 102 is formed, and the top of the isolation film 104 is higher than the top of the hard mask layer 103 .

Before forming the isolation film 104 , the method further includes the step of: oxidizing the substrate 101 and the fins 102 to form a linear oxide layer on the surface of the substrate 101 and the surface of the fins 102 .

The isolation film 104 provides a technological basis for the subsequent formation of the isolation layer; the material of the isolation film 104 is an insulating material, such as silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation film 104 is silicon oxide.

In order to improve the gap-filling capability of the process of forming the isolation film 104 , the isolation film 104 is formed by flow chemical vapor deposition (FCVD, Flowable CVD) or high aspect ratio chemical vapor deposition (HARP CVD).

After the isolation film 104 is formed, the method further includes the step of: annealing the isolation film 104 to improve the density of the isolation film 104 .

Referring to FIG. 3 , a partial thickness of the isolation film 104 (refer to FIG. 2 ) is removed to form an isolation layer 114 , the isolation layer 114 is located on the surface of the substrate 101 and covers part of the sidewall surface of the fin 102 , and the top of the isolation layer 114 is lower than the fin section 102 at the top.

The material of the isolation layer 114 is silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation layer 114 is silicon oxide.

In one embodiment, a dry etching process is used to remove a part of the thickness of the isolation film 104 by etching. In another embodiment, a wet etching process is used to etch and remove a part of the thickness of the isolation film 104 .

It also includes the step of removing the hard mask layer 103 by etching (refer to FIG. 2 ). It can also include the step of: forming a shielding layer on the top and sidewall surfaces of the fins 102 and the surface of the isolation layer 114, the shielding layer is made of silicon oxide or silicon oxynitride, and its function is to: in the subsequent doping treatment During the process, the shielding layer can reduce the lattice damage to the fins 102 caused by the doping treatment.

It also includes the steps of: performing an N-type well region doping process on the P-type logic device region and the pull-up transistor region I, and forming an N-type well region in the substrate of the P-type logic device region and the pull-up transistor region I; P-type well region doping treatment is performed on the N-type logic device region, transfer gate transistor region II and pull-down transistor region III, in the substrate of the N-type logic device region, transfer gate transistor region II and pull-down transistor region III A P-type well region is formed.

Referring to FIG. 4 , a first threshold voltage adjustment doping treatment is performed on the substrate of the pull-up transistor region I.

In this embodiment, the pull-up transistor region I is a PMOS region, and the doping ions for the first threshold voltage adjustment doping treatment are N-type ions, and the N-type ions are P, As or Sb. The first threshold voltage adjustment doping treatment is actually doping the channel region below the gate structure of the pull-up transistor formed subsequently. A threshold voltage adjusts the doping process.

The process steps of performing the first threshold voltage adjustment doping treatment on the substrate of the pull-up transistor region I include: forming a first pattern layer 105 on the surface of the isolation layer 114 and the surface of the fin 102, and the first pattern layer 105 Expose the base surface of the pull-up transistor region I; use the first pattern layer 105 as a mask to perform N-type ion implantation on the fins 102 of the pull-up transistor region I; then, remove the first pattern layer 105 .

In this embodiment, the equivalent work function value of the pull-up work function layer subsequently formed on the substrate of the pull-up transistor region I is relatively high. Specifically, P-type threshold voltage regions with different equivalent work function values are subsequently formed in each P-type threshold voltage region. type work function layer, wherein, the P-type work function layer with the largest equivalent work function value is the first P-type work function layer, and the pull-up work function layer formed subsequently in this embodiment and the first P-type work function layer are Material and thickness are the same. Therefore, for the pull-up transistor, the equivalent work function value of the pull-up work function layer in the pull-up transistor is relatively large. In order to make the formed pull-up transistor have a fixed threshold voltage, the pull-up transistor region I substrate is The doping ion concentration of the first threshold voltage adjustment doping treatment performed should be high. In this embodiment, the doping ions in the first threshold voltage doping treatment are As, and the doping concentration is 1E12 atoms/cm ³ to 1E14 atoms/cm ³ .

Compared with the doping concentration of the threshold voltage adjustment doping treatment performed on the substrate of the pull-up transistor region in the prior art, the doping concentration of the first threshold voltage adjustment doping treatment performed on the substrate of the pull-up transistor region I in this embodiment is The concentration of impurity ions is higher. It can also be considered that the concentration of impurity ions in the I-channel region of the pull-up transistor region in this embodiment is higher, so the saturation current and on-state current of the pull-up transistor formed in this embodiment are lower. The resulting pull-up transistor has a lower operating current.

In a specific embodiment, the first threshold voltage adjustment doping treatment is performed by an ion implantation process, and the process parameters of the first threshold voltage adjustment doping treatment include: the implanted ions are As, the implantation energy is 5kev to 15kev, The implantation dose is 1E12atom/cm ² to 1E14atom/cm ² , the implantation angle is 0 degree to 15 degrees, the twist angle is 23 degrees, and the number of injections is 4 times.

It also includes the step of: performing N-type threshold voltage adjustment doping treatment on the P-type logic device region substrate. Specifically, N-type threshold voltage adjustment doping treatment is performed on the substrates of the P-type ultra-low threshold voltage region 11 , the P-type standard threshold voltage region 12 and the P-type high threshold voltage region 13 . According to the required threshold voltage range of a device formed by several P-type threshold voltage regions, the doping concentration for performing the N-type threshold voltage adjustment doping treatment on each P-type threshold voltage region is determined. In this embodiment, the doping concentrations of the N-type threshold voltage adjustment doping treatments performed on the P-type ultra-low threshold voltage region 11 , the P-type standard threshold voltage region 12 and the P-type high threshold voltage region 13 are different.

Referring to FIG. 5 , a second threshold voltage adjustment doping process is performed on the substrate of the transfer gate transistor region II.

In this embodiment, the transfer gate transistor region II is an NMOS region, the doping ions for the second threshold voltage adjustment doping treatment are P-type ions, and the P-type ions are B, Ga, or In. The second threshold adjustment doping process is actually doping the channel region below the gate structure of the transfer gate transistor formed subsequently. Threshold voltage adjustment doping treatment.

The process steps of performing the second threshold voltage adjustment doping treatment on the substrate of the transfer gate transistor region II include: forming a second pattern layer 106 on the surface of the isolation layer 114 and the surface of the fin 102 , the second pattern layer 106 exposing the base surface of the transfer gate transistor region II; using the second pattern layer 106 as a mask to perform P-type ion implantation on the fins 102 of the transfer gate transistor region II; then, removing the second pattern layer 106.

In this embodiment, the equivalent work function value of the transfer gate work function layer subsequently formed on the surface of the gate dielectric layer of the transfer gate transistor region II is relatively high. Specifically, the equivalent work function values of the subsequent N-type threshold voltage regions will be different. The N-type work function layer, wherein, the N-type work function layer with the largest equivalent work function value is the first N-type work function layer, and the transmission gate work function layer formed subsequently in this embodiment and the first N-type work function layer The material and thickness of the layers are the same.

Therefore, for the transfer gate transistor, the equivalent work function value of the transfer gate work function layer in the transfer gate transistor is relatively large. In order to make the formed transfer gate transistor have a fixed threshold voltage, in this embodiment, the transfer gate transistor region II is The doping ion concentration of the second threshold voltage adjustment doping treatment performed on the substrate should be low. In this embodiment, the doping ion used in the second threshold voltage adjustment doping treatment is B, and the doping concentration is 1E12 atom/cm ³ to 1E14 atom/cm ³ .

Compared with the doping concentration of the threshold voltage adjustment doping treatment performed on the substrate of the transfer gate transistor region in the prior art, the doping concentration of the second threshold voltage adjustment doping treatment performed on the transfer gate transistor region II substrate in this embodiment is The impurity ion concentration is lower, and it can also be considered that the dopant ion concentration in the channel region II of the transfer gate transistor region in this embodiment is lower, so the correspondingly formed transfer gate transistor in this embodiment has lower saturation current and on-state current, The resulting transfer gate transistor has a lower operating current.

In a specific embodiment, the second threshold voltage adjustment doping treatment is performed by an ion implantation process, and the process parameters of the second threshold voltage adjustment doping treatment include: the implanted ions are B, the implantation energy is 2kev to 5kev, The implantation dose is 1E12atom/cm ² to 1E14atom/cm ² , the implantation angle is 0° to 15°, the implantation twist angle is 23°, and the implantation times are 4 times.

It also includes the steps of: performing a third threshold voltage adjustment doping treatment on the substrate of the pull-down transistor region III, and the doping ions of the third threshold voltage adjustment doping treatment are P-type ions; The substrate is subjected to P-type threshold voltage adjustment doping treatment. Specifically, the substrates of the N-type ultra-low threshold voltage adjustment region 21 , the N-type standard threshold voltage region 22 and the N-type high threshold voltage region 23 are subjected to P-type threshold voltage adjustment doping treatment. According to the required threshold voltage range of the device formed by several N-type threshold voltage regions, the doping concentration for performing the P-type threshold voltage adjustment doping treatment on each N-type threshold voltage region is determined. In this embodiment, the N-type ultra-low threshold voltage region 21 , the N-type standard threshold voltage region 22 and the N-type high threshold voltage region 23 have different doping concentrations for the P-type threshold voltage adjustment doping treatment.

The gate structure will be formed on the surface of the substrate later. In this implementation, the gate structure is formed by using a gate last process as an example, that is, the gate structure is formed after the source/drain region (S/D, Source/Drain) is formed. . In other embodiments, the gate structure can also be formed by a gate first process, and the gate structure is formed before the source and drain regions are formed.

Referring to FIG. 6, a dummy oxide film is formed on the substrate surface of the pull-up transistor region I, the P-type logic device region, the N-type logic device region, the transfer gate transistor region II and the pull-down transistor region II; dummy gate film; patterning the dummy gate film and the dummy oxide film to form parts of the substrate surface located in the N-type logic device region, the P-type logic device region, the pull-up transistor region I, the transfer gate transistor region II and the pull-down transistor region III The dummy oxide layer 201 forms a dummy gate layer 202 on the surface of the oxide layer 201 .

The dummy gate layer 202 occupies the space position of the gate structure formed subsequently. The material of the dummy oxide layer 201 is silicon oxide or silicon oxynitride, and the material of the dummy gate layer 202 is polysilicon, amorphous silicon or amorphous carbon. In this embodiment, the material of the dummy oxide layer 201 is silicon oxide, and the material of the dummy gate layer 202 is polysilicon.

It also includes the steps of: forming offset spacers on the sidewall surfaces of the dummy gate layer 202; lightly doping the N-type logic device region fins 102 on both sides of the dummy gate layer 202 to form an N-type LDD region, In this embodiment, the fins 102 of each N-type threshold voltage region in the N-type logic device region are lightly doped; the fins 102 of the P-type logic device region on both sides of the dummy gate layer 202 are lightly doped. Doping treatment to form a P-type LDD region, in this embodiment, includes lightly doping the fins 102 of each P-type threshold voltage region in the P-type logic device region; pull-up on both sides of the dummy gate layer 202 The transistor region I fins 102 are lightly doped to form a pull-up LDD region; the transfer gate transistor region II fins 102 on both sides of the dummy gate layer 202 are lightly doped to form a transfer gate LDD region; The pull-down transistor region III fins 102 on both sides of the dummy gate layer 202 are lightly doped to form pull-down LDD regions.

It also includes the steps of: forming a main spacer on the sidewall surface of the offset spacer; performing heavy doping treatment on the N-type logic device region fins 102 on both sides of the dummy gate layer 202 to form an N-type S/D region In this embodiment, the fins 102 of each N-type threshold voltage region in the N-type logic device region are heavily doped; the fins 102 of the P-type logic device region on both sides of the dummy gate layer 202 are heavily doped Doping treatment to form a P-type S/D region, in this embodiment, including heavy doping treatment on the fins 102 of each P-type threshold voltage region in the P-type logic device region; on both sides of the dummy gate layer 202 The fins 102 of the pull-up transistor region I are heavily doped to form a pull-up S/D region; the fins 102 of the transfer gate transistor region II on both sides of the dummy gate layer 202 are heavily doped to form a transfer gate S/D region; the pull-down transistor region III fins 102 on both sides of the dummy gate layer 202 are heavily doped to form a pull-down S/D region.

Referring to FIG. 7 , the dummy gate layer 202 (refer to FIG. 6 ) and the dummy oxide layer 201 (refer to FIG. 6 ) are removed.

Before removing the dummy gate layer 202 , the method further includes the step of forming an interlayer dielectric layer (not shown) on the surface of the substrate, and the interlayer dielectric layer covers the sidewall surface of the dummy gate layer 202 .

The dummy gate layer 202 and the dummy oxide layer 201 are removed by etching using a dry etching process, a wet etching process or a SiCoNi etching system. During the process of removing the dummy gate layer 202 , the dummy oxide layer 201 functions to protect the fins 102 .

Next, referring to FIG. 8 , an interface layer 204 is formed on the substrate surface of the N-type logic device region, the P-type logic device region, the pull-up transistor region I, the transfer gate transistor region II, and the pull-down transistor region III.

The interface layer 204 is a part of the gate dielectric layer formed subsequently, and the material of the interface layer 204 is silicon oxide or silicon oxynitride. In this embodiment, the interface layer 204 is formed by an oxidation process, and the oxidation process is dry oxygen oxidation, wet oxygen oxidation or water vapor oxidation, and the formed interface layer 204 is only located on the exposed top surface and sidewall surface of the fin 102 .

In other embodiments, the interface layer is formed by a deposition process, and the deposition process is chemical vapor deposition, physical vapor deposition or atomic layer deposition, and the formed interface layer is also located on the surface of the isolation layer.

Continuing to refer to FIG. 8 , a high-k gate dielectric layer 205 is formed on the surface of the interface layer 204 .

In this embodiment, the high-k gate dielectric layer 205 is also located on the surface of the isolation layer 114 and the sidewall surface of the interlayer dielectric layer (not shown). The material of the high-k gate dielectric layer 205 is a high-k gate dielectric material, wherein the high-k gate dielectric material refers to a gate dielectric material with a relative dielectric constant greater than that of silicon oxide, and the high-k gate dielectric material The material of the layer 205 is HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO ₂ or Al ₂ O ₃ .

The high-k gate dielectric layer 205 is formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In this embodiment, the material of the high-k gate dielectric layer 205 is HfO ₂ , the thickness of the high-k gate dielectric layer 205 is 5 angstroms to 15 angstroms, and the high-k gate dielectric layer 205 is formed by an atomic layer deposition process. .

The stacked structure of the interface layer 204 and the high-k gate dielectric layer 205 on the surface of the interface layer 204 is used as a gate dielectric layer, so the N-type logic device region, P-type logic device region, pull-up transistor region I, transfer gate A gate dielectric layer is formed on the substrate surfaces of the transistor region II and the pull-down transistor region III. Specifically in this embodiment, the gate dielectric layer spans the fins 102 and covers a part of the top surface and sidewall surfaces of the fins 102 .

Subsequently, an N-type work function layer will be formed on the surface of the gate dielectric layer in the N-type logic device region, and a P-type work function layer will be formed on the surface of the gate dielectric layer in the P-type logic device region. In this embodiment, the P-type work function layer of the P-type logic device region is formed first, and then the N-type work function layer of the N-type logic device region is formed as an example for detailed description. In other embodiments, the N-type work function layer of the N-type logic device region can also be formed first, and then the P-type work function layer of the P-type logic device region can be formed.

Referring to FIG. 9 , a P-type work function layer 208 is formed on the surface of the gate dielectric layer in the P-type logic device region.

In this embodiment, the formed P-type work function layer is also located on the surface of the gate dielectric layer in the pull-up transistor region I, and the P-type work function layer 208 is also located in the N-type logic device region, the transfer gate transistor region II and the pull-down transistor region. The surface of the gate dielectric layer in region III.

Before forming the P-type work function layer 208, the method further includes the steps of: forming a capping layer (not shown) on the surface of the high-k gate dielectric layer 205; forming an etch stop layer (not shown) on the surface of the capping layer ).

The cap layer plays a role in protecting the high-k gate dielectric layer 205, preventing unnecessary etching losses to the high-k gate dielectric layer 205 caused by the subsequent etching process, and the cap layer is also conducive to blocking metal ions from entering the high-k gate dielectric layer 205. Diffusion in the gate dielectric layer 205 . The material of the capping layer is TiN; the capping layer is formed by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

The material of the etch stop layer is different from that of the formed P-type work function layer 208 and the subsequently formed N-type work function layer, so that the etching process of the subsequent etching process of the P-type work function layer 208 can etch the etch stop layer. The etching rate is small, and the etching rate of the subsequent etching process for etching the N-type work function layer is small for the etching stop layer, so as to avoid etching damage to the high-k gate dielectric layer 205 . In this embodiment, the material of the etch stop layer is TaN, and the etch stop layer is formed by an atomic layer deposition process.

The material of the P-type work function layer 208 is one or more of Ta, TiN, TaSiN or TiSiN. The P-type work function layer 208 is formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition.

In this embodiment, the material of the P-type work function layer 208 is TiN, the P-type work function layer 208 has a third thickness, and the third thickness is 45 angstroms to 55 angstroms, for example, 50 angstroms.

In this embodiment, since the P-type logic device region includes a P-type ultra-low threshold voltage region 11 , a P-type standard threshold voltage region 12 and a P-type high threshold voltage region, in order to meet device requirements, each region of the P-type logic device region forms The difference between the threshold voltages of the devices is large, and it is difficult to obtain a threshold voltage with a large difference only by means of the aforementioned P-type threshold voltage adjustment and doping treatment. To this end, in this embodiment, the P-type work function layer 208 of the P-type high threshold voltage region 13 is further etched, and the P-type work function layer 208 of the P-type high threshold voltage region 13 is thinned, thereby making the P-type high threshold voltage region 13 thinner. The equivalent work function value of the P-type work function layer in the voltage region 13 is reduced, thereby further increasing the threshold voltage value of the device formed by the P-type high threshold voltage region 13, so that the threshold voltage of the device formed in each region of the P-type logic device region is increased. The difference between is large.

Referring to FIG. 10, a second mask layer 209 is formed on the surface of the P-type work function layer 208, and the second mask layer exposes the surface of the P-type work function layer 208 of the P-type high threshold voltage region 13; The second mask layer 209 is a mask, and the second thickness of the P-type work function layer 208 located in the P-type high threshold voltage region 13 is removed by etching.

The second mask layer 209 also covers the surface of the P-type work function layer 208 in the pull-up transistor region I, and is also located on the surface of the P-type work function layer 208 in the transfer gate transistor region II, the N-type logic device region and the pull-down transistor region III. . In other embodiments, the second mask layer further exposes the transfer gate transistor, the N-type logic device region and the P-type work function layer surface of the pull-down transistor region, so that the transfer gate transistor, the N-type logic device region and the pull-down transistor region are subsequently removed. The process duration of the P-type work function layer in the pull-down transistor region is shorter.

In this embodiment, the material of the second mask layer 209 is a photoresist material. In other embodiments, the material of the second mask layer can also be silicon nitride or boron nitride.

A dry etching process, a wet etching process or a SiCoNi etching system is used to etch and remove the P-type work function layer 208 of the second thickness of the P-type high threshold voltage region 13 .

After the etching process is completed, the equivalent work function values of the P-type work function layers 208 corresponding to the plurality of P-type threshold voltage regions are different, and the P-type work function layer 208 with the largest equivalent work function value is the first The P-type work function layer 218, therefore, the unetched P-type work function layer 208 in the P-type logic device region is the first P-type work function layer 218. Specifically in this embodiment, the P-type ultra-low threshold The P-type work function layer 208 corresponding to the voltage region 11 is the first P-type work function layer 218 . Among the P-type work function layers 208 corresponding to the plurality of P-type threshold voltage regions, the thickness of the first P-type work function layer 218 is the thickest.

Since the second mask layer 209 also covers the surface of the P-type work function layer 208 in the pull-up transistor region I, the P-type work function layer 208 in the pull-up transistor region I is also not etched, and the pull-up transistor region I is not etched. The etched P-type work function layer 208 is the pull-up work function layer 228 . Therefore, in this embodiment, a pull-up work function layer 228 is formed on the surface of the gate dielectric layer of the pull-up transistor region I, and the materials and thicknesses of the pull-up work function layer 228 and the first P-type work function layer 218 are same. In addition, in this embodiment, the pull-up work function layer 228 and the first P-type work function layer 218 are formed in the same process step, and there is no need to use an additional mask for forming the pull-up work function layer 228 .

In this embodiment, the thickness of the first P-type work function layer 218 is 45 angstroms to 55 angstroms, for example, 50 angstroms; the thickness of the pull-up work function layer 228 in the pull-up transistor region I is 45 angstroms to 55 angstroms. Angstrom, for example, 50 angstroms; the thickness of the etched P-type work function layer 208 is 25 angstroms to 35 angstroms, for example, 30 angstroms, that is, in the P-type logic device region, except for the first P-type work function layer 208 The thickness of the p-type work function layer 208 other than the type work function layer 218 is 25 angstroms to 35 angstroms.

In this embodiment, since the equivalent work function value of the pull-up work function layer 228 in the pull-up transistor region I is selected as: the maximum equivalent work function value of several P-type work function layers corresponding to the P-type logic device region Therefore, in order to make the pull-up transistor formed in the pull-up transistor region I have a fixed threshold voltage, the doping concentration of the first threshold voltage adjustment doping treatment performed on the substrate of the pull-up transistor region I is high, so that the pull-up transistor formed in the pull-up transistor region I has a high doping concentration. The doping concentration of the transistor channel region is high, so the saturation current and on-state current of the pull-up transistor are small.

In other embodiments, the P-type work function layers of other P-type threshold voltage regions other than the P-type high threshold voltage region in the P-type logic device region can also be etched and thinned, and the P-type work function layers of the other P-type threshold voltage regions The thickness of the P-type work function layer to be etched and thinned can also be different, ensuring that the P-type work function layer with the largest equivalent work function value in the P-type logic device region is the first P-type work function layer, and the pull-up work function layer is The material and thickness are the same as those of the first P-type work function layer. It can also be considered that for the P-type work function layer with the same material, the thickest P-type work function in the P-type logic device region The layer is the first P-type work function layer.

Next, referring to FIG. 11 , the second mask layer 209 (refer to FIG. 10 ) is removed; the P-type work function layer 208 located in the N-type logic device region, the transfer gate transistor region II and the pull-down transistor region III is removed by etching.

Specifically, a third mask layer (not shown) is formed on the surface of the P-type work function layer 208 in the P-type logic device region and the surface of the pull-up work function layer 228 in the pull-up transistor region I. The film exposes the surface of the P-type work function layer 208 of the N-type logic device region, the transfer gate transistor region II and the pull-down transistor region III; using the third mask layer as a mask, etch to remove the N-type logic device region, The P-type work function layer 208 of the transfer gate transistor region II and the pull-down transistor region III; then, the third mask layer is removed.

In other embodiments, the P-type work function layer located in the N-type logic device region, the transfer gate transistor region and the pull-down transistor region can also be removed first, and then the P-type work function layer in the P-type logic device region can be etched .

Referring to FIG. 12 , an N-type work function layer 211 is formed on the surface of the gate dielectric layer in the N-type logic device region.

In this embodiment, the formed N-type work function layer 211 is also located on the surface of the gate dielectric layer of the transfer gate transistor region II, and the N-type work function layer 211 is also located on the surface of the P-type work function layer 208. The surface of the function layer 218, the surface of the pull-up work function layer 228, and the surface of the gate dielectric layer of the pull-down transistor region III.

The material of the N-type work function layer 211 is one or more of TiAl, TiAlC, TaAlN, TiAlN, MoN, TaCN or AlN. The N-type work function layer 211 is formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition.

In this embodiment, the material of the N-type work function layer 211 is TiAlC, the N-type work function layer 211 has a fourth thickness, and the fourth thickness is 45 angstroms to 55 angstroms, for example, 50 angstroms.

Since the N-type logic device region includes an N-type ultra-low threshold voltage region 21, an N-type standard threshold voltage region 22 and an N-type high threshold voltage region 23, in order to meet the device requirements, the threshold voltage of the device formed in each region of the N-type logic device region The difference between them is large, and it is difficult to obtain a threshold voltage with a large difference only by the above-mentioned N-type threshold voltage adjustment and doping treatment.

To this end, in this embodiment, the N-type work function layer 211 of the N-type high threshold voltage region 23 is further etched, the N-type work function layer 211 of the N-type high threshold voltage region 23 is thinned, and the N-type high threshold voltage region 23 is further increased. The threshold voltage values of the devices formed by the threshold voltage region 23 make the difference between the threshold voltages of the devices formed by each region of the N-type logic device region relatively large.

13, a first mask layer 212 is formed on the surface of the N-type work function layer 211, and the first mask layer 212 exposes the surface of the N-type work function layer 211 of the N-type high threshold voltage region 23; The first mask layer 212 is a mask, and the N-type work function layer 211 of the second thickness located in the N-type high threshold voltage region 23 is removed by etching.

The first mask layer 212 also exposes the surface of the N-type work function layer 211 of the transfer gate transistor region II, and also covers the pull-up transistor region I, the pull-down transistor region III and the N-type work function layer of the P-type logic device region. 211 Surface. In other embodiments, the first mask layer can also expose the surface of the N-type work function layer of the pull-up transistor region, the pull-down transistor region or the P-type logic device region.

In this embodiment, the material of the first mask layer 212 is a photoresist material. In other embodiments, the material of the first mask layer can also be silicon nitride or boron nitride.

A dry etching process, a wet etching process or a SiCoNi etching system is used to etch and remove the N-type work function layer 211 of the first thickness of the N-type high threshold voltage region 23 .

After the etching is completed, the equivalent work function values of the N-type work function layers 211 corresponding to the plurality of N-type threshold voltage regions are different, wherein the N-type work function layer 211 with the largest equivalent work function value is the first N-type work function layer 211 . Therefore, the etched N-type work function layer 211 in the N-type logic device region is the first N-type work function layer 221 . Specifically in this embodiment, the N-type work function layer 211 corresponding to the N-type high threshold voltage region 23 is the first N-type work function layer 221 . Among the N-type work function layers 211 corresponding to the plurality of N-type threshold voltage regions, the thickness of the first N-type work function layer 221 is the thinnest.

Since the first mask layer 212 also exposes the surface of the N-type work function layer 211 in the transfer gate transistor region II, while the N-type work function layer 211 of the first thickness in the N-type high threshold voltage region 23 is removed by etching, The N-type work function layer 211 with the first thickness on the surface of the gate dielectric layer in the transfer gate transistor region II is also etched and removed. The etched N-type work function layer 211 in the transfer gate transistor region II is the transfer gate work function layer 231 .

Therefore, in this embodiment, a transfer gate work function layer 231 is formed on the surface of the gate dielectric layer of the transfer gate transistor region II, and the transfer gate work function layer 231 and the first N-type work function layer 221 have the same material and thickness . In this embodiment, the transfer gate work function layer 231 and the first N-type work function layer 221 are formed in the same process step, and there is no need to use an additional mask for forming the transfer gate work function layer 231 .

In the N-type logic device region, the thickness of the N-type work function layer 211 other than the first N-type work function layer 221 is 45 angstroms to 55 angstroms, eg, 50 angstroms; the first N-type work function layer 211 has a thickness of 50 angstroms. The thickness of the work function layer 221 is 25 angstroms to 35 angstroms, for example, 30 angstroms; the thickness of the transfer gate work function layer 231 is 25 angstroms to 35 angstroms, for example, 30 angstroms.

In this embodiment, since the equivalent work function value of the transfer gate work function layer 231 in the transfer gate transistor region II is selected as: the maximum equivalent work function value of several corresponding N-type work function layers in the N-type logic device region Therefore, in order to make the transfer gate transistor formed in the transfer gate transistor region II have a fixed threshold voltage, the doping concentration of the second threshold voltage adjustment doping treatment performed on the transfer gate transistor region II substrate is low, so that the transfer gate formed The doping concentration of the transistor channel region is low, and the saturation current and on-state current of the transfer gate transistor are large.

In other embodiments, the N-type work function layers of other N-type threshold voltage regions in the N-type logic device region can also be etched and thinned, and the N-type work function layers of other N-type threshold voltage regions can be etched The thickness of the thinning can also be different, ensuring that the N-type work function layer with the largest equivalent work function value in the N-type logic device region is the first N-type work function layer, and the material and thickness of the transfer gate work function layer are the same as those of the first N-type work function layer. The material and thickness of the type work function layer can be the same. It can also be considered that for the N type work function layer with the same material, the N type work function layer with the thinnest thickness in the N type logic device region is the first N type work function. Floor.

Next, referring to FIG. 14 , the first mask layer 212 (refer to FIG. 13 ) is removed; the N-type work function layer 211 located in the pull-up transistor region I and the P-type logic device region is removed.

Specifically, a fourth mask layer (not shown) is formed on the surface of the transfer gate work function layer 231 in the transfer gate transistor region II, and the fourth mask layer also covers the N-type work function layer in the pull-down transistor region III 211 and the N-type work function layer 211 in the N-type logic device region; using the fourth mask layer as a mask, etch and remove the N-type work function layer 211 located in the pull-up transistor region I and the P-type logic device region; Next, the fourth mask layer is removed.

In other embodiments, the N-type work function layer in the pull-up transistor region and the P-type logic device region can also be removed first, and then the N-type work function layer in the N-type high threshold voltage region is etched and thinned.

In another embodiment, since the N-type work function layer has less influence on the threshold voltage of the pull-up transistor and the P-type logic device, the pull-up transistor region and the N-type work function layer of the P-type logic device region can also be reserved.

15 , a gate electrode layer 301 is formed on the surface of the N-type work function layer 211 , the P-type work function layer 208 , the transfer gate work function layer 231 , and the pull-up work function layer 228 .

In this embodiment, the P-type work function layer 208 includes a first P-type work function layer 218 located in the P-type ultra-low threshold voltage region 11 , and the N-type work function layer 211 includes a first P-type work function layer 218 located in the N-type high threshold voltage region 23 The first N-type work function layer 221 . The gate electrode layer 301 is also located on the surface of the N-type work function layer 211 of the pull-down transistor region III.

The gate electrode layers 301 located on the surface of the N-type work function layer 211 , the P-type work function layer 208 , the transfer gate work function layer 231 and the pull-up work function layer 228 are connected to each other. In other embodiments, the gate electrode layers located on the surface of the N-type work function layer, the P-type work function layer, the transfer gate work function layer, and the pull-up work function layer can also be independent of each other.

The material of the gate electrode layer 301 includes one or more of Al, Cu, Ag, Au, Pt, Ni, Ti or W.

In a specific embodiment, the process steps of forming the first gate electrode layer 301 include: on the surface of the N-type work function layer 211 , the surface of the P-type work function layer 208 , the surface of the transfer gate work function layer 231 , and pull-up A gate electrode film is formed on the surface of the work function layer 228 , and the top of the gate electrode film is higher than the top of the interlayer dielectric layer; the gate electrode film above the top of the interlayer dielectric layer is removed by grinding to form the gate electrode layer 301 .

It can be seen from the foregoing analysis that the saturation current and on-state current of the pull-up transistor formed in this embodiment are low, while the saturation current and on-state current of the transfer gate transistor formed are relatively high. The ratio between the state current and the on-state current of the pull-up transistor is proportional, so the gamma of the memory formed in this embodiment is relatively large, thereby improving the write redundancy of the memory and the corresponding performance of the memory. For example, the yield of memory is improved, which in turn improves the performance of the resulting semiconductor device.

In addition, in this embodiment, the pull-up transistor, pull-down transistor and transfer gate transistor in the memory are formed while the logic device is formed, so that the formed memory has a large write redundancy, and the process of forming the memory and the logic of forming the memory are also formed. The process of the device is compatible, the process steps are saved, an extra mask is not needed to improve the write redundancy of the memory, and the semiconductor production cost is saved.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (20)

1. a method for improving SRAM performance, is characterized in that, comprises: A substrate is provided, the substrate includes an N-type logic device region, a P-type logic device region, a pull-up transistor region, and a pass-gate transistor region, wherein the N-type logic device region includes a plurality of N-type threshold voltage regions, the P-type logic device region The type logic device region includes several P-type threshold voltage regions, and a gate dielectric layer is formed on part of the substrate surface of the N-type logic device region, the P-type logic device region, the pull-up transistor region and the transfer gate transistor region; A P-type work function layer is formed on the surface of the gate dielectric layer in the P-type logic device region, and the equivalent work function values of the P-type work function layers corresponding to the plurality of P-type threshold voltage regions are different, wherein the equivalent work function The P-type work function layer with the largest value is the first P-type work function layer; A pull-up work function layer is formed on the surface of the gate dielectric layer of the pull-up transistor region, and the material and thickness of the pull-up work function layer are the same as those of the first P-type work function layer; performing a first threshold voltage adjustment doping treatment on the substrate of the pull-up transistor region; An N-type work function layer is formed on the surface of the gate dielectric layer in the N-type logic device region, and the equivalent work function values of the N-type work function layers corresponding to the plurality of N-type threshold voltage regions are different, wherein the equivalent work function The N-type work function layer with the largest value is the first N-type work function layer; A transfer gate work function layer is formed on the surface of the gate dielectric layer in the transfer gate transistor region, and the material and thickness of the transfer gate work function layer are the same as those of the first N-type work function layer; performing a second threshold voltage adjustment doping treatment on the substrate of the transfer gate transistor region; A gate electrode layer is formed on the surface of the N-type work function layer, the P-type work function layer, the transfer gate work function layer, and the pull-up work function layer. 2 . The method of claim 1 , wherein the transfer gate transistor region is an NMOS region; the pull-up transistor region is a PMOS region. 3 . 3. The method for improving SRAM performance according to claim 1, wherein in the P-type work function layers corresponding to the plurality of P-type threshold voltage regions, the thickness of the first P-type work function layer is the thickest ; Among the N-type work function layers corresponding to the plurality of N-type threshold voltage regions, the thickness of the first N-type work function layer is the thinnest. 4. The method for improving SRAM performance according to claim 1, wherein in the same process step, the pull-up work function layer and the first P-type work function layer are formed; in the same process step, the pull-up work function layer and the first P-type work function layer are formed; The transfer gate work function layer and the first N-type work function layer. 5. the method for improving SRAM performance as claimed in claim 1 is characterized in that, the material of described P-type work function layer is one or more in Ta, TiN, TaSiN or TiSiN; Described N-type work function layer The material is one or more of TiAl, TiAlC, TaAlN, TiAlN, MoN, TaCN or AlN. 6. The method for improving SRAM performance as claimed in claim 1, wherein the plurality of N-type threshold voltage regions comprise an N-type ultra-low threshold voltage region, an N-type standard threshold voltage region and an N-type high threshold voltage region, The N-type work function layer corresponding to the N-type high threshold voltage region is the first N-type work function layer. 7. The method for improving SRAM performance according to claim 6, wherein the process step of forming an N-type work function layer including the first N-type work function layer comprises: a gate dielectric in the N-type logic device region An N-type work function layer is formed on the surface of the layer; a first mask layer is formed on the surface of the N-type work function layer, and the first mask layer exposes the surface of the N-type work function layer in the N-type high threshold voltage region; The first mask layer is a mask, and the N-type work function layer of the first thickness located in the N-type high threshold voltage region is etched and removed, and the etched N-type work function layer in the N-type logic device region is the first N-type work function layer. Type work function layer. 8. The method of claim 7, wherein the N-type work function layer is further located on the surface of the gate dielectric layer in the transfer gate transistor region; and the first mask layer further exposes the transfer gate transistor The surface of the N-type work function layer in the N-type high threshold voltage region is etched to remove the first thickness of the N-type work function layer located in the N-type high threshold voltage region, and the first thickness of the surface of the gate dielectric layer in the transfer gate transistor region is also etched and removed. The N-type work function layer forms the transfer gate work function layer. 9 . The method for improving the performance of an SRAM according to claim 6 , further comprising the step of: performing an N-type threshold adjustment doping treatment on the N-type logic device region substrate. 10 . 10. The method according to claim 1, wherein in the N-type logic device region, the thickness of the N-type work function layers other than the first N-type work function layer is 45 μm Angstrom to 55 Angstroms. 11. The method of claim 1 or 10, wherein the transfer gate work function layer has a thickness of 25 angstroms to 35 angstroms. 12 . The method for improving SRAM performance according to claim 11 , wherein the doping ions used in the second threshold voltage adjustment doping treatment are B, and the doping concentration is 1E12 atoms/cm ³ to 1E14 atoms/cm ³ . 13. The method for improving SRAM performance according to claim 1, wherein the plurality of P-type threshold voltage regions comprise a P-type ultra-low threshold voltage region, a P-type standard threshold voltage region and a P-type high threshold voltage region, Wherein, the P-type work function layer corresponding to the P-type ultra-low threshold voltage region is the first P-type work function layer. 14. The method of claim 13, wherein the step of forming a P-type work function layer including the first P-type work function layer comprises: a gate dielectric in the P-type logic device region A P-type work function layer is formed on the surface of the layer; a second mask layer is formed on the surface of the P-type work function layer, and the second mask layer exposes the surface of the P-type work function layer in the P-type high threshold voltage region; The second mask layer is a mask, and the P-type work function layer of the second thickness located in the P-type high threshold voltage region is etched and removed, and the P-type work function layer that is not etched in the P-type logic device region is the first P-type work function layer. 15. The method of claim 14, wherein the P-type work function layer is further located on the surface of the gate dielectric layer in the pull-up transistor region, and the second mask layer also covers the pull-up transistor region On the surface of the P-type work function layer, the unetched P-type work function layer in the pull-up transistor region is the pull-up work function layer. 16. The method of claim 1, wherein, in the P-type logic device region, the thickness of the P-type work function layers other than the first P-type work function layer is 25 μm Angstrom to 35 Angstroms. 17. The method of claim 1 or 16, wherein the pull-up work function layer has a thickness of 45 angstroms to 55 angstroms. 18 . The method of claim 17 , wherein the doping ions for the first threshold voltage doping treatment are As, and the doping concentration is 1E12 atoms/cm ³ to 1E14 atoms/cm ³ . 19 . 19. The method of claim 1, wherein the gate dielectric layer comprises an interface layer and a high-k gate dielectric layer located on the surface of the interface layer. 20. The method of claim 1, wherein the base comprises a substrate and a fin on a surface of the substrate, wherein the gate dielectric layer spans across the fin and covers the fin part of the top and sidewall surfaces.

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