CN108122912B - SRAM device and manufacturing method thereof - Google Patents

Abstract

A SRAM device and its manufacturing method, the manufacturing method comprising: forming a gate dielectric layer on part of the substrate of the pull-up transistor region and the pull-down transistor region; forming a first work function layer on the gate dielectric layer; etching and removing the pull-down transistor The first work function layer in the region; the second work function layer is formed on the remaining first work function layer and the pull-down transistor region, and the material of the second work function layer is a P-type work function material; in the pull-up transistor region A diffusion barrier layer is formed on the sidewall of the remaining second work function layer and the sidewall of the remaining first work function layer; on the diffusion barrier layer, on the top of the second work function layer of the pull-up transistor region, and on the gate of the pull-down transistor region A third work function layer is formed on the dielectric layer, and the material of the third work function layer is an N-type work function material; a gate electrode layer is formed on the third work function layer. The invention improves the electrical parameter mismatch of the SRAM device and optimizes the electrical performance of the formed SRAM device.

Description

SRAM device and manufacturing method thereof

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to an SRAM device and a manufacturing method thereof.

Background technique

In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory and analog circuits, among which memory devices account for a considerable proportion of integrated circuit products. With the development of semiconductor technology, storage devices are more widely used, and the storage device and other device regions need to be formed on a chip at the same time to form an embedded semiconductor storage device. For example, to embed the storage device in the central processing unit, it is necessary to make the storage device compatible with the embedded central processing unit platform, and maintain the specifications and corresponding electrical performance of the original storage device.

Generally, the memory device needs to be compatible with embedded standard logic devices. For an embedded semiconductor device, it is usually divided into a logic area and a storage area, the logic area usually includes logic devices, and the storage area includes storage devices. With the development of storage technology, various types of semiconductor memories have appeared, such as Static Random Access Memory (SRAM, Static Random Access Memory), Dynamic Random Access Memory (DRAM, Dynamic Random Access Memory), Erasable Programmable Read-Only Memory ( EPROM, Erasable Programmable Read-Only Memory), Electrically Erasable Programmable Read-Only Memory (EEPROM, Electrically Erasable Programmable Read-Only) and flash memory (Flash). Since the SRAM has the advantages of low power consumption and fast working speed, more and more attention has been paid to the SRAM and its forming method.

However, the electrical performance of the SRAM device formed in the prior art needs to be improved.

Contents of the invention

The problem solved by the present invention is to provide a SRAM device and its manufacturing method, and improve the electrical performance of the formed SRAM device.

In order to solve the above problems, the present invention provides a method for manufacturing an SRAM device, comprising: providing a substrate, the substrate including adjacent pull-up transistor regions and pull-down transistor regions; A gate dielectric layer is formed on part of the substrate; a first work function layer is formed on the gate dielectric layer, and the material of the first work function layer is a P-type work function material; the first work function layer of the pull-down transistor region is removed by etching Function layer; form a second work function layer on the remaining first work function layer and the pull-down transistor region, the material of the second work function layer is a P-type work function material; etch to remove the second work function layer of the pull-down transistor region function layer; a diffusion barrier layer is formed on the remaining second work function layer sidewall and the remaining first work function layer sidewall of the pull-up transistor region; on the diffusion barrier layer, the second work function layer of the pull-up transistor region A third work function layer is formed on the top of the function layer and on the gate dielectric layer of the pull-down transistor region, and the material of the third work function layer is an N-type work function material; a gate electrode layer is formed on the third work function layer.

Optionally, a deposition process is used to form the diffusion barrier layer; in the process step of forming the diffusion barrier layer, the top of the second work function layer of the pull-up transistor region and the gate of the pull-down transistor region The diffusion barrier layer is formed on the dielectric layer; in the process step of forming the third work function layer, the formed third work function layer is located on the diffusion barrier layer of the pull-up transistor region and the pull-down transistor region.

Optionally, the diffusion barrier layer is formed by using an atomic layer deposition process.

Optionally, the thickness of the diffusion barrier layer is 5 angstroms to 20 angstroms.

Optionally, the material of the diffusion barrier layer is TaN or TaCN.

Optionally, after etching and removing the second work function layer of the pull-down transistor region, the remaining first work function layer and the remaining second work function layer The side walls are flush.

Optionally, the material of the first work function layer is one or more of Ta, TiN, TaN, TaSiN or TiSiN; the material of the second work function layer is Ta, TiN, TaN, TaSiN or TiSiN One or more of them; the material of the third work function layer is one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN.

Optionally, after forming the gate dielectric layer and before forming the first work function layer, the method further includes: forming a protection layer on the gate dielectric layer.

Optionally, the process step of forming the protection layer includes: forming a capping layer on the gate dielectric layer; forming an etch stop layer on the cap layer, and the material of the etch stop layer is the same as that of the first The materials of a work function layer are different.

Optionally, the substrate further includes a channel gate transistor region; in the process step of forming the gate dielectric layer and the protective layer, a gate dielectric layer and a gate dielectric layer located on a part of the substrate of the channel gate transistor region are also formed. In the process step of forming the first work function layer, a first work function layer is also formed on the channel gate transistor region; in the process step of forming the second work function layer, also The second work function layer is formed on the pass gate transistor region; in the process step of forming the third work function layer, the third work function layer is also formed on the pass gate transistor region.

Optionally, before forming the second work function layer, the first work function layer and the protective layer of the channel gate transistor region are removed by etching; in the process step of forming the second work function layer, in the A second work function layer is formed on the gate dielectric layer of the channel gate transistor region.

The present invention also provides an SRAM device, comprising: a substrate, the substrate including an adjacent pull-up transistor region and a pull-down transistor region; a gate dielectric layer located on part of the substrate of the pull-up transistor region and the pull-down transistor region; The first work function layer located on the gate dielectric layer of the pull-up transistor region and the second work function layer located on the first work function layer, the materials of the first work function layer and the second work function layer All are P-type work function materials; the diffusion barrier layer located on the sidewall of the second work function layer and the side wall of the first work function layer of the pull-up transistor region; the diffusion barrier layer located on the pull-up transistor region The third work function layer on the top of the second work function layer and on the gate dielectric layer of the pull-down transistor region, the material of the third work function layer is an N-type work function material; the gate located on the third work function layer electrode layer.

Optionally, the diffusion barrier layer is also located on top of the second work function layer in the pull-up transistor region and on the gate dielectric layer in the pull-down transistor region.

Optionally, the thickness of the diffusion barrier layer is 5 angstroms to 20 angstroms.

Optionally, the material of the diffusion barrier layer is TaN or TaCN.

Optionally, sidewalls of the first work function layer and the second work function layer are flush with each other where the pull-up transistor and the region of the pull-down transistor adjoin.

Optionally, the SRAM device further includes: a protective layer located between the gate dielectric layer of the pull-up transistor region and the first work function layer, and the protective layer is also located in the gate dielectric layer of the pull-down transistor region and the third work function layer.

Optionally, the substrate further includes a pass-gate transistor region; wherein, the gate dielectric layer is also located on part of the substrate of the pass-gate transistor region; and the second work function layer is also located in the pass-gate transistor region on the gate dielectric layer; the third work function layer is also located on the second work function layer of the channel gate transistor region.

Optionally, the base includes a substrate and discrete fins on the substrate.

Optionally, the pull-up transistor region has one fin; the pull-down transistor region has two fins.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the manufacturing method of the SRAM device provided by the present invention, after the first work function layer is formed on the gate dielectric layer of the pull-up transistor region and the pull-down transistor region, the first work function layer of the pull-down transistor region is etched and removed ; Then form a second work function layer on the remaining first work function layer and the pull-down transistor region, the materials of the first work function layer and the second work function layer are both P-type work function materials; then etch and remove the Pulling down the second work function layer of the transistor region; then forming a diffusion barrier layer on the sidewalls of the first work function layer and the second work function layer of the pull-up transistor region; on the diffusion barrier layer, the pull-up transistor region A third work function layer is formed on the top of the second work function layer and on the gate dielectric layer of the pull-down transistor region, and the material of the third work function layer is an N-type work function material; formed on the third work function layer gate electrode layer. In the present invention, while meeting the threshold voltage requirements of the pull-up transistor and the pull-down transistor, diffusion is formed on the side wall of the first work function layer and the side wall of the second work function layer at the junction of the pull-up transistor region and the pull-down transistor region. barrier layer, the diffusion barrier layer is beneficial to block the lateral diffusion between the first work function layer and the third work function layer at the junction, and is beneficial to block the second work function layer at the junction and the first work function layer The lateral diffusion between the three work function layers improves the electrical parameter mismatch between the formed pull-up transistor and the pull-down transistor, and improves the electrical performance of the formed SRAM device.

In an optional solution, the substrate further includes a pass-gate transistor region; before forming the second work-function layer, the first work function layer and the gate dielectric layer of the pass-gate transistor region are removed, so that the pass-gate transistor region corresponds to The thickness of the work function layer is relatively thin, so the threshold voltage of the channel gate transistor formed accordingly is relatively low, thereby increasing the operating speed of the channel gate transistor and further improving the electrical performance of the formed SRAM device.

In an optional solution, after the second work function layer of the pull-down transistor region is removed by etching, the remaining first work function layer and the remaining second work function layer are adjacent to the pull-up transistor region and the pull-down transistor region The sidewalls are flush, which provides good process conditions for forming a diffusion barrier layer at the junction, thereby improving the thickness uniformity of the formed diffusion barrier layer, and further improving the work function of the diffusion barrier layer against the junction The ability of layers to interdiffuse.

The present invention also provides an SRAM device with superior structural performance, the pull-up transistor region is adjacent to the pull-down transistor region, and since the first work function layer and the second work function layer are only located in the pull-up transistor region ; between the first work function layer and the second work function layer at the junction of the pull-up transistor region and the pull-down transistor region, and the third work function layer are blocked by the diffusion barrier layer, and the diffusion barrier layer is conducive to blocking all The mutual lateral diffusion between the first work function layer and the third work function layer at the junction is beneficial to block the mutual lateral diffusion between the second work function layer and the third work function layer at the junction, thereby The electrical performance of the SRAM device is improved, for example, the electrical parameter mismatch between the pull-up transistor and the pull-down transistor is improved. .

Description of drawings

Fig. 1 is a top view structural schematic diagram of a kind of SRAM device;

2 to 14 are schematic structural diagrams of the forming process of the SRAM device provided by the embodiment of the present invention.

Detailed ways

It can be seen from the background art that the electrical performance of the SRAM device formed in the prior art needs to be improved.

Now analyze in conjunction with a SRAM device, referring to Fig. 1, Fig. 1 is a schematic diagram of a top view structure of a SRAM device, the SRAM device includes a pull-up (PU, Pull Up) transistor, a pull-down (PD, Pull Down) transistor and a channel Gate (PG, Pass Gate) transistor, wherein the first region 101 is a region where a pull-up transistor is formed, the second region 102 is a region where a pull-down transistor is formed, and the third region 103 is a region where a pass gate transistor is formed, usually Yes, the pull-up transistor is a PMOS transistor, and the pull-down transistor and channel gate transistor are NMOS transistors.

Taking the SRAM device as a FinFET device as an example, the first region 101 is adjacent to the second region 102, and the first region 101, the second region 102 and the third region 103 all have fins 105, and the first region 101 has one fin 105, the second region 102 has two fins 105, and the second region 102 and the third region 103 have one fin 105 together; and the first region 101 and the second The two regions 102 share the same gate electrode layer 106 .

The pull-up transistor is a PMOS device, and the pull-down transistor is an NMOS device. In order to meet the requirements of improving the threshold voltage (Threshold Voltage) of PMOS devices and NMOS devices at the same time, different metal materials are usually used as the work function layer (WF, Work Function) material in the gate structure of NMOS devices and PMOS devices, and in NMOS devices The work function layer is called an N-type work function material, and the work function layer in a PMOS device is called a P-type work function material. When the NMOS device and the PMOS device share the same gate electrode layer, there will be an N/P boundary interface (N/P boundary Interface) between the N-type work function layer and the P-type work function layer at the junction of the NMOS device and the PMOS device. The above-mentioned work function materials at the N/P interface diffuse and affect each other, resulting in changes in the performance of the NMOS device and the PMOS device.

For SRAM devices, the work function layer at the junction of the pull-up transistor and the pull-down transistor is usually a stacked structure, and the work function layer at the junction has both an N-type work function layer and a P-type work function layer, so that The work function layer of the pull-up transistor and the work function layer of the pull-down transistor influence each other, for example, the work function layer of the pull-up transistor and the work function layer of the pull-down transistor interact with each other through lateral diffusion, thereby causing the pull-up of the SRAM device The electrical parameter mismatch (Mismatch) between the transistor and the pull-down transistor becomes worse, thereby affecting the electrical performance of the SRAM device.

Wherein, the lateral diffusion is mainly the diffusion of Al ions in the N-type work function material to the P-type work function material, thus affecting the equivalent work function values of the N-type work function layer and the P-type work function layer, further affecting The threshold voltages of the corresponding pull-up transistors and pull-down transistors.

If the type of the work function layer at the junction of the pull-up transistor and the pull-down transistor is relatively single, it can effectively reduce the mutual diffusion interaction between the work function layers at the junction of the pull-up transistor and the pull-down transistor, thereby improving the electrical properties of the SRAM device performance, and meet the requirements of read margin and write margin.

In order to solve the above problems, the present invention provides a method for manufacturing an SRAM device, comprising: providing a substrate, the substrate including adjacent pull-up transistor regions and pull-down transistor regions; A gate dielectric layer is formed on part of the substrate; a first work function layer is formed on the gate dielectric layer, and the material of the first work function layer is a P-type work function material; the first work function layer of the pull-down transistor region is removed by etching Function layer; form a second work function layer on the remaining first work function layer and the pull-down transistor region, the material of the second work function layer is a P-type work function material; etch to remove the second work function layer of the pull-down transistor region function layer; on the top of the second work function layer of the pull-up transistor region, on the remaining second work function layer sidewalls and the remaining first work function layer sidewalls of the pull-up transistor region, and on the pull-down transistor region A third work function layer is formed, and the material of the third work function layer is an N-type work function material; a gate electrode layer is formed on the third work function layer.

In the SRAM device formed by the present invention, the work function layer interface at the junction of the pull-up transistor and the pull-down transistor is single, reducing or avoiding the problem of mutual diffusion of the work function layers at the junction, thereby improving the pull-up transistor and the pull-down transistor. The electrical parameter mismatch optimizes the electrical performance of the formed SRAM device.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

2 to 14 are schematic structural diagrams of the forming process of the SRAM device provided by the embodiment of the present invention.

Referring to FIG. 2 and FIG. 3, FIG. 2 is a schematic diagram of a top view structure, and FIG. 3 is a schematic diagram of a cross-sectional structure along the direction AA1 in FIG. The part and the isolation structure are not shown, and a substrate is provided, and the substrate includes adjacent pull-up transistor regions I and pull-down transistor regions II.

The pull-up transistor area I provides a process platform for the subsequent formation of the pull-up transistor, and the pull-down transistor area II provides a process platform for the subsequent formation of the pull-down transistor.

In this embodiment, the pull-down transistor region II includes a first pull-down transistor region (not marked) and a second pull-down transistor region (not marked), wherein the first pull-down transistor region and the pull-up transistor region Adjacent; the first pull-down transistor region provides a process platform for the subsequent formation of the first pull-down transistor, the second pull-down transistor region provides a process platform for the subsequent formation of the second pull-down transistor, and the first pull-down transistor A pull-down transistor connected in parallel with the second pull-down transistor is formed.

In this embodiment, the substrate further includes a pass-gate transistor region III, and the pass-gate transistor region III provides a process platform for subsequent formation of a pass-gate transistor.

In this embodiment, the pull-up transistor region I is a PMOS region, the pull-down transistor region II is an NMOS region, and the channel gate transistor region III is an NMOS region.

Taking the formed SRAM device as a FinFET device as an example, the base includes: a substrate 201 and discrete fins 202 on the substrate 201 . In order to electrically isolate adjacent fins 202 and adjacent devices, the base further includes: an isolation structure 214 located on the substrate 201 exposed by the fins 202, the isolation structure 214 covers part of the sidewall of the fins 202, And the top of the isolation structure 214 is lower than the top of the fin 202 .

The material of the isolation structure 214 is silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation structure 214 is silicon oxide.

In another embodiment, the SRAM device is a planar transistor, the substrate is a planar substrate, and the planar substrate is a silicon substrate, a germanium substrate, a silicon germanium substrate or a silicon carbide substrate, or a silicon-on-insulator substrate Or a germanium-on-insulator substrate, a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), and the gate structure is formed on the surface of the planar substrate.

The material of the substrate 201 is silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate 201 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; The material of the fin portion 202 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. In this embodiment, the substrate 201 is a silicon substrate, and the material of the fins 202 is silicon.

In this embodiment, the pull-down transistor region II includes a first pull-down transistor region and a second pull-down transistor region; correspondingly, the pull-up transistor region I has a fin 202, and the pull-down transistor region II has two fins 202, wherein one fin 202 provides a process platform for forming the first pull-down transistor, and the other fin 202 provides a process platform for forming the second pull-down transistor; the channel gate transistor region III has a fin 202, and The pass-gate transistor region III shares a fin 202 with the pull-down transistor region II.

It should also be noted that, in other embodiments, the number of fins in the pull-up transistor region, the number of fins in the pull-down transistor region, and channel The number of fins in the gate transistor region.

Referring to FIG. 4 , in this embodiment, the gate structure of the SRAM device is formed by adopting a process of forming a high-k gate dielectric layer and then forming a gate electrode layer (high klast metal gate last). Therefore, the forming method further includes: forming a dummy gate structure 210 on the substrates of the pull-up transistor region I and the pull-down transistor region II.

The dummy gate structure 210 occupies a spatial position for a gate structure of an SRAM device to be subsequently formed. Specifically, a dummy gate structure 210 spanning the fin 202 is formed on the isolation structure 214 , and the dummy gate structure 210 covers part of the top surface and part of the sidewall surface of the fin 202 .

The dummy gate structure 210 is a single layer structure or a stacked layer structure. The dummy gate structure 210 includes a dummy gate layer; or the dummy gate structure 210 includes a dummy oxide layer and a dummy gate layer on the dummy oxide layer. Wherein, the material of the dummy gate layer is polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride or amorphous carbon, and the material of the dummy oxide layer is silicon oxide or silicon oxynitride.

In this embodiment, in the process step of forming the dummy gate structure 210 on the pull-up transistor region I and the pull-down transistor region II, the dummy gate structure 210 is also formed on the pass-gate transistor region II.

In this embodiment, since the pull-up transistor region I is adjacent to the pull-down transistor region II, the dummy gate structure 210 is made to straddle the pull-up transistor region I and the pull-down transistor region II, correspondingly, The subsequently formed gate electrode layer spans the pull-up transistor region I and the pull-down transistor region II.

After forming the dummy gate structure 210 , the manufacturing method further includes: forming source and drain doped regions of each transistor in the fins 202 on both sides of the dummy gate structure 210 in each region.

After the source-drain doped region is formed, the dummy gate structure 210 is removed. In this embodiment, the dummy gate structure 210 may be removed by using a dry etching process, a wet etching process or a SiCoNi etching system.

It should be noted that, before removing the dummy gate structure 210, the manufacturing method further includes: forming an interlayer dielectric layer (not shown in the figure) on the substrate exposed by the dummy gate structure 210, the interlayer dielectric layer exposing the top of the dummy gate structure 210 .

Referring to FIG. 5 , after removing the dummy gate structure 210 , a gate dielectric layer 204 is formed on part of the bases of the pull-up transistor region I and the pull-down transistor region II.

The substrate also includes a pass-gate transistor region III, so in the process step of forming the gate dielectric layer 204 , the gate dielectric layer 204 is also formed on part of the substrate of the pass-gate transistor region III.

In this embodiment, the gate dielectric layer 204 includes an interfacial layer (IL, Interfacial Layer) (not marked) and a high-k gate dielectric layer (not marked) located on the surface of the interface layer. Specifically, in the step of forming the gate dielectric layer 204 , the gate dielectric layer 204 spans the fin portion 202 and covers part of the top surface and the sidewall surface of the fin portion 202 .

The interface layer provides a good interface basis for forming the high-k gate dielectric layer, thereby improving the quality of the high-k gate dielectric layer and reducing the interface state density between the high-k gate dielectric layer and the fin 202 , and avoid adverse effects caused by direct contact between the high-k gate dielectric layer and the fin portion 202 . The material of the interface layer is silicon oxide or silicon oxynitride.

In this embodiment, the interface layer is formed by an oxidation process, and the formed interface layer is only formed on the exposed top surface and sidewall surface of the fin 202 . In other embodiments, the interface layer may also be formed by a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process, and the formed interface layer is also located on the isolation structure.

The material of the high-k gate dielectric layer is a gate dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO ₂ . In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO ₂ or Al ₂ O ₃ . The high-k gate dielectric layer can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In this embodiment, the high-k gate dielectric layer is formed by an atomic layer deposition process.

Subsequent steps include forming a work function layer on the gate dielectric layer 204 . In order to protect the gate dielectric layer 204 in subsequent process steps, before forming the first work function layer, it further includes: forming a protection layer on the gate dielectric layer 204 .

Referring to FIG. 6, the process steps of forming the protective layer include: forming a cap layer 205 on the gate dielectric layer 204; forming an etch stop layer 206 on the cap layer 205, and the etch stop layer 206 The material is different from that of the subsequently formed first work function layer.

In this embodiment, in the process step of forming the protective layer, the protective layer is further formed on the gate dielectric layer 204 of the channel gate transistor region III.

The capping layer 205 can protect the gate dielectric layer 204 and prevent unnecessary etching losses to the gate dielectric layer 204 caused by subsequent etching processes. The capping layer 205 is also beneficial to block subsequent The easily diffusible metal ions formed in the gate electrode layer diffuse into the gate dielectric layer 204 .

In this embodiment, the material of the capping layer 205 is TiN, and the capping layer is formed by an atomic layer deposition process, so that the capping layer 205 has good step coverage.

The material of the etching stop layer 206 is different from that of the subsequently formed work function layer, so that the etching rate of the etching stop layer 206 in the subsequent etching process for etching the work function layer is relatively small, so the The etch stop layer 206 functions as an etch stop in the subsequent etching process of etching the work function layer, and can avoid etching damage to the gate dielectric layer 204 .

In this embodiment, the material of the etching stop layer is TaN, and the etching stop layer is formed by an atomic layer deposition process, so that the etching stop layer has good step coverage.

Referring to FIG. 7 , a first work function layer 207 is formed on the gate dielectric layer 204 , and the material of the first work function layer 207 is a P-type work function material.

In the process step of forming the first work function layer 207, the first work function layer 207 is also formed on the pass-gate transistor region III. In this embodiment, since a protective layer is formed on the gate dielectric layer 204, the first work function layer 207 is formed on the protective layer; specifically, the etching stop layer 206 is formed on the The first work function layer 207 .

The first work function layer 207 is a part of the work function layer corresponding to the pull-up transistor region I.

The work function range of the P-type work function material is 5.1eV to 5.5eV, for example, 5.2eV, 5.3eV or 5.4eV. The material of the first work function layer 207 is one or more of Ta, TiN, TaN, TaSiN or TiSiN, and the first work function layer can be formed by chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process. Function layer 207 .

In this embodiment, the material of the first work function layer 207 is TiN, and the thickness of the first work function layer 207 is 10 angstroms to 30 angstroms.

Referring to FIG. 8 , the first work function layer 207 of the pull-down transistor region II is removed by etching.

In this embodiment, in order to meet the threshold voltage requirement of the pull-down transistor, the first work function layer 207 in the pull-down transistor region II needs to be etched and removed, and the first work function layer 207 in the pull-up transistor region I is retained as Part of the work function layer of the pull-up transistor.

Specifically, the process step of etching and removing the first work function layer 207 of the pull-down transistor region II includes: forming a first pattern layer on the first work function layer 207 of the pull-up transistor region I and the channel gate transistor region , the first pattern layer exposes the first work function layer 207 of the pull-down transistor region II; using the first pattern layer as a mask, etching and removing the first work function layer 207 of the pull-down transistor region II; The first graphics layer is removed.

During the process of etching and removing the first work function layer 207 of the pull-down transistor region II, the etch stop layer 206 located in the pull-down transistor region II plays the role of an etching stop, avoiding damage to the pull-down transistor region II. The gate dielectric layer 204 causes etching damage.

Referring to FIG. 9 , the first work function layer 207 and the protection layer of the channel gate transistor region III are removed by etching.

In this embodiment, the first work function layer 207 and the protection layer of the pass-gate transistor region III are also etched away to expose the gate dielectric layer 204 of the pass-gate transistor region III. Its benefits include:

Since the first work function layer 207 and the protective layer of the channel gate transistor region III are etched and removed, the thickness of the work function layer correspondingly formed in the channel gate transistor region III subsequently is relatively thin; the channel gate transistor region III is In the NMOS region, for the channel gate transistor, the thinner the work function layer, the lower the threshold voltage, which is beneficial to improve the operating speed of the subsequently formed channel gate transistor.

Specifically, the process steps of etching and removing the first work function layer 207 and the protective layer of the channel gate crystal region III include: on the first work function layer 207 of the pull-up transistor region I and on the pull-down transistor region II A second pattern layer is formed on the protective layer, and the second pattern layer exposes the first work function layer 207 of the channel gate transistor region III; using the second pattern layer as a mask, etching removes the channel The first work function layer 207, the etching stop layer 206 and the capping layer 205 of the gate transistor region III until the gate dielectric layer 204 of the channel gate transistor region III is exposed; the second pattern layer is removed.

It should be noted that, in this embodiment, the first work function layer 207 of the pull-down transistor region II is etched and removed first, and then the first work function layer 207 and the protection layer of the channel gate transistor region III are etched and removed. In other embodiments, the first work function layer and the protective layer of the channel gate transistor region may be removed by etching first, and then the first work function layer of the pull-down transistor region may be removed by etching; or, the first work function layer of the pull-down transistor region may be removed by etching first. The pull-down transistor region and the first work function layer of the channel gate transistor region are etched to remove the protection layer of the channel gate transistor region.

Referring to FIG. 10 , a second work function layer 208 is formed on the remaining first work function layer 207 and the pull-down transistor region II, and the material of the second work function layer 208 is a P-type work function material.

In this embodiment, in the process step of forming the second work function layer 207 , the second work function layer 208 is formed on the protection layer of the pull-down transistor region II.

And in the process step of forming the second work function layer 208 , the second work function layer 208 is also formed on the pass-gate transistor region III. Specifically, in the process step of forming the second work function layer 208 , the second work function layer 208 is formed on the gate dielectric layer 204 of the channel gate transistor region III.

Specifically, the second work function layer 208 located in the pull-up transistor region I and the first work function layer 207 together constitute the work function layer of the subsequently formed pull-up transistor; the second work function layer located in the channel gate transistor region III The function layer 208 serves as a part of the work function layer of the subsequently formed pass-gate transistor.

The material of the second work function layer 208 is one or more of Ta, TiN, TaN, TaSiN or TiSiN.

In this embodiment, the material of the second work function layer 208 is different from that of the etching stop layer 207, the material of the second work function layer 208 is TiN, and the thickness of the second work function layer 208 is 5 angstroms to 30 angstroms.

Referring to FIG. 11 , the second work function layer 208 of the pull-down transistor region II is removed by etching.

In order to meet the threshold voltage requirement of the pull-down transistor subsequently formed in the pull-down transistor region II, the second work function layer 208 of the pull-down transistor region II needs to be etched away.

Specifically, the process step of etching and removing the second work function layer 208 of the pull-down transistor region II includes: forming a third pattern layer on the second work function layer 208, and the third pattern layer exposes the Pulling down the second work function layer 208 of the transistor region II; using the third pattern layer as a mask, etching and removing the second work function layer 208 of the pull-down transistor region II until the surface of the protective layer is exposed; removing the Describe the third graphics layer.

During the process of etching and removing the second work function layer 208 of the pull-down transistor region II, the etch stop layer 206 of the pull-down transistor region II acts as an etching stopper, avoiding damage to the gate of the pull-down transistor region II. Dielectric layer 204 causes etch damage.

In this embodiment, after the second work function layer 208 in the pull-down transistor region II is removed by etching, the remaining first work function layer 207 and the remaining second work function layer 208 are formed in the pull-up transistor region I and the pull-down transistor region. Zone II has flush sidewalls adjacent to it.

Referring to FIG. 12 , a diffusion barrier layer 212 is formed on the remaining sidewalls of the second work function layer 208 and the remaining sidewalls of the first work function layer 207 in the pull-up transistor region I.

The function of the diffusion barrier layer 212 includes: a third work function layer will be formed subsequently on the pull-up transistor region I and the pull-down transistor region II, and the material of the third work function layer is an N-type work function material; The diffusion barrier layer 212 is beneficial to block the mutual lateral diffusion between the work function layers at the junction of the pull-up transistor region I and the pull-down transistor region II, for example, blocking the first work function layer 207 and the second work function layer at the junction. The mutual lateral diffusion between the materials of the three work function layers blocks the mutual lateral diffusion between the materials of the second work function layer 208 and the third work function layer at the junction, thereby improving the subsequent formation of the pull-up transistor and the pull-down transistor. Electrical parameter mismatch between transistors.

In this embodiment, in order to reduce the process difficulty of forming the diffusion barrier layer 212, the diffusion barrier layer 212 is formed by a deposition process; in the process steps of forming the diffusion barrier layer 212, the pull-up transistor region The diffusion barrier layer 212 is formed on the top of the second work function layer 208 of I and the gate dielectric layer 204 of the pull-down transistor region II.

Specifically, in this embodiment, since a protective layer is also formed on the gate dielectric layer 204 of the pull-down transistor region II, in the process step of forming the diffusion barrier layer 212 on the gate dielectric layer 204 of the pull-down transistor region II , forming the diffusion barrier layer 212 on the protection layer of the pull-down transistor region II.

The substrate also includes a channel gate transistor region III, for which, in the process step of forming the diffusion barrier layer 212, the diffusion barrier layer is also formed on the second work function layer 208 of the channel gate transistor region III 212.

In this embodiment, the material of the diffusion barrier layer 212 is TaN. In other embodiments, the material of the diffusion barrier layer 212 may also be TaCN.

The thickness of the diffusion barrier layer 212 should neither be too thin nor too thick. If the thickness of the diffusion barrier layer 212 is too thin, the ability of the diffusion barrier layer 212 to block the mutual lateral diffusion between the work function layers at the subsequent junction is too weak; if the thickness of the diffusion barrier layer 212 is too thick, then The diffusion barrier layer 212 will adversely affect the threshold voltage of the pull-up transistor or the threshold voltage of the pull-down transistor formed subsequently.

Therefore, in this embodiment, the thickness of the diffusion barrier layer 212 is 5 angstroms to 20 angstroms.

In this embodiment, the diffusion barrier layer 212 is formed by atomic layer deposition process, which is beneficial to improve the step coverage capability of the diffusion barrier layer 212 and improve the thickness uniformity of the formed diffusion barrier layer 212 . It should be noted that, in other embodiments, the diffusion barrier layer may also be formed by chemical vapor deposition or physical vapor deposition process.

In addition, since the sidewalls of the remaining first work function layer 207 and the remaining second work function layer 208 are flush at the adjoining positions of the pull-up transistor region I and the pull-down transistor region II, the first work function layer The diffusion barrier layer 212 formed on the sidewall of 207 and the sidewall of the second work function layer 208 has good morphology and good thickness uniformity, thereby further improving the ability of the diffusion barrier layer 212 to block mutual lateral diffusion between work function layers .

Referring to FIG. 13, a third work function layer 209 is formed on the diffusion barrier layer 212, on the top of the second work function layer 208 in the pull-up transistor region I, and on the gate dielectric layer 204 in the pull-down transistor region II. The material of the work function layer 209 is an N-type work function material.

In this embodiment, in the process step of forming the third work function layer 209, the formed third work function layer 209 is located on the diffusion barrier layer 212 of the pull-up transistor region I and the pull-down transistor region II; And the formed third work function layer 209 is also located on the diffusion barrier layer 212 of the channel gate transistor region III.

The third work function layer 209 located in the pull-down transistor region II is used as the work function layer corresponding to the pull-down transistor region II for adjusting the threshold voltage of the pull-down transistor formed subsequently; the third work function layer 209 located in the channel gate transistor region III The layer 209 and the second work function layer 208 serve as the work function layer corresponding to the channel gate transistor region III, and are used to adjust the threshold voltage of the subsequently formed channel gate transistor.

The first work function layer 207 and the second work function layer 208 located in the pull-up transistor region I serve as work function layers corresponding to the pull-up transistor region I, and are used to adjust the threshold voltage of the subsequently formed pull-up transistor.

It should be noted that, in order to reduce process steps and save photomasks, in this embodiment, after the third work function layer 209 is formed, the third work function layer 209 located in the pull-up transistor region I remains. It should also be noted that, in other embodiments, after forming the third work function layer, the third work function layer in the pull-up transistor region may be removed by etching.

The third work function layer 209 is an N-type work function material, and the work function of the N-type work function material ranges from 3.9eV to 4.5eV, such as 4eV, 4.1eV or 4.3eV. The material of the third work function layer 209 is one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN, and the third work function layer 209 can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Three work function layers 209 . In this embodiment, the material of the third work function layer 209 is TiAl.

The thickness of the third work function layer 209 is determined according to the threshold voltages of the pull-up transistor and the pass-gate transistor. In this embodiment, the thickness of the third work function layer 209 is 20 angstroms to 70 angstroms.

Referring to FIG. 14 , a gate electrode layer 211 is formed on the third work function layer 209 .

In this embodiment, the gate electrode layer 211 is formed on the third work function layer 209 of the pull-up transistor region I, the pull-down transistor region II and the pass-gate transistor region III. Wherein, the gate electrode layer 211 of the pull-up transistor region I and the pull-down transistor region II straddles the pull-up transistor region I and the pull-down transistor region II, and it can also be considered that the pull-up transistor region I and the pull-down transistor region II share the same gate electrode layer 211.

In this embodiment, the material of the gate electrode layer 211 includes one or more of Al, Cu, Ag, Au, Pt, Ni, Ti or W.

Specifically, the process step of forming the gate electrode layer 211 includes: forming a gate electrode film on the third work function layer 209, the top of the gate electrode film is higher than the top of the interlayer dielectric layer (not shown) ; Grinding and removing the gate electrode film above the top of the interlayer dielectric layer to form the gate electrode layer 211 .

In the technical solution for the formation method of the SRAM device provided by the embodiment of the present invention, the pull-up transistor region I is adjacent to the pull-down transistor region II, and since the first work function layer 207 and the second work function layer 208 are only located The pull-up transistor region I; the first work function layer 207, the second work function layer 208, and the third work function layer 209 at the junction of the pull-up transistor region I and the pull-down transistor region II are blocked by the diffusion layer 212, the diffusion barrier layer 212 is conducive to blocking the mutual lateral diffusion between the first work function layer 207 and the third work function layer 209 at the junction, and is conducive to blocking the second work function layer 209 at the junction The mutual lateral diffusion between the layer 208 and the third work function layer 209 improves the electrical performance of the formed SRAM device, for example, improves the electrical parameter mismatch between the pull-up transistor and the pull-down transistor.

Specifically, the diffusion barrier layer 212 is conducive to blocking the lateral diffusion of Al ions in the third work function layer 209 at the junction to the first work function layer 207, and is also conducive to blocking the third work function layer 209 at the junction. Al ions in layer 209 diffuse laterally toward second work function layer 208 . Ensure that the equivalent work function value of the work function layer of the pull-up transistor region I remains unchanged, and the equivalent work function value of the work function layer of the pull-down transistor region II remains unchanged, thereby avoiding the pull-up transistor and the pull-down The threshold voltage of the transistor has adverse effects, and the electrical parameter mismatch between the pull-up transistor and the pull-down transistor is improved.

In this embodiment, the sidewalls of the first work function layer 207 and the sidewalls of the second work function layer 208 at the adjacent portion of the pull-up transistor region I and the pull-down transistor region II are flush with each other, which is beneficial to improve the junction area. The uniformity of the thickness of the diffusion barrier layer 212, thereby further improving the ability of the diffusion barrier layer 212 to block diffusion, and further improving the electrical performance of the formed SRAM device.

In addition, in this embodiment, the formed SRAM device also meets the requirements of read redundancy and write redundancy.

Correspondingly, the present invention also provides an SRAM device. Referring to FIG. 14, the SRAM device includes:

a substrate, the substrate comprising adjacent pull-up transistor regions I and pull-down transistor regions II;

A gate dielectric layer 204 located on part of the base of the pull-up transistor region I and the pull-down transistor region II;

The first work function layer 207 located on the gate dielectric layer 204 of the pull-up transistor region I and the second work function layer 208 located on the first work function layer 207, the first work function layer 207 and the second work function layer 208 The materials of the second work function layer 208 are P-type work function materials;

The diffusion barrier layer 212 located on the sidewall of the second work function layer 208 and the side wall of the first work function layer 207 of the pull-up transistor region I;

The third work function layer 209 located on the diffusion barrier layer 212, on the top of the second work function layer 208 of the pull-up transistor region I and on the gate dielectric layer 204 of the pull-down transistor region II, the third work function layer 209 The material is an N-type work function material;

The gate electrode layer 211 is located on the third work function layer 209 .

The SRAM device provided by the embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

In this embodiment, the pull-down transistor region II includes a first pull-down transistor region and a second pull-down transistor region, and the first pull-down transistor region is adjacent to the pull-up transistor region, and the first pull-down transistor region is adjacent to the pull-up transistor region. The pull-down transistor region has a first pull-down transistor, and the second pull-down transistor region has a second pull-down transistor.

The substrate also includes a channel gate transistor region III, and the gate dielectric layer 204 is also located on the substrate of the channel gate transistor region III; wherein, the second work function layer 208 is also located in the channel gate transistor region III on the gate dielectric layer 204; the diffusion barrier layer 212 is also located on the second work function layer 208 of the channel gate transistor region III; the third work function layer 209 is also located on the diffusion of the channel gate transistor region III on the barrier layer 212.

Taking the SRAM device as an example of a fin field effect transistor, the base includes a substrate 201 and a fin 202 located on the substrate 201, and the base also includes a substrate exposed from the fin 202 The isolation structure 214 on 201 , the isolation structure 214 covers part of the sidewall of the fin 202 , and the top of the isolation structure 214 is lower than the top of the fin 202 .

In this embodiment, the pull-up transistor region I has one fin 202; the pull-down transistor region II has two fins 202, wherein one fin 202 provides a process platform for the first pull-down transistor region, Another fin 202 provides a process platform for the second pull-down transistor region; the pass-gate transistor region III has one fin 202 .

For detailed descriptions of the substrate and the gate dielectric layer 204 , please refer to the corresponding descriptions of the foregoing embodiments, which will not be repeated here.

The material of the first work function layer 207 is one or more of Ta, TiN, TaN, TaSiN or TiSiN; the material of the second work function layer 208 is Ta, TiN, TaN, TaSiN or TiSiN. One or more; the material of the third work function layer 209 is one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN.

In this embodiment, the material of the first work function layer 207 is TiN, the material of the second work function layer 208 is TiN; the material of the third work function layer 209 is TiAl.

In this embodiment, the thickness of the first work function layer 207 is 10 angstroms to 30 angstroms; the thickness of the second work function layer 208 is 5 angstroms to 30 angstroms; the thickness of the third work function layer 209 is 20 angstroms to 70 angstroms.

The SRAM device further includes: a protection layer located between the gate dielectric layer 204 of the pull-up transistor region I and the first work function layer 207, and the protection layer is also located at the gate of the pull-down transistor region II. between the dielectric layer 204 and the third work function layer 209 .

The protective layer serves to protect the gate dielectric layer 204 . In this embodiment, the protection layer includes: a capping layer 205 on the gate dielectric layer 204 and an etching stop layer 206 on the capping layer 205 . Wherein, the material of the capping layer 205 is TiN, and the material of the etching stop layer 206 is TaN.

The diffusion barrier layer 212 is also located on top of the second work function layer 208 in the pull-up transistor region I and on the gate dielectric layer 204 in the pull-down transistor region II. Since there is a protection layer on the gate dielectric layer 204 of the pull-down transistor region II, the diffusion barrier layer 212 of the pull-down transistor region II is located on the protection layer of the pull-down transistor region II.

In this embodiment, the material of the diffusion barrier layer 212 is TiaN. In other embodiments, the material of the diffusion barrier layer may also be TaCN.

In this embodiment, the thickness of the diffusion barrier layer 212 is 5 Ř20 Å. Regarding the selection principle of the thickness of the diffusion barrier layer 212 , reference may be made to the corresponding descriptions of the above-mentioned embodiments, which will not be repeated here.

In the SRAM device provided by the present invention, the pull-up transistor region I is adjacent to the pull-down transistor region II, and since the first work function layer 207 and the second work function layer 208 are only located in the pull-up transistor region I ; between the first work function layer 207 and the second work function layer 208 at the junction of the pull-up transistor region I and the pull-down transistor region II, and the third work function layer 209 are blocked by the diffusion barrier layer 212, and the diffusion The barrier layer 212 is beneficial to block the mutual lateral diffusion between the first work function layer 207 and the third work function layer 209 at the junction, and is beneficial to block the second work function layer 208 and the third work function layer 208 at the junction. The mutual lateral diffusion between the work function layers 209 improves the electrical performance of the SRAM device, for example, improves the electrical parameter mismatch between the pull-up transistor and the pull-down transistor.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. a kind of manufacturing method of SRAM device characterized by comprising

Substrate is provided, the substrate includes adjacent pull up transistor area and pull-down transistor area；

Gate dielectric layer is formed on the part of substrate in pull up transistor area and the pull-down transistor area；

The first work-function layer is formed on the gate dielectric layer, the material of first work-function layer is p-type work function material；

Etching removes first work-function layer in the pull-down transistor area；

The second work-function layer, the material of second work-function layer are formed in remaining first work-function layer and pull-down transistor area Material is p-type work function material；

Etching removes second work-function layer in the pull-down transistor area；

It is formed and is expanded on residue the second work-function layer side wall and remaining first work-function layer side wall in the area that pulls up transistor Dissipate barrier layer；

Upper and pull-down transistor area grid are situated between on the diffusion barrier layer, at the top of second work-function layer in the area that pulls up transistor Third work-function layer is formed on matter layer, the material of the third work-function layer is N-type work function material；

Gate electrode layer is formed in the third work-function layer.

2. the manufacturing method of SRAM device as described in claim 1, which is characterized in that form the diffusion using depositing operation Barrier layer；

In the processing step for forming the diffusion barrier layer, also at the top of second work-function layer in the area that pulls up transistor on And the diffusion barrier layer is formed on the gate dielectric layer in the pull-down transistor area；

In the processing step for forming the third work-function layer, the third work-function layer of formation is located at the upper crystal pulling On the diffusion barrier layer in area under control and pull-down transistor area.

3. the manufacturing method of SRAM device as claimed in claim 1 or 2, which is characterized in that use atom layer deposition process shape At the diffusion barrier layer.

4. the manufacturing method of SRAM device as claimed in claim 2, which is characterized in that the diffusion barrier layer with a thickness of 5 Angstrom~20 angstroms.

5. the manufacturing method of SRAM device as described in claim 1, which is characterized in that the material of the diffusion barrier layer is TaN or TaCN.

6. the manufacturing method of SRAM device as described in claim 1, which is characterized in that remove the pull-down transistor in etching After second work-function layer in area, remaining first work-function layer and remaining second work-function layer are in the area that pulls up transistor under The side wall at the adjacent place in crystal pulling area under control flushes.

7. the manufacturing method of SRAM device as described in claim 1, which is characterized in that the material of first work-function layer is One or more of Ta, TiN, TaN, TaSiN or TiSiN；The material of second work-function layer be Ta, TiN, TaN, One or more of TaSiN or TiSiN；The material of the third work-function layer be TiAl, TiAlC, TaAlN, TiAlN, One or more of TaCN and AlN.

8. the manufacturing method of SRAM device as described in claim 1, which is characterized in that after forming the gate dielectric layer, It is formed before first work-function layer, further includes: form protective layer on the gate dielectric layer.

9. the manufacturing method of SRAM device as claimed in claim 8, which is characterized in that form the processing step of the protective layer It include: to form cap on the gate dielectric layer；Etching stop layer, and the etching stop layer are formed in the cap Material it is different from the material of first work-function layer.

10. the manufacturing method of SRAM device as claimed in claim 8, which is characterized in that the substrate further includes that channel grid are brilliant Body area under control；

Part of substrate in the processing step for forming the gate dielectric layer and protective layer, also in channel gate transistor area Upper formation gate dielectric layer and the protective layer on gate dielectric layer；

In the processing step for forming first work-function layer, the first work function also is formed in channel gate transistor area Layer；

In the processing step for forming second work-function layer, second function is also formed in channel gate transistor area Function layer；

In the processing step for forming the third work-function layer, the third function is also formed in channel gate transistor area Function layer.

11. the manufacturing method of SRAM device as claimed in claim 10, which is characterized in that forming second work-function layer Before, first work-function layer and protective layer in etching removal channel gate transistor area；Forming second work function In the processing step of layer, the second work-function layer is formed on the gate dielectric layer in channel gate transistor area.

12. a kind of SRAM device characterized by comprising

Substrate, the substrate include adjacent pull up transistor area and pull-down transistor area；

Gate dielectric layer on the part of substrate in pull up transistor area and the pull-down transistor area；

The first work-function layer on the gate dielectric layer for pulling up transistor area and it is located in first work-function layer The second work-function layer, the material of first work-function layer and the second work-function layer is p-type work function material；

Diffusion barrier layer on the second work-function layer side wall and the first work-function layer side wall in the area that pulls up transistor；

On the diffusion barrier layer, second work-function layer in the area that pulls up transistor top is gone up and the grid in pull-down transistor area Third work-function layer on dielectric layer, the material of the third work-function layer are N-type work function material；

Gate electrode layer in the third work-function layer.

13. SRAM device as claimed in claim 12, which is characterized in that the diffusion barrier layer is also located at the upper crystal pulling At the top of second work-function layer in area under control on the upper and gate dielectric layer in pull-down transistor area.

14. SRAM device as claimed in claim 13, which is characterized in that the diffusion barrier layer with a thickness of 5 angstroms~20 angstroms.

15. SRAM device as claimed in claim 12, which is characterized in that the material of the diffusion barrier layer be TaN or TaCN。

16. SRAM device as claimed in claim 12, which is characterized in that first work-function layer and the second work-function layer It is flushed in described pull up transistor with the side wall at adjacent place, pull-down transistor area, area.

17. SRAM device as claimed in claim 12, which is characterized in that the SRAM device further include: be located at the pull-up Protective layer between the gate dielectric layer of transistor area and the first work-function layer, and the protective layer is also located at the pull-down transistor Between the gate dielectric layer in area and the third work-function layer.

18. SRAM device as claimed in claim 12, which is characterized in that the substrate further includes channel gate transistor area；Its In, the gate dielectric layer is also located on the part of substrate in channel gate transistor area；And second work-function layer is also located at On the gate dielectric layer in channel gate transistor area；The third work-function layer is also located at the second of channel gate transistor area In work-function layer.

19. SRAM device as claimed in claim 12, which is characterized in that the substrate include substrate and be located at the substrate On discrete fin.

20. SRAM device as claimed in claim 19, which is characterized in that the area that pulls up transistor is with a fin；Institute Stating pull-down transistor area tool, there are two fins.