CN108573910A - Semiconductor structures and methods of forming them - Google Patents

Abstract

A kind of semiconductor structure and forming method thereof, forming method includes：Form substrate；Gate structure is formed on the substrate；It is formed and is located at the intrabasement source and drain doping area in the gate structure both sides；Dielectric layer is formed in the substrate that the gate structure exposes, the dielectric layer covers the source and drain doping area；The contact hole through the dielectric layer is formed, the source and drain doping area is exposed in the contact hole bottom；Metal oxide layer is formed in the source and drain doping area that the contact hole exposes；Plug is formed in the contact hole for being formed with metal oxide layer.Technical solution of the present invention can effectively inhibit the phenomenon that plug and source and drain doping area interface fermi level pinning, to advantageously reduce the contact resistance between the plug and the source and drain doping area, be conducive to the performance for improving formed semiconductor structure.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.

Background technique

In the integrated circuit manufacturing process, after the semiconductor device structure is formed, it is necessary to connect the semiconductor devices together to form a circuit. With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the critical dimensions of components are getting smaller and the circuit density inside integrated circuits is increasing. This development makes it impossible for the surface of the wafer to provide enough area to make the interconnection lines required by conventional circuits. .

In order to meet the requirements of the interconnection line after the critical dimension is reduced, at present, the conduction between different metal layers or the metal layer and the semiconductor device structure is realized through the interconnection structure. The interconnection structure includes interconnection wires and plugs located in contact holes, the plugs in the contact holes are used to connect semiconductor devices, and the interconnection wires connect plugs on different semiconductor devices to form a circuit.

As the process node of integrated circuits continues to shrink, the device size decreases and the contact area of the plug becomes smaller and smaller, and the contact resistance between the plug and the semiconductor device increases accordingly, which affects the electrical performance of the formed semiconductor structure.

Contents of the invention

The problem to be solved by the present invention is to provide a semiconductor structure and its forming method so as to reduce the contact resistance.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:

forming a base; forming a gate structure on the base; forming source-drain doped regions in the bases on both sides of the gate structure; forming a dielectric layer on the base exposed by the gate structure, and the dielectric layer covers The source-drain doped region; forming a contact hole through the dielectric layer, the bottom of the contact hole exposing the source-drain doped region; forming a metal oxide layer on the source-drain doped region exposed by the contact hole; Plugs are formed in the contact holes where the metal oxide layer is formed.

Optionally, in the step of forming a metal oxide layer on the source-drain doped region exposed by the contact hole, the material of the metal oxide layer is titanium oxide, cobalt oxide or nickel oxide.

Optionally, in the step of forming a metal oxide layer on the source-drain doped region exposed by the contact hole, the thickness of the metal oxide layer is less than or equal to 5 nm.

Optionally, the step of forming a metal oxide layer on the source-drain doped region exposed by the contact hole includes: forming a metal precursor layer on the source-drain doped region exposed by the contact hole; oxidation treatment to form the oxide metal layer.

Optionally, the material of the metal oxide layer is titanium oxide, and in the step of forming a metal precursor layer on the source-drain doped region exposed by the contact hole, the material of the metal precursor layer is titanium; the metal oxide layer The material of the layer is cobalt oxide, and in the step of forming a metal precursor layer on the source-drain doped region exposed by the contact hole, the material of the metal precursor layer is cobalt; the material of the metal oxide layer is nickel oxide, and the material of the metal oxide layer is nickel oxide. In the step of forming a metal precursor layer on the source-drain doped region exposed by the contact hole, the material of the metal precursor layer is nickel.

Optionally, in the step of forming a metal precursor layer on the source-drain doped region exposed by the contact hole, the thickness of the metal precursor layer is arrive within range.

Optionally, the step of oxidizing the metal precursor layer includes: forming a sacrificial layer on the metal precursor layer; performing oxidation annealing on the metal precursor layer formed with the sacrificial layer, so that the metal precursor layer is oxidized to form The oxidized metal layer; after performing oxidation and annealing on the metal precursor layer formed with the sacrificial layer, before forming a plug in the contact hole formed with the oxidized metal layer, the forming method further includes: removing the sacrificial layer to expose the the oxide metal layer.

Optionally, in the step of forming a sacrificial layer on the metal precursor layer, the material of the sacrificial layer is amorphous silicon.

Optionally, in the step of forming a sacrificial layer on the metal precursor layer, the thickness of the sacrificial layer is arrive within range.

Optionally, in the step of performing oxidation and annealing on the metal precursor layer formed with the sacrificial layer, the process gas includes oxygen.

Optionally, in the step of performing oxidation annealing on the metal precursor layer formed with the sacrificial layer, the process parameters include: the annealing temperature is in the range of 700°C to 1050°C, the annealing time is in the range of 5s to 20s, and the process gas includes oxygen and Nitrogen, the volume ratio of oxygen and nitrogen in the process gas is in the range of 1:20 to 1:2, and the flow rate of the process gas is in the range of 0.1slm to 30slm.

Optionally, in the step of forming a plug in the contact hole formed with the metal oxide layer, the material of the plug is titanium or tungsten.

Optionally, the semiconductor structure is a fin field effect transistor; in the step of forming the base, the base includes a substrate and fins on the substrate; in the step of forming a gate structure on the base , the gate structure straddles the fin and is located on the surface of part of the top and part of the sidewall of the fin; the step of forming source-drain doped regions in the substrate on both sides of the gate structure includes: forming a stress layer in the fins on both sides of the gate structure; doping the stress layer to form the source-drain doped region; in the step of forming a dielectric layer on the exposed base of the gate structure, the The dielectric layer covers the stress layer; in the step of forming a contact hole through the dielectric layer, the contact hole is located in the dielectric layer on the stress layer and the stress layer is exposed at the bottom; In the step of forming a metal oxide layer on the source-drain doped region, the metal oxide layer is located on the stress layer.

Optionally, the semiconductor structure is an N-type transistor, and in the step of forming a stress layer in the fins on both sides of the gate structure, the material of the stress layer is silicon or silicon carbon; the semiconductor material is a P-type transistor. For the transistor, in the step of forming a stress layer in the fins on both sides of the gate structure, the material of the stress layer is silicon or silicon germanium.

Correspondingly, the present invention also provides a semiconductor structure, including:

a substrate; a gate structure located on the substrate; a source-drain doped region located in the substrate on both sides of the gate structure; a dielectric layer located on the exposed substrate of the gate structure, and the dielectric layer covers the source-drain doped impurity region; a plug located on the source-drain doped region, the plug penetrates through the dielectric layer; a metal oxide layer located between the plug and the source-drain doped region.

Optionally, the material of the metal oxide layer is titanium oxide, cobalt oxide or nickel oxide.

Optionally, the thickness of the metal oxide layer is less than 5 nm.

Optionally, the material of the plug is titanium or tungsten.

Optionally, the semiconductor structure is a fin field effect transistor; the base includes a substrate and a fin located on the substrate; the gate structure crosses the fin and is located on the fin portion on the surface of the top and part of the sidewall; the semiconductor structure further includes: a stress layer located in the fins on both sides of the gate structure, the stress layer is used to form the source-drain doped region; the plug is located On the stress layer; the metal oxide layer is located at least between the stress layer and the plug.

Optionally, the semiconductor structure is an N-type transistor, the material of the stress layer is silicon or silicon carbon; the semiconductor material is a P-type transistor, and the material of the stress layer is silicon or silicon germanium.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the present invention, after the contact hole is formed, a metal oxide layer is formed on the source-drain doped region exposed at the bottom of the contact hole; then a plug is formed in the contact hole formed with the metal oxide layer. Since the metal oxide layer has a lower conduction band step, the setting of the metal oxide layer can effectively reduce the state density in the forbidden band of the source-drain doped region material, thereby effectively reducing the occurrence of the metal-induced gap state phenomenon. It can effectively suppress the Fermi level pinning phenomenon at the interface between the plug and the source-drain doped region, thereby helping to reduce the contact resistance between the plug and the source-drain doped region, and to improve the formed Properties of semiconductor structures.

In an optional solution of the present invention, the thickness of the metal oxide layer is controlled within 5 nm. By controlling the thickness of the metal oxide layer, the metal oxide layer can improve the performance of the interface between the plug and the source-drain doped region without affecting the conductivity between the plug and the source-drain doped region, Effectively suppress the phenomenon of Fermi level pinning at the interface between the plug and the source-drain doped region, which is conducive to reducing the contact resistance between the plug and the source-drain doped region, and is conducive to improving the semiconductor structure formed. performance.

In an optional solution of the present invention, before the step of performing oxidation annealing on the metal precursor layer, a sacrificial layer of amorphous silicon material is formed on the metal precursor layer; after that, the metal precursor layer formed with the sacrificial layer is treated oxidation annealing treatment. During the oxidation annealing process, the oxygen element first diffuses into the sacrificial layer; then diffuses into the metal precursor layer through the sacrificial layer to achieve the purpose of forming a metal oxide layer; therefore, the formation of the sacrificial layer can be effectively Controlling the diffusion rate of oxygen can effectively slow down the oxidation rate of the metal precursor layer, reduce the probability of other semiconductor structures being oxidized, and especially effectively reduce the possibility of oxidation of the source-drain doped region under the metal precursor layer , so as to improve the performance of the formed semiconductor structure and improve the yield of the formed semiconductor structure.

Description of drawings

Figures 1 and 2 are schematic cross-sectional structure diagrams corresponding to each step of a method for forming a semiconductor structure;

3 to 7 are schematic cross-sectional structure diagrams corresponding to each step of an embodiment of the semiconductor structure forming method of the present invention.

Detailed ways

It can be seen from the background art that there is a problem of excessive contact resistance in the semiconductor structure with plugs introduced in the prior art. Combining with a method of forming a semiconductor structure, the reason for the excessive contact resistance is analyzed:

Referring to FIG. 1 and FIG. 2 , there are shown schematic cross-sectional structure diagrams corresponding to each step of a method for forming a semiconductor structure.

As shown in FIG. 1 , a substrate 10 is provided; a gate structure 11 located on the substrate 10 is formed; stress layers 12 located on both sides of the gate structure are formed, and the stress layer 12 is doped to A source-drain doped region is formed; a dielectric layer 13 is formed on the substrate 10 where the gate structure 11 is exposed, and the dielectric layer 13 covers the stress layer 12 .

As shown in FIG. 2 , a plug 15 is formed in the dielectric layer 13 on the stress layer 12 , and the plug 15 penetrates the dielectric layer 13 on the stress layer 12 .

The stress layer 13 is used to form the source and drain doped regions of the semiconductor structure, so the material of the stress layer 13 is usually a doped semiconductor material, for example: the semiconductor structure is an N-type transistor, so the The stress layer 13 is made of N-type doped SiC material. The plug 15 is used to realize the connection between the doped source and drain regions of the semiconductor structure and the external circuit, so the material of the plug 15 is usually metal, such as tungsten.

When the metal is in contact with the semiconductor, metal-induced gap states (Metal-induced gap states, MIGS) will appear in the forbidden band of the semiconductor, which is prone to strong Fermi level pinning (Fermi level pinning, FLP), making The Fermi level at the interface between the metal and the semiconductor material is fixed in the energy band of the semiconductor material, thereby leading to an increase in the contact resistance between the plug 15 and the stress layer 13 .

One method to improve the contact resistance between the plug 15 and the stress layer 13 is to form a metal silicide layer (Silicide) between the plug 15 and the stress layer 12 . However, the formation of the metal silicide layer still cannot effectively improve the problem of Fermi level pinning, so there is still a large contact resistance between the plug 15 and the stress layer 13 .

In order to solve the technical problem, the present invention provides a method for forming a semiconductor structure, including:

forming a base; forming a gate structure on the base; forming source-drain doped regions in the bases on both sides of the gate structure; forming a dielectric layer on the base exposed by the gate structure, and the dielectric layer covers The source-drain doped region; forming a contact hole through the dielectric layer, the bottom of the contact hole exposing the source-drain doped region; forming a metal oxide layer on the source-drain doped region exposed by the contact hole; Plugs are formed in the contact holes where the metal oxide layer is formed.

In the technical solution of the present invention, after the contact hole is formed, a metal oxide layer is formed on the source-drain doped region exposed at the bottom of the contact hole; then a plug is formed in the contact hole formed with the metal oxide layer. Since the metal oxide layer has a lower conduction band step, the setting of the metal oxide layer can effectively reduce the state density in the forbidden band of the source-drain doped region material, thereby effectively reducing the occurrence of the metal-induced gap state phenomenon. It can effectively suppress the Fermi level pinning phenomenon at the interface between the plug and the source-drain doped region, thereby helping to reduce the contact resistance between the plug and the source-drain doped region, and to improve the formed Properties of semiconductor structures.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 3 to FIG. 7 , schematic cross-sectional structure diagrams corresponding to each step of an embodiment of the method for forming a semiconductor structure according to the present invention are shown.

Referring to Figure 3, a substrate is formed.

The substrate is used to provide a basis for process operation.

In this embodiment, the semiconductor structure is a FinFET, so the base includes a substrate 100 and discrete fins 101 on the substrate 100 . In other embodiments of the present invention, the semiconductor structure may also be a planar transistor, and the substrate is a planar substrate.

The substrate 100 is used to provide a process operation platform.

In this embodiment, the material of the substrate 100 is single crystal silicon. In other embodiments of the present invention, the substrate may also be a polysilicon substrate, an amorphous silicon substrate, or a silicon-germanium substrate, a silicon-carbon substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, or III-V compound substrates, such as gallium nitride substrates or gallium arsenide substrates. The material of the substrate can be selected suitable for process requirements or easily integrated.

The fin portion 101 is used to provide a channel of the FinFET.

In this embodiment, the material of the fin portion 101 is the same as that of the substrate 100 , both being single crystal silicon. In other embodiments of the present invention, the material of the fins may also be different from the material of the substrate, and may be selected from materials suitable for forming fins such as germanium, silicon germanium, silicon carbon, or gallium arsenide.

Specifically, the substrate 100 and the fins 101 may be formed simultaneously. The steps of forming the substrate 100 and the fins 101 include: providing an initial substrate; forming a fin mask layer (not shown in the figure) on the surface of the initial substrate; The initial substrate is etched for a mask to form the substrate 100 and the fins 101 on the substrate 100 .

The fin mask layer is used to define the size and position of the fin 101 .

The step of forming the fin mask layer includes: forming a mask material layer on the initial substrate; forming a pattern layer on the mask material layer; using the pattern layer as a mask, etching the A mask material layer exposing the initial substrate to form the fin mask layer.

The pattern layer is used to pattern the mask material layer to define the size and position of the fins.

In this embodiment, the pattern layer is a patterned photoresist layer, which can be formed by a coating process and a photolithography process. In other embodiments of the present invention, the pattern layer can also be a mask formed by a multiple patterning mask process, so as to reduce the feature size of the fins and the distance between adjacent fins, and improve the integration of the formed semiconductor structure. Spend. The multiple patterned mask process includes: self-aligned double patterned (Self-aligned Double Patterned, SaDP) process, self-aligned triple patterned (Self-aligned triple patterned) process, or self-aligned quadruple patterned ( Self-aligned Double Double Patterned, SaDDP) process.

It should be noted that, in this embodiment, after the substrate 100 and the fin 101 are formed, the fin mask layer on the top of the fin 101 is reserved. The material of the fin mask layer is silicon nitride, which is used to define the position of the stop layer of the planarization process in the subsequent process and protect the fin 101 .

In this embodiment, after forming the substrate 100 and the fins 101, the forming method further includes: forming an isolation layer (not shown in the figure) on the substrate 100 not covered by the fins 101 , the top of the isolation layer is lower than the top of the fin 101 and covers part of the surface of the sidewall of the fin 101 .

The isolation layer is used to realize electrical isolation between adjacent fins 101 and between adjacent semiconductor structures.

In this embodiment, the material of the isolation layer is silicon oxide. In other embodiments of the present invention, the material of the isolation layer may also be silicon nitride or silicon oxynitride.

The step of forming the isolation layer includes: forming an isolation material layer on the substrate 100 not covered by the fins 101 by chemical vapor deposition (for example: fluid chemical vapor deposition), the isolation material layer covers the The fin mask layer; removing the isolation material layer higher than the fin mask layer by means of chemical mechanical grinding; removing part of the thickness of the remaining isolation material layer by etching back to form the isolation layer.

It should be noted that, after forming the isolation layer, the forming method further includes: removing the fin mask layer to expose the top of the fin 101 .

Continuing to refer to FIG. 3 , a gate structure 110 is formed on the substrate.

The gate structure 110 is the gate structure 110 of the semiconductor structure, and is used to control the conduction and disconnection of the conduction channel of the semiconductor structure.

In this embodiment, the semiconductor structure is a fin field effect transistor, and the base includes a substrate 100 and a fin portion 101 on the substrate 100 . Therefore, in the step of forming the gate structure 110 on the substrate, the gate structure 110 crosses the fin 101 and is located on a part of the top and a part of the sidewall of the fin 101 .

The gate structure includes: an interface layer (not shown) on the substrate; a gate dielectric layer (not shown) on the interface layer (not shown); a gate dielectric layer (not shown) on the interface layer (not shown); A capping layer (not marked in the figure) on the capping layer (not marked in the figure); a work function layer (not marked in the figure) on the capping layer; a blocking layer (not marked in the figure) on the work function layer ); a metal layer on the barrier layer shown.

The interface layer is used to provide a good interface foundation for subsequent film layers to improve the quality of subsequent film layers, especially to improve the quality of the gate dielectric layer; in addition, the interface layer is also used to communicate with the grid The dielectric layer constitutes a stacked structure to realize electrical isolation between the gate structure and the channel in the substrate.

In this embodiment, the material of the interface layer is silicon oxide, which is formed by thermal oxidation. In other embodiments of the present invention, the material of the interface layer may also be other materials such as silicon oxycarbonitride, which may be formed by film deposition processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

The gate dielectric layer is used to realize electrical isolation between the formed gate structure and the channel in the substrate.

Specifically, the material of the gate dielectric layer is a high-K dielectric material. Wherein, the high-K dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. In this embodiment, the material of the gate dielectric layer is HfO ₂ . In other embodiments of the present invention, the material of the gate dielectric layer may also be selected from ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al ₂ O ₃ .

In this embodiment, the semiconductor structure is a fin field effect transistor, and the gate dielectric layer crosses the fin 101 and is located on part of the top and part of the sidewall of the fin 101 .

The gate dielectric layer can be formed by atomic layer deposition. In other embodiments of the present invention, the gate dielectric layer may also be formed by other film deposition methods such as chemical vapor deposition or physical vapor deposition.

The capping layer (cap layer) is used to protect the gate dielectric layer, preventing metal ions in the subsequent work function layer from diffusing into the gate dielectric layer and affecting the electrical isolation performance of the gate dielectric layer; Preventing the oxygen element in the gate dielectric layer from diffusing into the work function layer to cause the increase of oxygen vacancies.

In this embodiment, the material of the capping layer is titanium nitride. In other embodiments of the present invention, the material of the capping layer may also be titanium nitride silicon nitride or tantalum nitride.

The work function layer is used to adjust the threshold voltage of transistors in the formed semiconductor structure. In this embodiment, the semiconductor structure is an N-type transistor, so the work function layer is used to adjust the threshold voltage of the N-type transistor.

Therefore, in this embodiment, the material of the work function layer is an N-type work function material. The work function of the N-type work function material ranges from 3.9eV to 4.5eV, such as 4eV, 4.1eV or 4.3eV. The material of the work function layer can be one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN, and can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition.

The barrier layer is used to protect the work function layer and prevent impurity ions in the subsequent process from diffusing into the work function layer, which is beneficial to reduce the work function value of the work function layer and the formed transistor. Threshold voltage; the barrier layer is also used to improve the adhesion of the subsequently formed metal layer, which is beneficial to improve the reliability of the formed gate structure.

In this embodiment, the barrier layer 230 is made of titanium nitride, which can be formed by atomic layer deposition. In other embodiments of the present invention, the material of the barrier layer may also be titanium nitride silicide, and may also be formed by film deposition methods such as chemical vapor deposition or physical vapor deposition.

The metal layer is used as an electrode to realize electrical connection with an external circuit.

In this embodiment, the material of the metal layer is W. In other embodiments of the present invention, the material of the metal layer may also be Al, Cu, Ag, Au, Pt, Ni or Ti and the like.

This embodiment adopts a gate-first process, that is, the gate structure 110 is formed before the source-drain doped regions are formed. Other embodiments of the present invention may also adopt a gate-last process, that is, the gate structure is formed after the source-drain doped region.

When the gate-last process is adopted, in the step of forming the gate structure on the substrate, the gate structure is a dummy gate structure, which is used to occupy a space position for a subsequently formed gate structure.

In some embodiments of the present invention, the dummy gate structure is a single-layer structure, including a dummy gate made of polysilicon material. In other embodiments of the present invention, the material of the dummy gate can also be other materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride or amorphous carbon. In other embodiments of the present invention, the dummy gate structure may also be a stacked structure, including a dummy gate and a dummy oxide layer on the dummy gate, and the material of the dummy oxide layer may be silicon oxide and nitrogen silicon oxide.

It should be noted that, after forming the gate structure, the forming method further includes: forming sidewalls (not shown in the figure) on the sidewalls of the gate structure to protect the gate structure. The material of the side wall may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall may be a single-layer structure or laminated structures. In this embodiment, the sidewall is a single-layer structure, and the material of the sidewall is silicon nitride.

Referring to FIG. 3 , source and drain doped regions located in the substrate on both sides of the gate structure 110 are formed.

The source-drain doped region is used to form a source region or a drain region of the semiconductor structure.

In this embodiment, the semiconductor structure is a fin field effect transistor, and the source-drain doped region includes a doped stress layer. Therefore, the step of forming the source-drain doped regions in the substrate on both sides of the gate structure 110 includes: forming a stress layer 120 in the fin portion 101 on both sides of the gate structure 110; doping the stress layer 120 Doped to form the source and drain doped regions.

Specifically, the step of forming the stress layer 120 includes: forming the stress layer 120 in the fins 101 on both sides of the gate structure 110 by means of epitaxial growth. The semiconductor structure is an N-type transistor, and in the step of forming a stress layer 120 in the fins 101 on both sides of the gate structure 110 , the material of the stress layer 120 is silicon or silicon carbon.

In other embodiments of the present invention, the semiconductor material is a P-type transistor, and in the step of forming a stress layer in the fins on both sides of the gate structure, the material of the stress layer is silicon or silicon germanium.

The step of doping the stress layer 120 includes: during the process of forming the stress layer 120, performing in-situ ion doping to achieve the doping of the stress layer 120; or forming the stress layer 120 Afterwards, ion implantation is performed on the stress layer 120 to achieve doping of the stress layer 120 .

Since the semiconductor structure is an N-type transistor, the dopant ions in the stress layer 120 are N-type ions, including phosphorus, arsenic or antimony.

It should be noted that, in this embodiment, after forming the source-drain doped region, the forming method further includes: forming a contact hole etching stop layer, the contact hole etching stop layer covering the stress layer 120 and the gate structure 110 .

Continuing to refer to FIG. 3 , a dielectric layer 130 is formed on the exposed base of the gate structure 110 , and the dielectric layer 130 covers the source-drain doped region.

The dielectric layer 130 is used to realize electrical isolation between adjacent semiconductor structures.

In this embodiment, the material of the dielectric layer 130 is silicon oxide. In other embodiments of the present invention, the material of the dielectric layer may also be selected from other dielectric materials such as silicon nitride, silicon oxynitride, or silicon oxycarbonitride.

Specifically, the base includes a substrate 100 and fins 101 located on the substrate 100 , and there is an isolation layer between adjacent fins 101 . Therefore, the dielectric layer 130 is located on the substrate 100 , the fin portion 101 and the isolation layer.

It should be noted that, in other embodiments of the present invention, when the gate-last process is adopted, the gate structure is a dummy gate structure, so the step of forming the dielectric layer includes: after forming the source-drain doped region, Forming a first dielectric layer on the substrate exposed by the dummy gate structure, the first dielectric layer exposing the dummy gate structure; removing the dummy gate structure, forming a gate opening in the first dielectric layer; A gate structure is formed in the gate opening; a second dielectric layer is formed on the first dielectric layer and the gate structure, and the second dielectric layer and the first dielectric layer are used to form the dielectric layer.

The first dielectric layer is used to realize electrical isolation between adjacent semiconductor structures, and is also used to define the size and position of the gate structure; the second dielectric layer is used to realize electrical isolation between adjacent semiconductor structures .

Since the first dielectric layer and the second dielectric layer are used to form the dielectric layer, in this embodiment, the material of the first dielectric layer and the second dielectric layer is silicon oxide. In other embodiments of the present invention, the first dielectric layer and the second dielectric layer may also be made of different insulating materials.

For the technical solution of forming the gate structure in the gate opening, reference may be made to the technical solution of the gate structure in the foregoing embodiments, and the present invention will not repeat them here.

Referring to FIG. 4 , a contact hole 151 is formed through the dielectric layer 130 , and the bottom of the contact hole 151 exposes the doped source and drain regions.

The contact hole 151 is used to expose the doped source and drain regions, so as to provide a process basis for the formation of subsequent plugs.

In this embodiment, the source-drain doped region includes a stress layer 120, so the step of forming the contact hole 151 includes: removing part of the material of the dielectric layer 130 on the stress layer 120 by mask dry etching. A contact hole 151 is formed in the dielectric layer 130 , the contact hole 151 penetrates the dielectric layer 130 and exposes the stress layer 120 at the bottom.

Specifically, the process parameters for forming the contact hole 151 by mask dry etching include: the process gas pressure is 10 mTorr to 2000 mTorr; the process gas includes: CH ₄ : the flow rate is in the range of 8 sccm to 500 sccm; CHF ₃ : the flow rate In the range of 30sccm to 200sccm; RF power: in the range of 100W to 1300W; bias voltage in the range of 80V to 500V; etching time in the range of 4s to 500s.

Referring to FIG. 5 and FIG. 6 , a metal oxide layer 160 is formed on the source-drain doped region exposed by the contact hole 151 .

The metal oxide layer 160 has a lower conduction band step, so the metal oxide layer 160 can effectively reduce the density of states in the forbidden band of the source-drain doped region material, thereby effectively reducing the metal-induced gap state phenomenon. Appearing, the phenomenon of Fermi level pinning at the interface between the plug and the source-drain doped region can be effectively suppressed, thereby helping to reduce the contact resistance between the plug and the source-drain doped region, and improving the Properties of the formed semiconductor structures.

It should be noted that, in this embodiment, the source-drain doped region includes a stress layer 120 , and the stress layer 120 is exposed at the bottom of the contact hole 151 . Therefore, the metal oxide layer 160 is located on the exposed stress layer 120 at the bottom of the contact hole 151 . In addition, the metal oxide layer 160 is also located on the sidewall of the contact hole 151 and the top of the dielectric layer 130 .

In this embodiment, the material of the metal oxide layer 160 is titanium oxide. In other embodiments of the present invention, the material of the metal oxide layer may also be cobalt oxide or nickel oxide.

It should be noted that, generally, metal oxides have poor electrical conductivity, so the thickness of the metal oxide layer 160 should not be too large. If the thickness of the metal oxide layer 160 is too large, the existence of the metal oxide layer 160 will increase the contact resistance between the plug and the doped source and drain regions, thereby affecting the performance of the formed semiconductor structure. Therefore, in this embodiment, in the step of forming the metal oxide layer 160 on the source-drain doped region exposed by the contact hole 151 , the thickness of the metal oxide layer 160 is less than 5 nm.

Due to the small thickness of the metal oxide layer 160, electrons can tunnel in the metal oxide layer 160, so that the metal oxide layer 160 can improve the performance of the interface between the plug and the source-drain doped region. function, without affecting the conductivity between the plug and the source-drain doped region, effectively suppressing the phenomenon of Fermi level pinning at the interface between the plug and the source-drain doped region, which is conducive to reducing the plug The contact resistance between the source and drain doped regions is beneficial to improve the performance of the formed semiconductor structure.

Specifically, the step of forming the metal oxide layer 160 on the doped source and drain regions exposed by the contact hole 151 includes: as shown in FIG. 5 , forming a metal precursor layer on the doped source and drain regions exposed by the contact hole 151 161 ; as shown in FIG. 6 , perform oxidation treatment on the metal precursor layer 161 to form the metal oxide layer 160 .

The metal precursor layer 161 is used to provide metal elements for the formation of the metal oxide layer 160 .

In this embodiment, the material of the metal oxide layer 160 is titanium oxide, so in the step of forming the metal precursor layer 161 on the source-drain doped region exposed by the contact hole 151, the material of the metal precursor layer 161 is titanium.

In other embodiments of the present invention, the material of the metal oxide layer may also be cobalt oxide or nickel oxide. Correspondingly, the material of the metal oxide layer is cobalt oxide, and in the step of forming a metal precursor layer on the source-drain doped region exposed by the contact hole, the material of the metal precursor layer is cobalt; the metal oxide layer The material of the metal precursor layer is nickel oxide, and in the step of forming a metal precursor layer on the source-drain doping region exposed by the contact hole, the material of the metal precursor layer is nickel.

It should be noted that the thickness of the metal precursor layer 161 should neither be too large nor too small.

If the thickness of the metal precursor layer 161 is too small, the thickness of the metal oxide layer 160 formed is too small, which is not conducive to the improvement of the interface performance between the plug and the source-drain doped region by the metal oxide layer 160; If the thickness of the metal precursor layer 161 is too large, it is easy to increase the waste of materials and increase the difficulty of the process. In this embodiment, in the step of forming the metal precursor layer 161 on the source-drain doped region exposed by the contact hole 151, the thickness of the metal precursor layer 161 is arrive within range.

The metal precursor layer 161 can be formed on the doped source and drain regions exposed by the contact hole 151 by atomic layer deposition. In this embodiment, the metal precursor layer 161 is not only located on the stress layer 120 exposed by the contact hole 151 , but also located on the sidewall of the contact hole 151 and the surface of the dielectric layer 130 . Therefore, the method of forming the metal precursor layer 161 by atomic layer deposition can enhance the thickness control ability of the metal precursor layer 161, and is beneficial to the control of the thickness of the formed metal oxide layer 160; it can also effectively improve the thickness of the metal precursor layer 161. The step coverage is beneficial to improve the quality of the formed metal oxide layer 160 and the quality of the formed semiconductor structure. In other embodiments of the present invention, the metal precursor layer can also be formed by other film deposition methods such as chemical vapor deposition or physical vapor deposition.

The step of oxidizing the metal precursor layer 161 is used to transform the metal precursor layer 161 into the metal oxide layer 160 .

Specifically, the step of oxidizing the metal precursor layer 161 includes: as shown in FIG. 5 , forming a sacrificial layer 162 on the metal precursor layer 161 ; Processing 163 , oxidizing the metal precursor layer 161 to form the metal oxide layer 160 .

The sacrificial layer 162 is used to protect other semiconductor structures on the substrate 100 .

Specifically, during the oxidation annealing treatment 163 , the sacrificial layer 162 is oxidized first, and then the oxygen element in the sacrificial layer 162 diffuses into the precursor metal layer 161 . Therefore, the formation of the sacrificial layer 162 can effectively slow down the oxidation speed of the metal precursor layer 161 . Therefore, the formation of the sacrificial layer 162 can effectively control the diffusion rate of oxygen element, can effectively slow down the oxidation rate of the metal precursor layer 161, can reduce the probability of other semiconductor structures being oxidized, and especially can effectively reduce the oxidation rate of the metal precursor layer 161. The possibility that the source-drain doped region under the layer 161 is oxidized is beneficial to improving the performance of the formed semiconductor structure and the yield rate of forming the semiconductor structure.

In this embodiment, in the step of forming the sacrificial layer 162 on the metal precursor layer 161 , the material of the sacrificial layer 162 is amorphous silicon. The amorphous silicon material has low density and can effectively absorb the oxygen element in the oxidation annealing process 163, thereby effectively achieving a balance between production efficiency and process risk reduction. Moreover, the process temperature for forming the amorphous silicon material is relatively low, which can effectively reduce the influence of the formation of the sacrificial layer 162 on the formed semiconductor structure.

It should be noted that the thickness of the sacrificial layer 162 should neither be too large nor too small.

If the thickness of the sacrificial layer 162 is too small, it will affect the function of the sacrificial layer 162 to slow down the oxidation rate, which may increase the process risk that other semiconductor structures are affected by the oxidation annealing treatment 163; the thickness of the sacrificial layer 162 If it is too large, the aspect ratio of the remaining contact hole 151 will be large, which may affect the uniformity of oxidation of the precursor metal layer 161 , and may also cause waste of materials and increase the difficulty of the process. Therefore, in this embodiment, in the step of forming the sacrificial layer 162 on the metal precursor layer 161, the thickness of the sacrificial layer 162 is arrive within range.

The oxidation annealing treatment 163 is used to provide the oxygen element of the oxidized metal layer 160 , and make the oxygen element react with the metal element of the precursor metal layer 161 to form the oxidized metal layer 160 .

Specifically, in the step of performing oxidation annealing treatment 163 on the metal precursor layer 161 formed with the sacrificial layer 162 , the process gas includes oxygen to provide oxygen element.

It should be noted that, in the step of performing oxidation annealing treatment 163 on the metal precursor layer 161 formed with the sacrificial layer 162 , the annealing temperature should not be too high or too low, and the annealing time should not be too long or too short.

If the annealing temperature is too high, or the annealing time is too long, the oxygen element will diffuse widely, which will increase the process risk. For example, the stress layer 120 may be oxidized, thereby affecting the performance of the formed semiconductor structure; if the annealing temperature is too low, Or if the annealing time is too short, it is not conducive to the diffusion of oxygen, and the oxidation of the precursor metal layer 161 is not complete, which is not conducive to the formation of the oxide metal layer 160, which will affect the effect of the oxide metal layer 160 on the plug and the source-drain doping region. The effect of improving the performance of the interface. Therefore, in this embodiment, in the step of performing oxidation annealing treatment 163 on the metal precursor layer 161 formed with the sacrificial layer 162, the process parameters include: the annealing temperature is in the range of 700°C to 1050°C, the annealing time is in the range of 5s to 20s, The process gas includes oxygen and nitrogen, the volume ratio of oxygen and nitrogen in the process gas is in the range of 1:20 to 1:2, and the flow rate of the process gas is in the range of 0.1slm to 30slm.

Referring to FIG. 7 , a plug 150 is formed in the contact hole 151 (shown in FIG. 6 ) where the metal oxide layer 160 is formed.

The plug 150 is used to realize the electrical connection between the source and drain doped regions and external circuits.

In this embodiment, the material of the plug 150 is titanium. In other embodiments of the present invention, the material of the plug may also be tungsten. Specifically, the source-drain doped region includes the stress layer 120 , so the plug 150 is located on the stress layer 120 and penetrates the dielectric layer 130 on the stress layer 120 .

Specifically, the step of forming the plug 150 includes: filling the contact hole 151 formed with the metal oxide layer 160 with a conductive material, the conductive material covering the dielectric layer 130; removing the conductive material higher than the dielectric layer 130; material to form the plug 150 .

The metal oxide layer 160 has a lower conduction band step, so it can effectively reduce the density of states in the forbidden band of the source-drain doped region material, thereby effectively reducing the occurrence of metal-induced gap state phenomena, and effectively suppressing The Fermi level pinning phenomenon at the interface between the plug 150 and the source-drain doped region is beneficial to reduce the contact resistance between the plug 150 and the source-drain doped region, and to improve the formed Properties of semiconductor structures.

It should be noted that, in this embodiment, the sacrificial layer 162 is also formed on the oxide metal layer 160, so, as shown in FIG. As shown in FIG. 7, before forming the plug 150 in the contact hole 151 (as shown in FIG. 6) formed with the metal oxide layer 160, the forming method further includes: removing the sacrificial layer 162 to expose the metal oxide layer 160.

Correspondingly, referring to FIG. 7 , a schematic cross-sectional structure diagram of an embodiment of the semiconductor structure of the present invention is shown.

As shown in Figure 7, the semiconductor structure includes:

a substrate; a gate structure 110 on the substrate; a source-drain doped region in the substrate on both sides of the gate structure 110; a dielectric layer 130 on the exposed substrate of the gate structure 110, and the dielectric layer 130 covers The source-drain doped region; a plug 150 located on the source-drain doped region, the plug 150 passing through the dielectric layer 130; located between the plug 150 and the source-drain doped region The oxide metal layer 160.

The substrate is used to provide a basis for process operation.

In this embodiment, the semiconductor structure is a FinFET, so the base includes a substrate 100 and discrete fins 101 on the substrate 100 . In other embodiments of the present invention, the semiconductor structure may also be a planar transistor, and the substrate is a planar substrate.

The substrate 100 is used to provide a process operation platform.

In this embodiment, the material of the substrate 100 is single crystal silicon. In other embodiments of the present invention, the substrate may also be a polysilicon substrate, an amorphous silicon substrate, or a silicon-germanium substrate, a silicon-carbon substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, or III-V compound substrates, such as gallium nitride substrates or gallium arsenide substrates. The material of the substrate can be selected suitable for process requirements or easily integrated.

The fin portion 101 is used to provide a channel of the FinFET.

In this embodiment, the material of the fin portion 101 is the same as that of the substrate 100 , both being single crystal silicon. In other embodiments of the present invention, the material of the fins may also be different from the material of the substrate, and may be selected from materials suitable for forming fins such as germanium, silicon germanium, silicon carbon, or gallium arsenide.

It should be noted that, in this embodiment, the semiconductor structure further includes: an isolation layer (not shown in the figure) located on the substrate 100 not covered by the fin 101 , the top of the isolation layer is lower than the fin The top of the fin portion 101 and covers part of the surface of the sidewall of the fin portion 101 .

The isolation layer is used to realize electrical isolation between adjacent fins 101 and between adjacent semiconductor structures. In this embodiment, the material of the isolation layer is silicon oxide. In other embodiments of the present invention, the material of the isolation layer may also be silicon nitride or silicon oxynitride.

The gate structure 110 is the gate structure 110 of the semiconductor structure, and is used to control the conduction and disconnection of the conduction channel of the semiconductor structure.

In this embodiment, the semiconductor structure is a fin field effect transistor, and the base includes a substrate 100 and a fin portion 101 on the substrate 100 . Therefore, the gate structure 110 straddles the fin 101 and is located on part of the top and part of the sidewall of the fin 101 .

The gate structure includes: an interface layer (not shown) on the substrate; a gate dielectric layer (not shown) on the interface layer (not shown); a gate dielectric layer (not shown) on the interface layer (not shown); A capping layer (not marked in the figure) on the capping layer (not marked in the figure); a work function layer (not marked in the figure) on the capping layer; a blocking layer (not marked in the figure) on the work function layer ); a metal layer on the barrier layer shown.

The interface layer is used to provide a good interface foundation for subsequent film layers to improve the quality of subsequent film layers, especially to improve the quality of the gate dielectric layer; in addition, the interface layer is also used to communicate with the grid The dielectric layer constitutes a stacked structure to realize electrical isolation between the gate structure and the channel in the substrate.

In this embodiment, the material of the interface layer is silicon oxide. In other embodiments of the present invention, the material of the interface layer may also be other materials such as silicon oxycarbonitride.

The gate dielectric layer is used to realize electrical isolation between the gate structure 110 and the channel in the substrate.

Specifically, the material of the gate dielectric layer is a high-K dielectric material. Wherein, the high-K dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. In this embodiment, the material of the gate dielectric layer is HfO ₂ . In other embodiments of the present invention, the material of the gate dielectric layer may also be selected from ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al ₂ O ₃ .

In this embodiment, the semiconductor structure is a fin field effect transistor, and the gate dielectric layer crosses the fin 101 and is located on part of the top and part of the sidewall of the fin 101 .

The capping layer (cap layer) is used to protect the gate dielectric layer, preventing metal ions in the subsequent work function layer from diffusing into the gate dielectric layer and affecting the electrical isolation performance of the gate dielectric layer; Preventing the oxygen element in the gate dielectric layer from diffusing into the work function layer to cause the increase of oxygen vacancies. In this embodiment, the material of the capping layer is titanium nitride. In other embodiments of the present invention, the material of the capping layer may also be titanium nitride silicon nitride or tantalum nitride.

The work function layer is used to adjust the threshold voltage of transistors in the semiconductor structure. In this embodiment, the semiconductor structure is an N-type transistor, so the work function layer is used to adjust the threshold voltage of the N-type transistor.

Therefore, in this embodiment, the material of the work function layer is an N-type work function material. The work function of the N-type work function material ranges from 3.9eV to 4.5eV, such as 4eV, 4.1eV or 4.3eV. The material of the work function layer may be one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN.

The barrier layer is used to protect the work function layer and prevent impurity ions in the subsequent process from diffusing into the work function layer, which is conducive to reducing the work function value of the work function layer and reducing the Threshold voltage; the barrier layer is also used to improve the adhesion of the subsequent metal layer, which is beneficial to improve the reliability of the gate structure. In this embodiment, the barrier layer is made of titanium nitride. In other embodiments of the present invention, the material of the barrier layer may also be titanium nitride silicide.

The metal layer is used as an electrode to realize electrical connection with an external circuit.

In this embodiment, the material of the metal layer is W. In other embodiments of the present invention, the material of the metal layer may also be Al, Cu, Ag, Au, Pt, Ni or Ti and the like.

It should be noted that the semiconductor structure further includes: sidewalls (not shown in the figure) located on the sidewalls of the gate structure to protect the gate structure. The material of the side wall may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall may be a single-layer structure or laminated structures. In this embodiment, the sidewall is a single-layer structure, and the material of the sidewall is silicon nitride.

The source-drain doped region is used to form a source region or a drain region of the semiconductor structure.

In this embodiment, the semiconductor structure is a fin field effect transistor, and the doped source and drain regions include: stress layers 120 located in the fins on both sides of the gate structure.

Specifically, the semiconductor structure is an N-type transistor, so the material of the stress layer 120 is silicon or silicon carbon. In other embodiments of the present invention, the semiconductor material is a P-type transistor, and the material of the stress layer is silicon or silicon germanium.

Since the semiconductor structure is an N-type transistor, the dopant ions in the stress layer 120 are N-type ions, including phosphorus, arsenic or antimony.

It should be noted that, the semiconductor structure further includes: a contact hole etch stop layer covering the stress layer 120 and the gate structure 110 . In this embodiment, the material of the etching stop layer of the contact hole is silicon nitride.

The dielectric layer 130 is used to realize electrical isolation between adjacent semiconductor structures.

In this embodiment, the material of the dielectric layer 130 is silicon oxide. In other embodiments of the present invention, the material of the dielectric layer may also be selected from other dielectric materials such as silicon nitride, silicon oxynitride, or silicon oxycarbonitride.

Specifically, the base includes a substrate 100 and fins 101 located on the substrate 100 , and there is an isolation layer between adjacent fins 101 . Therefore, the dielectric layer 130 is located on the substrate 100 , the fin portion 101 and the isolation layer.

The plug 150 is used to realize the electrical connection between the source and drain doped regions and external circuits.

In this embodiment, the material of the plug 150 is titanium. In other embodiments of the present invention, the material of the plug may also be tungsten. Specifically, the source-drain doped region includes the stress layer 120 , so the plug 150 is located on the stress layer 120 and penetrates the dielectric layer 130 on the stress layer 120 .

The metal oxide layer 160 is used to reduce the contact resistance between the plug 150 and the source-drain doped region.

The metal oxide layer 160 has a lower conduction band step, so the metal oxide layer 160 can effectively reduce the density of states in the forbidden band of the source-drain doped region material, thereby effectively reducing the metal-induced gap state phenomenon. Appearing, the phenomenon of Fermi level pinning at the interface between the plug 150 and the source-drain doped region can be effectively suppressed, thereby helping to reduce the contact resistance between the plug 150 and the source-drain doped region. It is beneficial to improve the performance of the semiconductor structure.

In this embodiment, the source-drain doped region includes a stress layer 120, and the plug 150 is located at least partly on the stress layer 120, so the metal oxide layer 160 is located between the plug 150 and the stress layer. Between 120.

In this embodiment, the material of the metal oxide layer 160 is titanium oxide. In other embodiments of the present invention, the material of the metal oxide layer may also be cobalt oxide or nickel oxide.

Normally, metal oxides have poor electrical conductivity, so the thickness of the metal oxide layer 160 should not be too large. If the thickness of the metal oxide layer 160 is too large, the presence of the metal oxide layer 160 will increase the contact resistance between the plug 150 and the source-drain doped region, thereby affecting the performance of the semiconductor structure. . Therefore, in this embodiment, the thickness of the metal oxide layer 160 is less than 5 nm.

It should be noted that, due to the small thickness of the metal oxide layer 160, electrons can tunnel in the metal oxide layer 160, so that the metal oxide layer 160 can improve the doping of the plug 150 and the source and drain. The role of the interface performance between the regions without affecting the conductivity between the plug 150 and the source-drain doped region, effectively suppressing the phenomenon of Fermi level pinning at the interface between the plug 150 and the source-drain doped region , it is beneficial to reduce the contact resistance between the plug 150 and the source-drain doped region, and it is beneficial to improve the performance of the semiconductor structure.

To sum up, in the technical solution of the present invention, after the contact hole is formed, a metal oxide layer is formed on the source-drain doped region exposed at the bottom of the contact hole; plug. Since the metal oxide layer has a lower conduction band step, the setting of the metal oxide layer can effectively reduce the state density in the forbidden band of the source-drain doped region material, thereby effectively reducing the occurrence of the metal-induced gap state phenomenon. It can effectively suppress the Fermi level pinning phenomenon at the interface between the plug and the source-drain doped region, thereby helping to reduce the contact resistance between the plug and the source-drain doped region, and to improve the formed Properties of semiconductor structures. Moreover, in an optional solution of the present invention, the thickness of the metal oxide layer is controlled within 5 nm. By controlling the thickness of the metal oxide layer, the metal oxide layer can improve the performance of the interface between the plug and the source-drain doped region without affecting the conductivity between the plug and the source-drain doped region, Effectively suppress the phenomenon of Fermi level pinning at the interface between the plug and the source-drain doped region, which is conducive to reducing the contact resistance between the plug and the source-drain doped region, and is conducive to improving the semiconductor structure formed. performance. In addition, in an optional solution of the present invention, before the step of performing oxidation and annealing on the metal precursor layer, a sacrificial layer of amorphous silicon material is formed on the metal precursor layer; The layer is subjected to an oxidation annealing treatment. During the oxidation annealing process, the oxygen element first diffuses into the sacrificial layer; then diffuses into the metal precursor layer through the sacrificial layer to achieve the purpose of forming a metal oxide layer; therefore, the formation of the sacrificial layer can be effectively Controlling the diffusion rate of oxygen can effectively slow down the oxidation rate of the metal precursor layer, reduce the probability of other semiconductor structures being oxidized, and especially effectively reduce the possibility of oxidation of the source-drain doped region under the metal precursor layer , so as to improve the performance of the formed semiconductor structure and improve the yield of the formed semiconductor structure.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. a kind of forming method of semiconductor structure, which is characterized in that including：

Form substrate；

Gate structure is formed on the substrate；

It is formed and is located at the intrabasement source and drain doping area in the gate structure both sides；

Dielectric layer is formed in the substrate that the gate structure exposes, the dielectric layer covers the source and drain doping area；

The contact hole through the dielectric layer is formed, the source and drain doping area is exposed in the contact hole bottom；

Metal oxide layer is formed in the source and drain doping area that the contact hole exposes；

Plug is formed in the contact hole for being formed with metal oxide layer.

2. forming method as described in claim 1, which is characterized in that formed in the source and drain doping area that the contact hole exposes In the step of metal oxide layer, the material of the metal oxide layer is titanium oxide, cobalt oxide or nickel oxide.

3. forming method as described in claim 1, which is characterized in that formed in the source and drain doping area that the contact hole exposes In the step of metal oxide layer, the thickness of the metal oxide layer is less than or equal to 5nm.

4. forming method as described in claim 1, which is characterized in that formed in the source and drain doping area that the contact hole exposes The step of metal oxide layer includes：

Metal front floor is formed in the source and drain doping area that the contact hole exposes；

Oxidation processes are carried out to the metal front layer, to form the metal oxide layer.

5. forming method as claimed in claim 4, which is characterized in that the material of the metal oxide layer is titanium oxide, in institute It states in the step of forming metal front floor in the source and drain doping area of contact hole exposing, the material of the metal front layer is titanium；

The material of the metal oxide layer is cobalt oxide, and metal front floor is formed in the source and drain doping area that the contact hole exposes The step of in, the material of the metal front layer is cobalt；

The material of the metal oxide layer is nickel oxide, and metal front floor is formed in the source and drain doping area that the contact hole exposes The step of in, the material of the metal front layer is nickel.

6. forming method as claimed in claim 4, which is characterized in that formed in the source and drain doping area that the contact hole exposes In the step of metal front layer, the thickness of the metal front layer existsIt arrivesIn range.

7. forming method as claimed in claim 4, which is characterized in that the step of carrying out oxidation processes to the metal front layer Including：

Sacrificial layer is formed on the metal front layer；

Metal front layer to being formed with sacrificial layer carries out oxidizing annealing processing, and the metal front layer is made to aoxidize to form the oxygen Change metal layer；

After metal front layer to being formed with sacrificial layer carries out oxidizing annealing processing, in the contact hole for being formed with metal oxide layer Before interior formation plug, the forming method further includes：It removes the sacrificial layer and exposes the metal oxide layer.

8. forming method as claimed in claim 7, which is characterized in that in the step of forming sacrificial layer on the metal front layer In, the material of the sacrificial layer is non-crystalline silicon.

9. forming method as claimed in claim 7, which is characterized in that in the step of forming sacrificial layer on the metal front layer In, the thickness of the sacrificial layer existsIt arrivesIn range.

10. forming method as claimed in claim 7, which is characterized in that the metal front layer to being formed with sacrificial layer carries out oxygen In the step of annealing processing, process gas includes oxygen.

11. forming method as claimed in claim 10, which is characterized in that the metal front layer to being formed with sacrificial layer carries out oxygen In the step of annealing processing, technological parameter includes：Within the scope of 700 DEG C to 1050 DEG C, annealing time arrives annealing temperature in 5s Within the scope of 20s, process gas includes oxygen and nitrogen, and the volume ratio of oxygen and nitrogen is 1 in process gas:20 to 1:2 ranges Interior, process gas flow is in 0.1slm to 30slm ranges.

12. forming method as described in claim 1, which is characterized in that formed in the contact hole for being formed with metal oxide layer In the step of plug, the material of the plug is titanium or tungsten.

13. forming method as described in claim 1, which is characterized in that the semiconductor structure is fin formula field effect transistor；

In the step of forming substrate, the substrate includes substrate and the fin on the substrate；

In the step of forming gate structure on the substrate, the gate structure is across the fin and is located at the fin portion At the top of point and on the surface of partial sidewall；

Forming the step of being located at the intrabasement source and drain doping area in the gate structure both sides includes：In the gate structure both sides Stressor layers are formed in fin；The stressor layers are doped to form the source and drain doping area；

In the step of forming dielectric layer in the substrate that the gate structure exposes, the dielectric layer covers the stressor layers；

Formed through the dielectric layer contact hole the step of in, the contact hole be located at the dielectric layer in the stressor layers Nei and Expose the stressor layers in bottom；

In the step of forming metal oxide layer in the source and drain doping area that the contact hole exposes, the metal oxide layer is located at institute It states in stressor layers.

14. forming method as claimed in claim 13, which is characterized in that the semiconductor structure is N-type transistor, described In the step of forming stressor layers in the fin of gate structure both sides, the material of the stressor layers is silicon or carbon silicon；

The semi-conducting material be P-type transistor, in the fin of the gate structure both sides formed stressor layers the step of in, institute The material for stating stressor layers is silicon or germanium silicon.

15. a kind of semiconductor structure, which is characterized in that including：

Substrate；

Gate structure in the substrate；

Positioned at the intrabasement source and drain doping area in the gate structure both sides；

Expose the dielectric layer in substrate positioned at gate structure, the dielectric layer covers the source and drain doping area；

Plug in the source and drain doping area, the plug run through the dielectric layer；

Metal oxide layer between the plug and the source and drain doping area.

16. semiconductor structure as claimed in claim 15, which is characterized in that the material of the metal oxide layer be titanium oxide, Cobalt oxide or nickel oxide.

17. semiconductor structure as claimed in claim 15, which is characterized in that the thickness of the metal oxide layer is less than 5nm.

18. semiconductor structure as claimed in claim 15, which is characterized in that the material of the plug is titanium or tungsten.

19. semiconductor structure as claimed in claim 15, which is characterized in that the semiconductor structure is fin field effect crystal Pipe；

The substrate includes substrate and the fin on the substrate；

The gate structure is across the fin and on the surface of the fin atop part and partial sidewall；

The semiconductor structure further includes：Stressor layers in the fin of the gate structure both sides, the stressor layers are used for shape At the source and drain doping area；

The plug is located in the stressor layers；

The metal oxide layer is located at least between the stressor layers and the plug.

20. semiconductor structure as claimed in claim 19, which is characterized in that the semiconductor structure is N-type transistor, described The material of stressor layers is silicon or carbon silicon；

The semi-conducting material is P-type transistor, and the material of the stressor layers is silicon or germanium silicon.