CN106533438A - Terahertz frequency synthesizer realized by adopting CMOS process - Google Patents

Abstract

A terahertz frequency synthesizer realized by CMOS technology, including: a voltage-controlled oscillator for generating a terahertz LO signal, a first-stage injection-locked frequency divider for frequency division, and a second-stage injection A locked frequency divider, and a phase-locked loop for locking the set frequency, the feedback output of the phase-locked loop is connected to the feedback input of the voltage-controlled oscillator. A terahertz frequency synthesizer implemented by a CMOS process of the present invention is implemented by a standard CMOS process, and has the advantages of high integration, low cost, and easy mass production. At the same time, it also overcomes the limitation of poor working performance near the cutoff frequency of CMOS technology, and realizes the design of a terahertz frequency synthesizer.

Description

A Terahertz Frequency Synthesizer Realized by CMOS Technology

technical field

The invention relates to a terahertz frequency synthesizer. In particular, it relates to a terahertz frequency synthesizer realized by CMOS technology.

Background technique

In recent years, high-speed wireless communication systems are constantly developing towards higher frequency, bandwidth, higher integration and lower cost. The terahertz frequency band (300GHz-3THz) is between microwaves and infrared rays. It is the only last spectrum interval in the electromagnetic spectrum that has not been fully studied and well utilized. Today, when communication frequency bands are increasingly scarce, the use of terahertz wave communication Technical research is of great significance. Terahertz wave communication technology is widely used in all aspects of life. Due to its unique properties and position in the spectrum, terahertz waves are widely used in communications, electronic countermeasures, radar, electromagnetic weapons, astronomy, medical imaging, non-destructive testing, There are broad application prospects in the fields of environmental monitoring and safety inspection.

In recent years, with the continuous reduction of feature size, the characteristic frequency of deep submicron CMOS technology and its MOSFET has reached more than 200 GHz, making it possible to use CMOS technology to realize high-frequency analog circuits in the GHz band. Among many processes such as silicon CMOS, BiCMOS, bipolar process, GaAs MESFET, heterojunction bipolar transistor (HBT), GeSi device, etc., although the high frequency performance and noise performance of silicon CMOS are not the best, because its process is the most Mature, the lowest cost, the smallest power consumption, and the most widely used, so CMOS radio frequency integrated circuits are the development trend in recent years. With the development of radio frequency identification technology, researchers from all over the world have done a lot of research on the design and production of CMOS radio frequency integrated circuits, which has continuously improved the performance of CMOS radio frequency integrated circuits. With the advancement of silicon-based technology, silicon-based technology can support the realization of terahertz communication integrated circuits, but the working frequency band up to hundreds of GHz makes the realization of terahertz communication integrated circuits face a series of challenges.

The reason why traditional digital CMOS process technology has not been fully considered in the application of ultra-high frequency circuits (frequency exceeding 100GHz) is that the CMOS oscillator circuit is limited by the cut-off frequency (f _T ) and maximum oscillation frequency (f _max ) of the device . However, with the development of process technology, the size of the device is continuously reduced, and the operating frequency of the device is continuously increased, so that the cut-off frequency of the field effect transistor can be close to or even reach the frequency range of terahertz under the CMOS process, so that the CMOS process can be used to realize the frequency range of the terahertz wave. It is possible to work under the circuit.

The terahertz wave circuit realized by CMOS process has been studied, but because of the CMOS process device.

Contents of the invention

The technical problem to be solved by the present invention is to provide a terahertz frequency synthesizer realized by CMOS technology with high integration, low cost and easy mass production

The technical solution adopted in the present invention is: a terahertz frequency synthesizer realized by CMOS technology, including a voltage-controlled oscillator that generates a terahertz LO signal connected in series, and a first-stage injection for frequency division A locked frequency divider and a second-stage injection locked frequency divider, and a phase locked loop for locking the set frequency, the feedback output of the phase locked loop is connected to the feedback input of the voltage controlled oscillator .

The voltage-controlled oscillator includes a first MOS transistor, a second MOS transistor, a first resistor, and a second resistor, wherein the gate of the first MOS transistor is connected to the second MOS transistor through a third inductance and a fourth inductance in sequence. The gate of the MOS transistor, the gate of the first MOS transistor is also connected to one end of the variable capacitor and one end of the fifth inductor through the third capacitor and the source, and the drain of the first MOS transistor is connected to the first end of the MOS transistor through the first The inductance is connected to the power supply, and the positive pole of the output terminal is connected to the input terminal of the first-stage injection-locked frequency divider through the first capacitor, and the gate of the second MOS transistor is also connected to the variable capacitor through the fourth capacitor and the source. The other end of the second MOS transistor and one end of the sixth inductance, the drain of the second MOS transistor is connected to the power supply through the second inductance, and the negative electrode of the output end is connected to the input end of the first-stage injection-locked frequency divider through the second capacitor, so The connection ends of the third inductance and the fourth inductance are grounded sequentially through the first resistor and the bias voltage, the other end of the fifth inductance and the other end of the sixth inductance are connected to one end of the second resistor and the fifth capacitor, the The other ends of the second resistor and the fifth capacitor are grounded.

The first-stage injection-locked frequency divider includes a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor, wherein the third MOS transistor The gate is connected to an external power supply, the source and drain of the third MOS transistor are respectively connected to tap a and tap c on the ninth inductance, the gate of the fourth MOS transistor is connected to tap b in the middle of the ninth inductance, and constitute The input terminal (Prot1) is connected to the output terminal of the voltage-controlled oscillator, and the source of the fourth MOS transistor is respectively connected to one end of the ninth inductor, the grid of the fifth MOS transistor, the drain of the seventh MOS transistor, and the drain of the fourth MOS transistor. The gates of the eight MOS transistors and the drain of the fourth MOS transistor are respectively connected to the other end of the ninth inductor, the gate of the sixth MOS transistor, the drain of the eighth MOS transistor, and the gate of the seventh MOS transistor. The sources of the MOS transistor and the eighth MOS transistor are grounded through the first current source, the sources of the fifth MOS transistor and the sixth MOS transistor are grounded through the second current source, and the drains of the fifth MOS transistor are connected through the seventh inductance A power supply, and an output end connected to the input end of the second-stage injection-locked frequency divider, the drain of the sixth MOS transistor is connected to the power supply through the eighth inductor.

The second-stage injection-locked frequency divider includes a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor and a transformer, wherein the gate of the eleventh MOS transistor constitutes an input terminal connected to the first The output terminal of the first-stage injection-locked frequency divider, the source and drain of the eleventh MOS tube are respectively connected to the two ends of the primary coil of the transformer, and one end of the secondary coil of the transformer constitutes the positive pole or negative pole of the output terminal connected to the The input terminal of the phase-locked loop, which is also connected to the drain of the ninth MOS transistor and the gate of the tenth MOS transistor, the other end of the secondary coil of the transformer constitutes the negative pole of the output terminal or the positive pole is connected to the gate of the phase-locked loop The input terminal is connected to the drain of the tenth MOS transistor and the gate of the ninth MOS transistor respectively, and the sources of the ninth MOS transistor and the tenth MOS transistor are grounded.

A terahertz frequency synthesizer implemented by a CMOS process of the present invention is implemented by a standard CMOS process, and has the advantages of high integration, low cost, and easy mass production. At the same time, it also overcomes the limitation of poor working performance near the cutoff frequency of CMOS technology, and realizes the design of a terahertz frequency synthesizer. The present invention has the following advantages:

1. The wavelength of THz wave is between microwave and infrared light. Its interaction with matter has a unique physical mechanism and presents many new features. Since the terahertz wave in the 0.3THz-10THz frequency band can strongly penetrate substances such as plastic, paper, wood, human body, atmosphere, etc., it can be widely used in security scanning, radio astronomy, biological remote sensing, production monitoring and other fields , the specific classification can include mail scanning, paper production, plastic welding inspection, ancient painting analysis, human body perspective, food quality inspection, skin cancer classification, etc.

2. The frequency synthesizer can work at the terahertz frequency, and can overcome the frequency limitation caused by the frequency close to the cut-off frequency of the device, so that the output frequency can be increased above the actual operating frequency of the device.

3. Compared with the traditional circuit, the power consumption and size of the design are significantly improved.

In summary, the power amplifier structure and implementation method proposed by the present invention have good application prospects.

Description of drawings

Fig. 1 is a block diagram of the composition of a terahertz frequency synthesizer realized by CMOS technology in the present invention;

Fig. 2 is the circuit schematic diagram of voltage-controlled oscillator in the present invention;

Fig. 3 is the circuit schematic diagram of the first-stage injection-locked frequency divider in the present invention;

Fig. 4 is a schematic circuit diagram of the second-stage injection-locked frequency divider in the present invention.

detailed description

A terahertz frequency synthesizer implemented by a CMOS process of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.

A terahertz frequency synthesizer implemented by a CMOS process of the present invention is composed of a terahertz voltage-controlled oscillator, ILFDs and a frequency divider chain. Among them, the voltage-controlled oscillator is used to obtain the output signal satisfying the terahertz frequency; the subsequent ILFDs (injection locking frequency dividers) and frequency divider chain adjust the signal to the appropriate frequency. Its rear end is locked independently by a phase-locked loop in frequency and phase.

Due to the limitation of the cut-off frequency and the maximum oscillation frequency of the CMOS process, it is determined that the performance of active devices is greatly deteriorated or cannot work normally at frequencies close to or exceeding the cut-off frequency. However, the terahertz frequency band is still above the cut-off frequency of the CMOS process, so active devices in integrated circuits of the CMOS process cannot be directly applied to the terahertz frequency band. In the present invention, the fundamental frequency signal is separated by power, and the multi-channel signal paths respectively pass through the power amplifier, and the generated power amplified signal is frequency-multiplied by passive devices, and no longer passes through active devices after frequency multiplication, and the even-order harmonic frequency will be obtained The signal is directly subjected to power combination and impedance transformation, thereby avoiding the deterioration of the performance of the active device at an excessively high operating frequency, and finally obtaining an output signal in the terahertz frequency band.

As shown in Fig. 1, a kind of terahertz frequency synthesizer realized by CMOS technology of the present invention includes: a voltage-controlled oscillator 1 generating a terahertz LO signal connected in series, and a first stage for frequency division An injection-locked frequency divider 2 and a second-stage injection-locked frequency divider 3, and a phase-locked loop 4 for locking to a set frequency, the feedback output of the phase-locked loop 4 is connected to the voltage-controlled oscillation Feedback input of device 1.

First, a terahertz LO signal is generated by a voltage-controlled oscillator, and the adjustable frequency range of the oscillator output is 118.6GHz to 121GHz. Then the signal enters the first-stage injection-locked frequency divider, the second-stage injection-locked frequency divider and the frequency divider chain for frequency division, and finally enters the phase-locked loop to lock to the desired frequency. The present invention finally achieves a frequency of 21GHz, a phase noise of -74dBc/Hz at 1MHz, and a DC power consumption of 174mW.

As shown in FIG. 2, the voltage-controlled oscillator 1 includes a first MOS transistor M1, a second MOS transistor M2, a first resistor R1, and a second resistor R2, wherein the gate of the first MOS transistor M1 The gate of the second MOS transistor M2 is connected sequentially through the third inductance L3 and the fourth inductance L4, and the gate of the first MOS transistor M1 is also connected to one end and the source of the variable capacitor C6 through the third capacitor C3 and the source, respectively. One end of the fifth inductor L5, the drain of the first MOS transistor M1 is connected to the power supply VDD through the first inductor L1, and the input of the first-stage injection-locked frequency divider 2 is connected to the positive electrode Prot1 of the output terminal through the first capacitor C1 terminal, the gate of the second MOS transistor M2 is also connected to the other end of the variable capacitor C6 and one end of the sixth inductor L6 through the fourth capacitor C4 and the source, and the drain of the second MOS transistor M2 is connected through The second inductor L2 is connected to the power supply VDD, and is connected to the input terminal of the first-stage injection-locked frequency divider 2 through the second capacitor C2 to the negative electrode Prot1 of the output terminal, and the connection terminals of the third inductor L3 and the fourth inductor L4 are sequentially passed through The first resistor R1 and the bias voltage V1 are grounded, the other end of the fifth inductance L5 and the other end of the sixth inductance L6 are connected to the second resistor R2 and one end of the fifth capacitor C5, the second resistor R2 and the fifth capacitor C5 The other end of the capacitor C5 is grounded.

The DC bias is mainly determined by the first MOS transistor M1, the second MOS transistor M2, the first resistor R1, the second resistor R2, the bias voltage V1 and the resistor R2, the value of the first resistor R1 should be as small as possible, on the one hand It can reduce voltage fluctuations. On the other hand, this resistor can be regarded as a resistor connected in series with the inductor. A larger resistance value will deteriorate the Q value of the inductor and affect the phase noise performance of the circuit. The role of the second resistor R2 is equivalent to a current Source, on the one hand, it needs to establish a DC bias, and at the same time, it must ensure that the noise introduced by it cannot be too large, so the selection of the resistance value of the second resistor R2 also needs to be compromised according to the performance requirements. After design simulation, the first resistor R1 and the second resistor R2 should be 20Ω and 52Ω respectively. Compared with the traditional design, this method can obtain a wider tuning range at the predetermined fundamental frequency and can reduce the deterioration of the quality factor Q.

The voltage-controlled oscillator in the previous part may produce DC voltage mismatch, so it is necessary to add the first-stage injection-locked frequency divider 2 and the second-stage injection-locked frequency divider 3 to solve this problem.

As shown in FIG. 3, the first-stage injection-locked frequency divider 2 includes a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7 and The eighth MOS transistor M8, wherein the gate of the third MOS transistor M3 is connected to the external power supply Vsw2, and the source and drain of the third MOS transistor M3 are respectively connected to the a tap and the c tap on the ninth inductor L9. The gates of the four MOS transistors M4 are connected to the tap b in the middle of the ninth inductor L9, and the input end Prot1 is connected to the output end of the voltage-controlled oscillator 1, and the sources of the fourth MOS transistor M4 are respectively connected to the ninth inductor L9. One end, the gate of the fifth MOS transistor M5, the drain of the seventh MOS transistor M7, and the gate of the eighth MOS transistor M8, and the drain of the fourth MOS transistor M4 are respectively connected to the other end of the ninth inductor L9, the sixth The gate of the MOS transistor M6, the drain of the eighth MOS transistor M8, and the gate of the seventh MOS transistor M7, the sources of the seventh MOS transistor M7 and the eighth MOS transistor M8 are grounded through the first current source I1, the The sources of the fifth MOS transistor M5 and the sixth MOS transistor M6 are grounded through the second current source I2, the drain of the fifth MOS transistor M5 is connected to the power supply VDD through the seventh inductance L7, and the output terminal Prot2 is connected to the second injection stage. The input terminal of the frequency divider 3 is locked, and the drain of the sixth MOS transistor M6 is connected to the power supply VDD through the eighth inductor L8.

The first-stage injection-locked frequency divider 2 receives the output given by the previous voltage-controlled oscillator, in which the resonant inductor L9 controls the frequency error within 1GHz. Since the operating frequency of the frequency divider is low (94GHz), the resonant inductor The inductance value of L9 should be controlled at 120pH, and the quality factor Q also needs to be controlled within an acceptable range.

As shown in FIG. 4, the second-stage injection-locked frequency divider 3 includes a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11 and a transformer T, wherein the eleventh MOS The gate of the tube M11 forms an input terminal Prot2 connected to the output terminal of the first-stage injection-locked frequency divider 2, and the source and drain of the eleventh MOS tube M11 are respectively connected to both ends of the primary coil of the transformer T, so One end of the secondary coil of the transformer T constitutes the positive or negative pole of the output terminal Prot3 connected to the input terminal of the phase-locked loop 4, and this terminal is also connected to the drain of the ninth MOS transistor M9 and the grid of the tenth MOS transistor M10, The other end of the secondary coil of the transformer T constitutes the output terminal Prot3. The negative pole or the positive pole is connected to the input terminal of the phase-locked loop 4, and this terminal is also connected to the drain of the tenth MOS transistor M10 and the gate of the ninth MOS transistor M9 respectively. The source electrodes of the ninth MOS transistor M9 and the tenth MOS transistor M10 are grounded.

The second-stage injection-locked frequency divider 3 is used to divide the terahertz signal output by the first-stage injection-locked frequency divider 2 by 1/12.

Claims (4)

1. A terahertz frequency synthesizer that adopts CMOS technology to realize, is characterized in that, comprises and is connected in series successively: the voltage-controlled oscillator (1) that produces terahertz LO signal, is used for carrying out the first stage injection of frequency division A locked frequency divider (2) and a second-stage injection locked frequency divider (3), and a phase-locked loop (4) for locking to a set frequency, the feedback output of the phase-locked loop (4) The terminal is connected to the feedback input terminal of the voltage-controlled oscillator (1). 2. A terahertz frequency synthesizer realized by a CMOS process according to claim 1, wherein said voltage-controlled oscillator (1) includes a first MOS transistor (M1), a second MOS transistor (M2), the first resistor (R1) and the second resistor (R2), wherein, the gate of the first MOS transistor (M1) is connected to the second resistor through the third inductor (L3) and the fourth inductor (L4) in turn The gate of the MOS transistor (M2), the gate of the first MOS transistor (M1) is also connected to one end of the variable capacitor (C6) and the fifth inductor (L5) through the third capacitor (C3) and the source respectively One end of the first MOS transistor (M1), the drain of the first MOS transistor (M1) is connected to the power supply (VDD) through the first inductor (L1), and is connected to the first stage of injection locking through the first capacitor (C1) to the positive pole of the output terminal (Prot1) The input terminal of the frequency divider (2), the gate of the second MOS transistor (M2) is also connected to the other end of the variable capacitor (C6) and the sixth inductance ( One end of L6), the drain of the second MOS transistor (M2) is connected to the power supply (VDD) through the second inductor (L2), and connected to the first stage through the second capacitor (C2) to the negative pole of the output terminal (Prot1) Injection into the input terminal of the locking frequency divider (2), the connection terminal of the third inductance (L3) and the fourth inductance (L4) are grounded sequentially through the first resistor (R1) and the bias voltage (V1), and the first The other end of the fifth inductance (L5) and the other end of the sixth inductance (L6) are connected to one end of the second resistor (R2) and the fifth capacitor (C5), and the second resistor (R2) and the fifth capacitor (C5) The other end of the ground. 3. A terahertz frequency synthesizer realized by a CMOS process according to claim 1, wherein said first-stage injection-locked frequency divider (2) includes a third MOS transistor (M3), The fourth MOS transistor (M4), the fifth MOS transistor (M5), the sixth MOS transistor (M6), the seventh MOS transistor (M7) and the eighth MOS transistor (M8), wherein the third MOS transistor (M3) The gate is connected to an external power supply (Vsw2), the source and drain of the third MOS transistor (M3) are respectively connected to tap a and tap c on the ninth inductor (L9), and the gate of the fourth MOS transistor (M4) The pole is connected to the tap b in the middle of the ninth inductor (L9), and the input terminal (Prot1) is connected to the output terminal of the voltage-controlled oscillator (1), and the source of the fourth MOS transistor (M4) is respectively connected to the ninth inductor One end of (L9), the gate of the fifth MOS transistor (M5), the drain of the seventh MOS transistor (M7), the gate of the eighth MOS transistor (M8), the drain of the fourth MOS transistor (M4) Respectively connect the other end of the ninth inductor (L9), the gate of the sixth MOS transistor (M6), the drain of the eighth MOS transistor (M8), and the gate of the seventh MOS transistor (M7), the seventh MOS transistor (M7) and the source of the eighth MOS transistor (M8) are grounded through the first current source (I1), and the sources of the fifth MOS transistor (M5) and the sixth MOS transistor (M6) are connected through the second current source ( I2) is grounded, the drain of the fifth MOS transistor (M5) is connected to the power supply (VDD) through the seventh inductance (L7), and the output end (Prot2) is connected to the input end of the second-stage injection-locked frequency divider (3) , the drain of the sixth MOS transistor (M6) is connected to the power supply (VDD) through the eighth inductor (L8). 4. A terahertz frequency synthesizer realized by CMOS technology according to claim 1, characterized in that, said second-stage injection-locked frequency divider (3) includes a ninth MOS transistor (M9), The tenth MOS transistor (M10), the eleventh MOS transistor (M11) and the transformer (T), wherein the gate of the eleventh MOS transistor (M11) forms an input terminal (Prot2) connected to the first-stage injection Lock the output terminal of the frequency divider (2), the source and the drain of the eleventh MOS tube (M11) are respectively connected to the two ends of the primary coil of the transformer (T), and one end of the secondary coil of the transformer (T) The positive pole or negative pole constituting the output terminal (Prot3) is connected to the input terminal of the phase-locked loop (4), and this terminal is also respectively connected to the drain of the ninth MOS transistor (M9) and the gate of the tenth MOS transistor (M10), The other end of the secondary coil of the transformer (T) constitutes the negative or positive pole of the output terminal (Prot3) connected to the input terminal of the phase-locked loop (4), and this terminal is also connected to the drain of the tenth MOS tube (M10) respectively and the gate of the ninth MOS transistor (M9), the sources of the ninth MOS transistor (M9) and the tenth MOS transistor (M10) are grounded.