CN211296713U - A broadband injection-locked divide-by-four with transformer-coupled divide-by-three - Google Patents

Abstract

The utility model discloses a broadband injection locking that contains transformer coupling and removes three frequency divisions removes four dividers, including first inductance, second inductance, third inductance, fourth inductance, fifth inductance, sixth inductance, power VDD, first resistance, second resistance, first electric capacity, second electric capacity, third electric capacity, fourth electric capacity, fifth electric capacity, first NMOS pipe, second NMOS pipe, third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, first bias voltage and second bias voltage etc.; the positive ends of the first inductor and the second inductor are both connected with a power supply VDD, and the two ends of the first resistor are respectively connected with the negative ends of the first inductor and the second inductor; the first capacitor is connected with the negative end of the first inductor, and the other end of the first capacitor is grounded; the second capacitor is connected with the negative end of the first inductor, and the other end of the second capacitor is grounded. The utility model discloses signal injection efficiency has been increased to realize that the broadband removes the four frequency division, reduces output signal third harmonic intensity.

Description

A broadband injection-locked divide-by-four with transformer-coupled divide-by-three

technical field

The utility model relates to the field of millimeter-wave front-end circuits of electronic communication technology, and provides a wideband injection-locked divide-by-four frequency divider including a transformer-coupled divide-by-three technology.

Background technique

In recent years, many industry and academic research institutions have turned their research focus to fifth-generation (5G) communications. The millimeter-wave front-end circuit is an important part of the 5G communication system. One of the keys is that the phase-locked loop closely follows the voltage-controlled oscillator. The first stage of the divider - the study of the injection-locked divider. The frequency divider works at the highest frequency in the phase-locked loop module. It needs to track the frequency of the oscillator and divide it. The most important performance indicator of the injection-locked frequency divider is the input signal bandwidth.

Among the existing solutions, [Wu L, Luong H C. Analysis and design of a 0.6 V 2.2mW 58.5-to-72.9 GHz divide-by-4 injection-locked frequency divider withharmonic boosting[J]. IEEE Transactions on Circuits and Systems I: RegularPapers, 2013, 60(8): 2001-2008. ] proposed a third-harmonic enhanced divide-by-four frequency divider with an input frequency range of 58.5-72.9 GHz and a relative bandwidth of 21.3%; [Jang S L, Fu C C. Wide locking rangedivide-by-4 LC-tank injection-locked frequency divider using series-mixers[J]. Analog Integrated Circuits and Signal Processing, 2014, 78(2): 523-528.] A divide-by-four using a series mixer was published in , with an input frequency range of 9.9-12.5 GHz and a relative bandwidth of 23.2%; [Garghetti A, Lacaita A L, Levantino S. A Single-Inductor Two-Step-Mixing Injection -Locked Frequency Divider by Four with Concurrent Tail-Injection[C]//2018 25th IEEE International Conference on Electronics,Circuits and Systems (ICECS). IEEE, 2018: 349-352.] A dual tail parallel injection was proposed The step-mixer divide-by-four has a center frequency of 20GHz and a relative bandwidth of 22.2%. This type of frequency divider is suitable for millimeter wave communication front-end circuits. The frequency division bandwidth of the above frequency dividers is not large enough, and the relative bandwidth does not exceed 25%. The output port contains a strong third harmonic, and the power consumption is too large, which is not suitable for the circuit in the terminal equipment.

Utility model content

The purpose of the utility model is to solve the problem of increasing the bandwidth of the input signal and reducing the third harmonic at the output end of the circuit for subsequent filtering.

The present invention is realized by at least one of the following technical solutions.

A broadband injection-locked frequency divider by 3 including transformer-coupled frequency division by 3, comprising a first inductance L ₁₊ , a second inductance L _1- , a third inductance L ₂₊ , a fourth inductance L _2- , a fifth inductance L 2- , a Inductor L ₃₊ , sixth inductance L _3- , power supply VDD, first resistor R _p , second resistor R ₁ , first capacitor C ₁₊ , second capacitor C _1- , third capacitor C ₂₊ , fourth Capacitor C _2- , fifth capacitor C _in , first NMOS transistor M ₁ , second NMOS transistor M ₂ , third NMOS transistor M ₃ , fourth NMOS transistor M ₄ , fifth NMOS transistor M ₅ , sixth NMOS transistor M ₆ , a seventh NMOS transistor M ₇ , a first bias voltage VB ₁ and a second bias voltage VB ₂ ;

The positive terminals of the first inductor L ₁₊ and the second inductor L _1- are both connected to the power supply VDD, and the two ends of the first resistor R _p are respectively connected to the negative terminals of the first inductor L ₁₊ and the second inductor L _1- ; The first capacitor C ₁₊ is connected to the negative end of the first inductor L ₁₊ , the other end of the first capacitor C ₁₊ is grounded; the second capacitor C _1- is connected to the negative end of the second inductor L _1- , and the second capacitor C _{1 -The} other end is grounded; the positive ends of the third inductor L ₂₊ and the fourth inductor L _2- are respectively connected to the negative ends of the first inductor L ₁₊ and the second inductor L _1- ; the third capacitor C ₂₊ is connected to the third inductor The negative end of L ₂₊ , the other end of the third capacitor C ₂₊ is grounded; the fourth capacitor C _2- is connected to the negative end of the fourth inductor L _2- , and the other end of the fourth capacitor C _2- is grounded;

The positive terminals of the fifth inductor L ₃₊ and the sixth inductor L _3- are respectively connected to the gates of the fourth NMOS transistor M ₄ and the fifth NMOS transistor M ₅ , and the negative terminals of the fifth inductor L ₃₊ and the sixth inductor L _3- The terminals are all connected to the _second bias voltage VB2; the source of the _fourth NMOS transistor M4 is connected to the source of the _fifth NMOS transistor M5, and the drain of the _fourth NMOS transistor M4 is connected to the negative of the third inductor L2 ₊ terminal, the drain of the fifth NMOS transistor M5 is connected to the negative terminal of the fourth inductor _L2- ; the source and drain of the _third NMOS transistor M3 are respectively connected to the _fourth NMOS transistor M4 and the _fifth NMOS transistor _M5 drain;

One end of the second resistor R ₁ is connected to the first bias voltage VB ₁ , the other end of the second resistor R ₁ is connected to the gate of M ₃ ; one end of the fifth capacitor C _in is connected to the gate of the third NMOS transistor M ₃ , and the fifth capacitor C The other end of _in is connected to the input signal IN; the sources of the _first NMOS transistor M1 and the second NMOS transistor _M2 are grounded, the gate of the _first NMOS transistor M1 is connected to the drain of the _second NMOS transistor M2, and the first NMOS transistor M2 _The drain of M1 is connected to the drain of the _third NMOS transistor M3, the gate of the _second NMOS transistor M2 is connected to the drain of the _first NMOS transistor M1, and the drain of the _second NMOS transistor M2 is connected to the third NMOS transistor _The source of M3;

The gate of the _sixth NMOS transistor M6 is connected to the drain of the _fourth NMOS transistor M4, the source of the _sixth NMOS transistor M6 is grounded, and the drain of the _sixth NMOS transistor M6 is open-drain output; the _seventh NMOS transistor M7 The gate is connected to the drain of the _fifth NMOS transistor M5, the source of the _seventh NMOS transistor M7 is grounded, and the drain of the _seventh NMOS transistor M7 is open-drain output.

Further, the positive terminals of the third inductor L ₂₊ and the fourth inductor L _2- are respectively coupled with the positive terminals of the fifth inductor L ₃₊ and the sixth inductor L _3- , and the coupling coefficients are both k.

Further, the positive terminal of the third inductor L ₂₊ is coupled with the positive terminal of the fifth inductor L ₃₊ to form a first transformer T ₁ ; the positive terminal of the fourth inductor L _2- and the positive terminal of the sixth inductor L _3- coupled to form a second transformer T ₂ ; the coupling coefficients of the first transformer T ₁ and the second transformer T ₂ are both k.

Further, the first inductor L ₁₊ , the second inductor L _1- , the first capacitor C ₁₊ , the second capacitor C _1- , the second resistor R _p , the first transformer T1 and the second transformer T2 constitute a resonator.

Further, the impedance of the resonator has two peaks, and the corresponding center frequencies are ω and 3ω respectively, and the corresponding impedance amplitude at the 3ω frequency is smaller than the corresponding impedance amplitude at the ω frequency to ensure that the oscillator oscillation frequency is ω.

Further, the oscillator is mainly composed of a resonator, a _first NMOS transistor M1 and a second NMOS transistor _M2 .

Further, the frequency of the input signal IN is ω _in (ω _in =4ω), and is injected into the gate of the third NMOS transistor M ₃ through the AC coupling of the capacitor C _in . The working principle of the third NMOS transistor M ₃ is as in the Drain-Pumped mixer ( Drain mixer), the input signal IN is mixed with the oscillator output signal, and the frequency change process is ω _in -3ω = ω and ω _in - ω = 3ω, but the oscillator oscillation frequency is ω, so the circuit realizes four divisions frequency, and the output signal contains the third harmonic.

Further, the _fourth NMOS transistor M4 and the _fifth NMOS transistor M5 are differential floating source injection transistors. During the operation of the circuit, the common-mode point of the positive and negative output terminals of the oscillator with a frequency of ω is the CM point, and the CM point signal contains the 2ω frequency;

Further, the third harmonic of the differential output terminal of the oscillator is coupled to the gates of the _fourth NMOS transistor M4 and the _fifth NMOS transistor M5 by the _first transformer T1 and the _second transformer T2; the _fourth NMOS transistor M4 and The 3ω frequency component signal of the gate of the _fifth NMOS transistor M5 is mixed with the 2ω frequency component signal of the CM point, and the frequency change process is 3ω - 2ω = ω and 3ω + 2ω = 5ω; and 5ω frequency signal output, but the oscillator oscillates at the frequency ω, so the 5ω frequency component is filtered out by the resonator, and the frequency division by three is realized.

The frequency division by 4 and the frequency by 3 occur simultaneously, and the signals with the frequency ω obtained by the two frequency divisions are finally superimposed together after being filtered by the resonator and then enter the open-drain output buffer stage. On the basis of dividing the frequency divider by four, the utility model introduces three frequency division and adds one frequency division; the original one frequency division becomes two frequency division, so the signal injection efficiency is improved, and the whole frequency division is improved. The input signal bandwidth of the circuit.

Compared with the prior art, the beneficial effects of the present utility model are as follows: the utility model utilizes the third harmonic frequency component originally to be filtered out at the output end to divide the frequency by three on the basis of the published frequency divider by four, and Divide by four and divide by three in the same circuit. For these two frequency divisions, the main division is divided by 4, and the secondary division is divided by 3. The combined effect of the two frequency divisions significantly increases the input signal bandwidth of the entire circuit. At 0dBm power injection, the frequency range is 22.8-32.4 GHz, the center frequency is 27.6 GHz, and the bandwidth reaches 34.8%. At present, the frequency band range of 5G communication system widely used by domestic and foreign research institutions is 24.25-29.5 GHz, so the operating frequency range of the utility model can completely cover the frequency band of 5G communication, and can be used for the first stage of the phase-locked loop of the 5G communication front-end circuit. frequency division.

In addition to increasing the circuit bandwidth, because a part of the third harmonic of the output terminal is coupled to the gates of the _third NMOS transistor M3 and the _fourth NMOS transistor M4 by the _first transformer T1 and the _second transformer T2 to divide the frequency by three, The utility model also reduces the intensity of the third harmonic of the output signal, so the filtering of the output signal will be more thorough, or the suppression ratio of the third harmonic of the output signal will be higher. In the case of no filtering at the output, the ratio of the output signal of the oscillator after the open-drain output buffer stage and the third harmonic of the output of the oscillator at different input frequencies can reach about 8dB at the minimum and close to 22dB at the maximum.

Description of drawings

1 is a schematic diagram of a utility model of a broadband injection-locked divide-by-four that includes a transformer-coupled divide-by-three frequency divider;

Fig. 2 is the impedance amplitude curve diagram of the resonator of the present utility model;

Fig. 3 is the input signal sensitivity curve diagram of the present utility model;

FIG. 4 is a diagram showing the ratio of the output signal and the third harmonic of the present utility model under different input frequencies.

Detailed ways

The present utility model will be described in further detail below with reference to the embodiments and the accompanying drawings, but the embodiments of the present utility model are not limited thereto.

A broadband injection-locked frequency divider including transformer-coupled divide-by-three, as shown in FIG. 1 , includes a first inductor L ₁₊ , a second inductor L _1- , a third inductor L ₂₊ , and a fourth inductor L _2- , fifth inductor L ₃₊ , sixth inductor L _3- , power supply VDD, first resistor R _p , second resistor R ₁ , first capacitor C ₁₊ , second capacitor C _1- , third capacitor C ₂₊ , fourth capacitor C _2- , fifth capacitor C _in , first NMOS transistor M ₁ , second NMOS transistor M ₂ , third NMOS transistor M ₃ , fourth NMOS transistor M ₄ , fifth NMOS transistor M _5. The sixth NMOS transistor M ₆ , the seventh NMOS transistor M ₇ , the first bias voltage VB ₁ and the second bias voltage VB ₂ .

The positive terminals of the first inductor L ₁₊ and the second inductor L _1- are both connected to the power supply VDD, and the two ends of the first resistor R _p are respectively connected to the negative terminals of the first inductor L ₁₊ and the second inductor L _1- ; The first capacitor C ₁₊ is connected to the negative end of the first inductor L ₁₊ , the other end of the first capacitor C ₁₊ is grounded; the second capacitor C _1- is connected to the negative end of the second inductor L _1- , and the second capacitor C _{1 -The} other end is grounded; the positive ends of the third inductor L ₂₊ and the fourth inductor L _2- are respectively connected to the negative ends of the first inductor L ₁₊ and the second inductor L _1- ; the third capacitor C ₂₊ is connected to the third inductor The negative terminal of L ₂₊ , the other terminal of the third capacitor C ₂₊ is grounded; the fourth capacitor C _2- is connected to the negative terminal of the fourth inductor L _2- , and the other terminal of the fourth capacitor C _2- is grounded.

The positive terminal of the third inductor L ₂₊ is coupled with the positive terminal of the fifth inductor L ₃₊ to form a first transformer T ₁ ; the positive terminal of the fourth inductor L _2- is coupled to the positive terminal of the sixth inductor L _3- to form a first transformer T 1 . The second transformer T ₂ ; the coupling coefficients of the first transformer T ₁ and the second transformer T ₂ are both k.

The first inductor L ₁₊ , the second inductor L _1- , the first capacitor C ₁₊ , the second capacitor C _1- , the second resistor R _p , the first transformer T1 and the second transformer T2 are combined into a resonator.

The positive terminals of the fifth inductor L ₃₊ and the sixth inductor L _3- are respectively connected to the gates of the fourth NMOS transistor M ₄ and the fifth NMOS transistor M ₅ , and the negative terminals of the fifth inductor L ₃₊ and the sixth inductor L _3- The terminals are all connected to the _second bias voltage VB2; the source of the _fourth NMOS transistor M4 is connected to the source of the _fifth NMOS transistor M5, and the drain of the _fourth NMOS transistor M4 is connected to the negative of the third inductor L2 ₊ terminal, the drain of the fifth NMOS transistor M5 is connected to the negative terminal of the fourth inductor _L2- ; the source and drain of the _third NMOS transistor M3 are respectively connected to the _fourth NMOS transistor M4 and the _fifth NMOS transistor _M5 drain.

One end of the second resistor R ₁ is connected to the first bias voltage VB ₁ , the other end of the second resistor R ₁ is connected to the gate of M ₃ ; one end of the fifth capacitor C _in is connected to the gate of the third NMOS transistor M ₃ , and the fifth capacitor C The other end of _in is connected to the input signal IN; the sources of the _first NMOS transistor M1 and the second NMOS transistor _M2 are grounded, the gate of the _first NMOS transistor M1 is connected to the drain of the _second NMOS transistor M2, and the first NMOS transistor M2 _The drain of M1 is connected to the drain of the _third NMOS transistor M3, the gate of the _second NMOS transistor M2 is connected to the drain of the _first NMOS transistor M1, and the drain of the _second NMOS transistor M2 is connected to the third NMOS transistor _The source of M3.

The gate of the _sixth NMOS transistor M6 is connected to the drain of the _fourth NMOS transistor M4, the source of the _sixth NMOS transistor M6 is grounded, and the drain of the _sixth NMOS transistor M6 is open-drain output; the _seventh NMOS transistor M7 The gate is connected to the drain of the _fifth NMOS transistor M5, the source of the _seventh NMOS transistor M7 is grounded, and the drain of the _seventh NMOS transistor M7 is open-drain output.

The positive terminals of the third inductor L ₂₊ and the fourth inductor L _2- are respectively coupled with the positive terminals of the fifth inductor L ₃₊ and the sixth inductor L _3- , and the coupling coefficients are both k.

The third inductor L ₂₊ and the fifth inductor L ₃₊ form a first transformer T ₁ , and the fourth inductor L _2- and the sixth inductor L _3- form a transformer second transformer T ₂ .

As shown in Figure 2, the resonator impedance has two peaks, and the corresponding center frequencies are ω (7GHz) and 3ω (21GHz). The corresponding impedance amplitude at the 3ω frequency is smaller than the corresponding impedance amplitude at the ω frequency to ensure The oscillation frequency of the oscillator is about ω. The oscillator is mainly composed of a resonator, a _first NMOS transistor M1 and a second NMOS transistor _M2 .

Frequency division by four: the frequency of the input signal IN of the entire circuit is ω _in (the frequency is ω _in = 4ω), and it is injected into the gate of the third NMOS transistor M ₃ through the AC coupling of the capacitor C _in , and the operation of the third NMOS transistor M ₃ The principle is as Drain-Pumpedmixer (drain mixer), and the frequency change process is ω _in -3ω = ω and ω _in - ω =3ω, but the oscillator oscillation frequency is ω, so the circuit realizes the frequency division by four, and the utility model The oscillator output signal in the frequency divider contains a strong third harmonic.

Frequency division by three: the _fourth NMOS tube M4 and the _fifth NMOS tube M5 are differential floating source injection tubes. During the operation of the circuit, the CM point is the common mode point of the positive and negative output terminals of the oscillator (frequency is ω), The CM point signal contains strong 2ω frequencies.

There is a certain degree of coupling between the third inductance L ₂₊ and the fifth inductance L ₃₊ , the fourth inductance L _2-- and the sixth inductance L 3--, and the coupling coefficient is k, forming a transformer structure; the third inductance L _{2-- 2+} and the fifth inductor L ₃₊ form a first transformer T ₁ , and the fourth inductor L _2- and the sixth inductor L _3- form a transformer second transformer T ₂ .

As mentioned above, the third harmonic of the differential output terminal of the oscillator in the frequency divider is coupled to the gates of the _fourth NMOS transistor M4 and the _fifth NMOS transistor M5 by the _first transformer T1 and the _second transformer T2, respectively ; The 3ω frequency component signal of the gate of the _fourth NMOS transistor M4 and the _fifth NMOS transistor M5 is mixed with the 2ω frequency component signal of the CM point, and the frequency change process is 3ω - 2ω = ω and 3ω + 2ω = 5ω; After mixing, a signal output containing ω and 5ω frequencies is obtained, but the oscillator oscillates at the frequency ω, so the 5ω frequency component is filtered out by the resonator, and the frequency divider realizes the frequency division by three. As shown in the input signal sensitivity curve shown in Figure 3, the frequency range of 0dBm power injection is 22.8-32.4 GHz, the center frequency is 27.6 GHz, and the bandwidth reaches 34.8%. Figure 4 shows the ratio of the output signal and its third harmonic (third harmonic rejection ratio) of the output of the oscillator after the open-drain output buffer stage at different input frequencies without additional filtering at the output end, The ratio can reach a minimum of about 8dB and a maximum of close to 22dB.

The above-mentioned embodiments are all preferred embodiments of the present utility model, but the embodiments of the present utility model are not limited by the above-mentioned embodiments, and any other changes, modifications, Substitution, combination, and simplification should all be equivalent substitution methods, which are all included in the protection scope of the present invention.

Claims (9)

1. A broadband injection-locked frequency divider including transformer coupling divide-by-three, characterized in that it comprises a first inductance L ₁₊ , a second inductance L _1- , a third inductance L ₂₊ , and a fourth inductance L _2- , fifth inductor L ₃₊ , sixth inductor L _3- , power supply VDD, first resistor R _p , second resistor R ₁ , first capacitor C ₁₊ , second capacitor C _1- , third capacitor C ₂₊ , fourth capacitor C _2- , fifth capacitor C _in , first NMOS transistor M ₁ , second NMOS transistor M ₂ , third NMOS transistor M ₃ , fourth NMOS transistor M ₄ , fifth NMOS transistor M _5. The sixth NMOS transistor M ₆ , the seventh NMOS transistor M ₇ , the first bias voltage VB ₁ and the second bias voltage VB ₂ ; The positive terminals of the first inductor L ₁₊ and the second inductor L _1- are both connected to the power supply VDD, and the two ends of the first resistor R _p are respectively connected to the negative terminals of the first inductor L ₁₊ and the second inductor L _1- ; The first capacitor C ₁₊ is connected to the negative end of the first inductor L ₁₊ , the other end of the first capacitor C ₁₊ is grounded; the second capacitor C _1- is connected to the negative end of the second inductor L _1- , and the second capacitor C _{1 -The} other end is grounded; the positive ends of the third inductor L ₂₊ and the fourth inductor L _2- are respectively connected to the negative ends of the first inductor L ₁₊ and the second inductor L _1- ; the third capacitor C ₂₊ is connected to the third inductor The negative end of L ₂₊ , the other end of the third capacitor C ₂₊ is grounded; the fourth capacitor C _2- is connected to the negative end of the fourth inductor L _2- , and the other end of the fourth capacitor C _2- is grounded; The positive terminals of the fifth inductor L ₃₊ and the sixth inductor L _3- are respectively connected to the gates of the fourth NMOS transistor M ₄ and the fifth NMOS transistor M ₅ , and the negative terminals of the fifth inductor L ₃₊ and the sixth inductor L _3- The terminals are all connected to the second bias voltage VB ₂ ; the source of the fourth NMOS transistor M ₄ is connected to the source of the fifth NMOS transistor M ₅ , and the drain of the fourth NMOS transistor M ₄ is connected to the negative electrode of the third inductor L ₂₊ terminal, the drain of the fifth NMOS transistor M5 is connected to the negative terminal of the fourth inductor _L2- ; the source and drain of the _third NMOS transistor M3 are respectively connected to the _fourth NMOS transistor M4 and the _fifth NMOS transistor _M5 drain; One end of the second resistor R ₁ is connected to the first bias voltage VB ₁ , the other end of the second resistor R ₁ is connected to the gate of M ₃ ; one end of the fifth capacitor C _in is connected to the gate of the third NMOS transistor M ₃ , and the fifth capacitor C The other end of _in is connected to the input signal IN; the sources of the _first NMOS transistor M1 and the second NMOS transistor _M2 are grounded, the gate of the _first NMOS transistor M1 is connected to the drain of the _second NMOS transistor M2, and the first NMOS transistor M2 _The drain of M1 is connected to the drain of the _third NMOS transistor M3, the gate of the _second NMOS transistor M2 is connected to the drain of the _first NMOS transistor M1, and the drain of the _second NMOS transistor M2 is connected to the third NMOS transistor _The source of M3; The gate of the _sixth NMOS transistor M6 is connected to the drain of the _fourth NMOS transistor M4, the source of the _sixth NMOS transistor M6 is grounded, and the drain of the _sixth NMOS transistor M6 is open-drain output; the _seventh NMOS transistor M7 The gate is connected to the drain of the _fifth NMOS transistor M5, the source of the _seventh NMOS transistor M7 is grounded, and the drain of the _seventh NMOS transistor M7 is open-drain output. 2 . The broadband injection-locked divide-by-four frequency divider comprising a transformer-coupled divide-by-three frequency divider according to claim 1 , wherein the positive ends of the third inductance L ₂₊ and the fourth inductance L _2- They are respectively coupled with the positive terminals of the fifth inductor L ₃₊ and the sixth inductor L _3- , and the coupling coefficients are both k. 3. A kind of broadband injection-locked frequency divider including transformer coupling divide-by-three frequency divider according to claim 1, characterized in that, the positive end of the third inductor L ₂₊ and the positive end of the fifth inductor L ₃₊ The terminals are coupled to form the first transformer T ₁ ; the positive terminal of the fourth inductor L _2- and the positive terminal of the sixth inductor L _3- are coupled to form the second transformer T ₂ ; the first transformer T ₁ and the second transformer T ₂ The coupling coefficients are all k. 4. The broadband injection-locked frequency divider comprising transformer coupling divide-by-three according to claim 1 or 3, wherein the first inductor L ₁₊ , the second inductor L _1- , the first inductor L 1- , the first inductor The capacitor C ₁₊ , the second capacitor C _1- , the second resistor R _p , the first transformer T1 and the second transformer T2 constitute a resonator. 5. a kind of broadband injection locking and dividing frequency divider comprising transformer coupling dividing by three according to claim 4, is characterized in that, the impedance of described resonator has two peaks, and the corresponding center frequency is ω and 3ω, the corresponding impedance amplitude at the 3ω frequency should be smaller than the corresponding impedance amplitude at the ω frequency to ensure that the oscillator oscillation frequency is ω. 6. The wideband injection-locked frequency divider comprising transformer coupling divide-by-three frequency divider according to claim 5, characterized in that, the oscillator is mainly composed of a resonator, a first NMOS transistor M ₁ and a second NMOS tube _M2 is composed. 7. a kind of broadband injection locking and dividing frequency divider comprising transformer coupling dividing by three according to claim 1, is characterized _in that, the frequency of input signal IN is ω _in , and is injected into the th The gate of the _three NMOS transistor M3, the input signal IN is mixed with the oscillator output signal, the frequency change process is ω _in -3ω = ω and ω _in - ω = 3ω, the oscillator oscillation frequency is ω, the circuit realizes four frequency, and the output signal contains the third harmonic. 8. The broadband injection-locked frequency divider comprising transformer coupling dividing by three according to claim 1, wherein the _fourth NMOS transistor M4 and the _fifth NMOS transistor M5 are differential floating sources Injecting tube, during the working process of the circuit, the common mode point with the frequency of ω at the positive and negative output terminals of the oscillator is the CM point, and the CM point signal contains the 2ω frequency. 9. The broadband injection-locked divide-by-four frequency divider comprising a transformer-coupled divide-by-three frequency divider according to claim 1, wherein the third harmonic of the differential output terminal of the oscillator is divided by the first transformer T ₁ and the second frequency divider. _The transformer T2 is coupled to the gates of the _fourth NMOS transistor M4 and the _fifth NMOS transistor M5 respectively; the 3ω frequency component signal of the gates of the _fourth NMOS transistor M4 and the _fifth NMOS transistor M5 and the 2ω frequency component of the CM point The signal is mixed, and the frequency change process is 3ω-2ω=ω and 3ω+2ω=5ω; after the frequency mixing, a signal output containing the ω and 5ω frequencies is obtained, and the oscillator oscillates at the frequency ω, so the 5ω frequency component is resonated filter to achieve three frequency division.

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