CN106531115B - Gate driving circuit, driving method and display device - Google Patents
Gate driving circuit, driving method and display device Download PDFInfo
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- CN106531115B CN106531115B CN201710006903.4A CN201710006903A CN106531115B CN 106531115 B CN106531115 B CN 106531115B CN 201710006903 A CN201710006903 A CN 201710006903A CN 106531115 B CN106531115 B CN 106531115B
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000006073 displacement reaction Methods 0.000 claims description 7
- 210000004027 cell Anatomy 0.000 description 28
- 230000005611 electricity Effects 0.000 description 3
- 210000000352 storage cell Anatomy 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
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- 238000002360 preparation method Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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Abstract
The main purpose of the present invention is to provide a kind of gate driving circuit, driving method and display devices.Gate driving circuit includes output control unit and pre-charge control unit；Output control unit includes M-1 grades of output control modules；Pre-charge control unit includes M-1 grades of preliminary filling electric control modules；N grades of preliminary filling electric control modules control N grades of gate drive signal output ends in N grades of gate drive signal output stages and N+1 grades of gate drive signal output ends are not connected to, and control N grades of gate drive signal output ends and N+1 grades of gate drive signal output end connections in N+1 grades of pre-charging stages；M is the positive integer greater than 1, and N+1 is less than or equal to M, and N is positive integer.The present invention solves the problems, such as the low power dissipation design that can not realize display panel while making gate driving circuit have pre-charging functions in the prior art.
Description
Technical field
The present invention relates to display actuation techniques field more particularly to a kind of gate driving circuits, driving method and display dress
It sets.
Background technique
Existing gate driving circuit has the following problems:
" top rake function " is in Power IC (power IC) design, by discharging over the ground, by the height electricity of constant pressure
Buckling inputs grid drive chip at voltage VGHM, VGHM with " top rake " waveform, ultimately forms with " top rake " function
The cut-in voltage Von of TFT (thin film transistor (TFT)), the charge directly bled off over the ground fail to be used effectively；
When a line TFT is closed, which becomes low level by charge release by high level, what this part directly discharged
Charge can also reuse；
The charging time of the every row of the higher liquid crystal display panel of resolution ratio is shorter, and grid line is opened line by line cannot ensure that pixel can fill
Enter preset voltage value, i.e. charge rate is insufficient.
Summary of the invention
The main purpose of the present invention is to provide a kind of gate driving circuit, driving method and display devices, solve existing
Asking for the low power dissipation design of display panel can not be realized in technology while making gate driving circuit that there are pre-charging functions
Topic.
In order to achieve the above object, the present invention provides a kind of gate driving circuits, including M cascade shift registers
Unit and M grades of gate drive signal output ends, the gate driving circuit further include output control unit and preliminary filling electric control list
Member, wherein
The output control unit includes M-1 grades of output control modules；
The pre-charge control unit includes M-1 grades of preliminary filling electric control modules；
N grades of output control modules are connected to the output end and N grades of gate drive signals of N grades of shift register cells
Between output end, for controlling the output end of the N grades of shift register cells in N grades of gate drive signal output stages
It is connect with the N grades of gate drive signal output ends, controls the N grades of shift registers in N+1 grades of pre-charging stages
The output end of unit is not connected to the N grades of gate drive signal output ends；
N grades of preliminary filling electric control modules are connected to the N grades of gate drive signal output ends and N+1 grades of gate drivings
Between signal output end, for controlling the N grades of gate drive signal output ends in N grades of gate drive signal output stages
It is not connected to N+1 grades of gate drive signal output ends, controls the N grades of gate drivings letter in N+1 grades of pre-charging stages
Number output end and N+1 grades of gate drive signal output ends connections；
M is the positive integer greater than 1, and N+1 is less than or equal to M, and N is positive integer.
When implementation, all grades of output control modules that the output control unit includes all connect with a control clock signal terminal
It connects；
N grades of output control modules are specifically used under the control of the control clock signal terminal, defeated in N grades of driving signals
The output end of N grades of shift register cells of stage control is connect with N grades of gate drive signal output ends out, at N+1 grades
The output end that pre-charging stage controls N grades of shift register cells is not connected to N grades of gate drive signal output ends；
All grades of preliminary filling electric control modules that the pre-charge control unit includes also all connect with the control clock signal terminal
It connects；
N grades of preliminary filling electric control modules are specifically used in N grades of gate drive signal output ends and the control clock signal
Under the control at end, the N grades of gate drive signal output ends and N+1 are controlled in N grades of gate drive signal output stages
Grade gate drive signal output end is not connected to, and controls the N grades of gate drive signal output ends in N+1 grades of pre-charging stages
It is connected with N+1 grades of gate drive signal output ends.
When implementation, the N grades of output control modules include: output control transistor, and grid and the control clock are believed
Number end connection, the first pole connect with the N grades of gate drive signal output ends, the second pole and N grades of shift register cells
Output end connection；
The N grades of preliminary filling electric control modules include:
First preliminary filling electric control transistor, grid and the first pole are all connect with the N grades of gate drive signal output ends；
And
Second preliminary filling electric control transistor, grid are connect with the control clock signal terminal, and the first pole is pre- with described first
Second pole of charge control transistor connects, and the second pole is connect with the N+1 grades of gate drive signal output ends.
When implementation, the output control transistor is p-type transistor, the first preliminary filling electric control transistor and described the
Two preliminary filling electric control transistors are all n-type transistor, and the control clock signal terminal is used in the N grades of gate drive signals
Output stage exports low level and exports high level in the N+1 grades of pre-charging stages.
When implementation, the output control transistor and the first preliminary filling electric control transistor are all n-type transistor, described
Second preliminary filling electric control transistor is p-type transistor, and the control clock signal terminal is used in the N grades of gate drive signals
Output stage exports high level and exports low level in the N+1 grades of pre-charging stages.
The present invention also provides a kind of driving methods of gate driving circuit, applied to above-mentioned gate driving circuit, institute
The driving method for stating gate driving circuit includes:
In N grades of gate drive signal output stages, N grades of output control modules control N grades of shift register cells
Output end connect with N grades of gate drive signal output ends, N grades of preliminary filling electric control modules control the N grade grids drive
Dynamic signal output end and N+1 grades of gate drive signal output ends are not connected to；
In N+1 grades of pre-charging stages, N grades of output control modules control the defeated of the N grades of shift register cells
Outlet is not connected to the N grades of gate drive signal output ends, and N grades of preliminary filling electric control modules control the N grades of grids
Driving signal output end is connected with N+1 grades of gate drive signal output ends.
When implementation, when all grades of output control modules that output control unit includes all connect with a control clock signal terminal
It connects, and when pre-charge control unit all grades of preliminary filling electric control modules including also all are connect with the control clock signal terminal,
It is described in N grades of gate drive signal output stages, N grades of output control modules control N grades of shift registers
The output end of unit is connect with N grades of gate drive signal output ends, the N grades of preliminary filling electric control module controls N grades of shiftings
The output end of bit register unit is not connected to step with the N grades of gate drive signal output ends and specifically includes: in N grades of grid
Pole driving signal output stage, under the control of the control clock signal terminal, N grades of output control modules control N grades of displacements
The output end of register cell is connect with N grades of gate drive signal output ends；In N grades of gate drive signal output stages,
Under the control of N grades of gate drive signal output ends and the control clock signal terminal, N grades of preliminary filling electric control modules control institute
It states N grades of gate drive signal output ends and N+1 grades of gate drive signal output ends is not connected to；
It is described in N+1 grades of pre-charging stages, N grades of output control modules control the N grades of shift register cells
Output end be not connected to the N grades of gate drive signal output ends, described N grades of the control of N grades of preliminary filling electric control modules
The output end of shift register cell and the N grades of gate drive signals output end Connection Step include: in N+1 grades of preliminary fillings
In the electric stage, under the control of the control clock signal terminal, N grades of output control modules control the N grades of shift register lists
The output end of member is not connected to the N grades of gate drive signal output ends；In N+1 grades of pre-charging stages, in N grades of grids
Under the control of driving signal output end and the control clock signal terminal, N grades of preliminary filling electric control modules control the N grades of grids
Driving signal output end is connected with N+1 grades of gate drive signal output ends.
The present invention also provides a kind of display devices, including above-mentioned gate driving circuit.
Compared with prior art, gate driving circuit of the present invention, driving method and display device are wrapped by increasing
Multi-level output control module is included, and increases the pre-charge control unit including multistage preliminary filling electric control module, passes through corresponding stage
Output control module control can be exported normally in corresponding stage gate drive signal output stage control gate drive signal, be passed through
Corresponding stage preliminary filling electric control module corresponding next stage pre-charging stage control corresponding stage gate drive signal output end with it is adjacent
The connection of next stage gate drive signal output end so that the same level gate drive signal has top rake, and passes through the same level grid simultaneously
The current potential of pole driving signal falls to adjacent next line precharge, thus between current row grid line and adjacent next line grid line into
Row charge is shared, sufficiently recycles to charge, achievees the purpose that low-power consumption.
Detailed description of the invention
Fig. 1 is the structure chart of gate driving circuit described in the embodiment of the present invention；
Fig. 2 is the circuit diagram of a specific embodiment of gate driving circuit of the present invention；
Fig. 3 is the working timing figure of the specific embodiment of present invention gate driving circuit as shown in Figure 2.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Gate driving circuit described in the embodiment of the present invention, including M cascade shift register cells and M grades of grids drive
Dynamic signal output end, the gate driving circuit further includes output control unit and pre-charge control unit, wherein
The output control unit includes M-1 grades of output control modules；
The pre-charge control unit includes M-1 grades of preliminary filling electric control modules；
N grades of output control modules are connected to the output end and N grades of gate drive signals of N grades of shift register cells
Between output end, for controlling the output end of the N grades of shift register cells in N grades of gate drive signal output stages
It is connect with the N grades of gate drive signal output ends, controls the N grades of shift registers in N+1 grades of pre-charging stages
The output end of unit is not connected to the N grades of gate drive signal output ends；
N grades of preliminary filling electric control modules are connected to the N grades of gate drive signal output ends and N+1 grades of gate drivings
Between signal output end, for controlling the N grades of gate drive signal output ends in N grades of gate drive signal output stages
It is not connected to N+1 grades of gate drive signal output ends, controls the N grades of gate drivings letter in N+1 grades of pre-charging stages
Number output end and N+1 grades of gate drive signal output ends connections；
M is the positive integer greater than 1, and N+1 is less than or equal to M, and N is positive integer.
In practical operation, N grades of gate drive signal output ends are connect with the Nth row grid line in display panel, N+1
Grade gate drive signal output end is connect with the N+1 row grid line in display panel, and so on.
In practical operation, N grades of gate drive signal output ends export N grades of gate drive signals, in N grades of grids
Driving signal output stage, the N grades of gate drive signals are high level, to open Nth row grid line, specific N grades of grid
Being divided in following FIG. 3 for pole driving signal output stage is introduced.
Gate driving circuit described in the embodiment of the present invention includes M-1 grades of output control modules by increasing, and is increased
Pre-charge control unit including M-1 grades of preliminary filling electric control modules is controlled by corresponding stage output control module in corresponding stage grid
Driving signal output stage control gate drive signal in pole can be exported normally, by corresponding stage preliminary filling electric control module corresponding
Next stage pre-charging stage controls corresponding stage gate drive signal output end and adjacent next stage gate drive signal output end connects
It connects, so that the same level gate drive signal has top rake, and phase is fallen to by the current potential of the same level gate drive signal simultaneously
Adjacent next line precharge is shared to carry out charge between current row grid line and adjacent next line grid line, sufficiently sharp again to charge
With achieving the purpose that low-power consumption.
As shown in Figure 1, being N grades of shift register cells marked as SN, label SN+1 is N+1 grades of shift LDs
Device unit, indicating SN+2 is N+2 grades of shift register cells, and indicating SN+3 is N+3 grades of shift register cells；N
For positive integer；
It is N grades of gate drive signal output ends marked as OUTN, is N+1 grades of gate drivings marked as OUTN+1
Signal output end is N+2 grades of gate drive signal output ends marked as OUTN+2, is N+3 grades marked as OUTN+3
Gate drive signal output end；
The N grades of output control modules that the output control unit includes are denoted as 10, and the output control unit includes
N+1 grades of output control modules be denoted as 11, the N+2 grades of output control modules that the output control unit includes are denoted as
12, the N+3 grades of output control modules that the output control unit includes are denoted as 13；
The N grades of preliminary filling electric control modules that the output control unit includes are denoted as 20, the output control unit packet
The N+1 grades of preliminary filling electric control modules included are denoted as 21, the N+2 grades of preliminary filling electric control modules that the output control unit includes
It is denoted as 22；
N grades of output control modules 10 are connected to the output end and N grades of gate drivings of N grades of shift register cell SN
Between signal output end OUTN, for being connect in the output end of N grades of gate drive signal output stage control SN with OUTN,
The output end of N+1 grades of pre-charging stage control SN is not connected to OUTN；
N grades of preliminary filling electric control modules 20 are connected to N grades of gate drive signal output end OUTN and N+1 grades of grids drive
Between dynamic signal OUTN+1, for being not connected in N grades of gate drive signal output stage control OUTN and OUTN+1, in N+
1 pre-charging stage control OUTN is connect with OUTN+1, is moved with guaranteeing that charge can only be oriented from Nth row to N+1 row, Nth row
It carries out charge with N+1 row to share, in the process, Nth row can be formed " top rake ", and N+1 row forms " precharge "；
N+1 grades of output control modules 11 be connected to N+1 grades of shift register cell SN+1 output end and N+1 grades
Between gate drive signal output end OUTN+1, for the output in N+1 grades of gate drive signal output stage control SN+1
End is connect with OUTN+1, is not connected in the output end of N+2 grades of pre-charging stage control SN+1 with OUTN+1；
N+1 grades of preliminary filling electric control modules 21 are connected to N+1 grades of gate drive signal output end OUTN+1 and N+2 grades
Between gate drive signal OUTN+2, for controlling OUTN+1 and OUTN+2 not in N+1 grades of gate drive signal output stages
Connection is connect in N+2 pre-charging stage control OUTN+1 with OUTN+2, to guarantee that charge can only be oriented from N+1 row to N
+ 2 rows are mobile, and N+1 row and N+2 row carry out charge and share, and in the process, N+1 row can be formed " top rake ", N+2
Row forms " precharge "；
N+2 grades of output control modules 12 be connected to N+2 grades of shift register cell SN+2 output end and N+2 grades
Between gate drive signal output end OUTN+2, for the output in N+2 grades of gate drive signal output stage control SN+2
End is connect with OUTN+1, is not connected in the output end of N+3 grades of pre-charging stage control SN+2 with OUTN+2；
N+2 grades of preliminary filling electric control modules 22 are connected to N+2 grades of gate drive signal output end OUTN+2 and N+3 grades
Between gate drive signal OUTN+3, for controlling OUTN+2 and OUTN+3 not in N+2 grades of gate drive signal output stages
Connection is connect in N+3 pre-charging stage control OUTN+2 with OUTN+3, to guarantee that charge can only be oriented from N+2 row to N
+ 3 rows are mobile, and N+2 row and N+3 row carry out charge and share, and in the process, N+2 row can be formed " top rake ", N+3
Row forms " precharge "；
N+3 grades of output control modules 13 be connected to N+3 grades of shift register cell SN+3 output end and N+3 grades
Between gate drive signal output end OUTN+3.
In the specific implementation, when all grades of output control modules that the output control unit includes can be controlled all with one
The connection of clock signal end；
N grades of output control modules are specifically used under the control of the control clock signal terminal, defeated in N grades of driving signals
The output end of N grades of shift register cells of stage control is connect with N grades of gate drive signal output ends out, at N+1 grades
The output end that pre-charging stage controls N grades of shift register cells is not connected to N grades of gate drive signal output ends；
All grades of preliminary filling electric control modules that the pre-charge control unit includes also all connect with the control clock signal terminal
It connects；
N grades of preliminary filling electric control modules are specifically used in N grades of gate drive signal output ends and the control clock signal
Under the control at end, the N grades of gate drive signal output ends and N+1 are controlled in N grades of gate drive signal output stages
Grade gate drive signal output end is not connected to, and controls the N grades of gate drive signal output ends in N+1 grades of pre-charging stages
It is connected with N+1 grades of gate drive signal output ends.
In gate driving circuit described in the embodiment of the present invention, output control module is controlled by control clock signal terminal,
Preliminary filling electric control module is controlled by the same level gate drive signal output end and control clock signal terminal.
Specifically, the N grades of output control modules may include: output control transistor, when grid is with the control
The connection of clock signal end, the first pole are connect with the N grades of gate drive signal output ends, the second pole and N grades of shift registers
The output end of unit connects；
The N grades of preliminary filling electric control modules include:
First preliminary filling electric control transistor, grid and the first pole are all connect with the N grades of gate drive signal output ends；
And
Second preliminary filling electric control transistor, grid are connect with the control clock signal terminal, and the first pole is pre- with described first
Second pole of charge control transistor connects, and the second pole is connect with the N+1 grades of gate drive signal output ends.
According to a kind of specific embodiment, the output control transistor can be p-type transistor, first precharge
It controls transistor and the second preliminary filling electric control transistor can all be n-type transistor, the control clock signal terminal is used for
Low level is exported in the N grades of gate drive signal output stages and exports high level in the N+1 grades of pre-charging stages.
According to another specific embodiment, the output control transistor and the first preliminary filling electric control transistor can
With all for n-type transistor, the second preliminary filling electric control transistor can be p-type transistor, the control clock signal terminal is used
In in N grades of gate drive signal output stages output high level and in the low electricity of N+1 grades of pre-charging stages output
It is flat.
Illustrate gate driving circuit of the present invention below by a specific embodiment.
As shown in Fig. 2, the N grades of output control modules 10 include the first output control transistor on the basis of Fig. 1
T101, grid are connect with control clock signal terminal CLK, and drain electrode is connect with the N grades of gate drive signal output ends OUTN, source
Pole is connect with the output end of N grades of shift register cell SN；
The N grades of preliminary filling electric control modules 20 include:
First preliminary filling electric control transistor T201, grid and drain electrode all with the N grades of gate drive signal output ends
OUTN connection；And
Second preliminary filling electric control transistor T202, grid are connect with the control clock signal terminal CLK, drain electrode and described the
The source electrode of one preliminary filling electric control transistor T201 connects, and source electrode and the N+1 grades of gate drive signal output end OUTN+1 connect
It connects；
The N+1 grades of output control modules 11 include the second output control transistor T111, grid and control clock letter
Number end CLK connection, drain connect with the N+1 grades of gate drive signal output ends OUTN+1, source electrode is posted with N+1 grades of displacements
The output end of storage cell S N+1 connects；
The N+1 grades of preliminary filling electric control modules 21 include:
Third preliminary filling electric control transistor T211, grid and drain electrode all with the N+1 grades of gate drive signal output ends
OUTN+1 connection；And
4th preliminary filling electric control transistor T212, grid are connect with the control clock signal terminal CLK, drain electrode and described the
The source electrode of three preliminary filling electric control transistor T211 connects, and source electrode and the N+2 grades of gate drive signal output end OUTN+2 connect
It connects；
The N+2 grades of output control modules 12 include third output control transistor T121, grid and control clock letter
Number end CLK connection, drain connect with the N+2 grades of gate drive signal output ends OUTN+2, source electrode is posted with N+2 grades of displacements
The output end of storage cell S N+2 connects；
The N+2 grades of preliminary filling electric control modules 22 include:
5th preliminary filling electric control transistor T221, grid and drain electrode all with the N+2 grades of gate drive signal output ends
OUTN+2 connection；And
6th preliminary filling electric control transistor T222, grid are connect with the control clock signal terminal CLK, drain electrode and described the
The source electrode of five preliminary filling electric control transistor T221 connects, and source electrode and the N+3 grades of gate drive signal output end OUTN+3 connect
It connects；
The N+3 grades of output control modules 13 include the second output control transistor T131, grid and control clock letter
Number end CLK connection, drain connect with the N+3 grades of gate drive signal output ends OUTN+3, source electrode is posted with N+3 grades of displacements
The output end of storage cell S N+3 connects.
As shown in figure 3, T101 is disconnected, and T201 and T202 are led when simultaneously OUTN also exports high level to CLK output high level
Logical, charge flows to N+1 row grid line through T201 and T202 by Nth row grid line, carries out charge and shares, in the process, N grades of grid
Pole driving signal can be formed " top rake ", and N+1 row forms " precharge "；
When simultaneously OUTN+1 also exports high level to CLK output high level, T111 is disconnected, and T211 and T212 are connected, charge
N+2 row grid line is flowed to through T211 and T212 by N+1 row grid line, charge is carried out and shares, in the process, N+1 grades of grids
Driving signal can be formed " top rake ", and N+2 row forms " precharge "；
When simultaneously OUTN+2 also exports high level to CLK output high level, T121 is disconnected, and T221 and T222 are connected, charge
N+3 row grid line is flowed to through T221 and T222 by N+2 row grid line, charge is carried out and shares, in the process, N+2 grades of grids
Driving signal can be formed " top rake ", and N+3 row forms " precharge ".
In Fig. 3, tN is N grades of gate drive signal output stages, and tN+1 is that N+1 grades of gate drive signals export rank
Section, t N+2 are N+2 grades of gate drive signal output stages.
In the embodiment shown in fig. 3, high level is exported in N grades of gate drive signals output stage tN, OUTN, such as
24V can be exported, in N+1 grades of gate drive signal output stage Tn+1, OUTN exports low level, such as can export -8V,
N+1 grades of pre-charging stages are between tN and tN+1.
The driving method of gate driving circuit of the present invention, applied to above-mentioned gate driving circuit, the gate driving electricity
The driving method on road includes:
In N grades of gate drive signal output stages, N grades of output control modules control N grades of shift register cells
Output end connect with N grades of gate drive signal output ends, N grades of preliminary filling electric control modules control the N grade grids drive
Dynamic signal output end and N+1 grades of gate drive signal output ends are not connected to；
In N+1 grades of pre-charging stages, N grades of output control modules control the defeated of the N grades of shift register cells
Outlet is not connected to the N grades of gate drive signal output ends, and N grades of preliminary filling electric control modules control the N grades of grids
Driving signal output end is connected with N+1 grades of gate drive signal output ends.
In the specific implementation, when all grades of output control modules that output control unit includes all control clock signal with one
End connection, and all grades of preliminary filling electric control modules that pre-charge control unit includes also all are connect with the control clock signal terminal
When,
It is described in N grades of gate drive signal output stages, N grades of output control modules control N grades of shift registers
The output end of unit is connect with N grades of gate drive signal output ends, the N grades of preliminary filling electric control module controls N grades of shiftings
The output end of bit register unit is not connected to step with the N grades of gate drive signal output ends and specifically includes: in N grades of grid
Pole driving signal output stage, under the control of the control clock signal terminal, N grades of output control modules control N grades of displacements
The output end of register cell is connect with N grades of gate drive signal output ends；In N grades of gate drive signal output stages,
Under the control of N grades of gate drive signal output ends and the control clock signal terminal, N grades of preliminary filling electric control modules control institute
It states N grades of gate drive signal output ends and N+1 grades of gate drive signal output ends is not connected to；
It is described in N+1 grades of pre-charging stages, N grades of output control modules control the N grades of shift register cells
Output end be not connected to the N grades of gate drive signal output ends, described N grades of the control of N grades of preliminary filling electric control modules
The output end of shift register cell and the N grades of gate drive signals output end Connection Step include: in N+1 grades of preliminary fillings
In the electric stage, under the control of the control clock signal terminal, N grades of output control modules control the N grades of shift register lists
The output end of member is not connected to the N grades of gate drive signal output ends；In N+1 grades of pre-charging stages, in N grades of grids
Under the control of driving signal output end and the control clock signal terminal, N grades of preliminary filling electric control modules control the N grades of grids
Driving signal output end is connected with N+1 grades of gate drive signal output ends.
Display device described in the embodiment of the present invention includes above-mentioned gate driving circuit.
The above is a preferred embodiment of the present invention, it is noted that for those skilled in the art
For, without departing from the principles of the present invention, it can also make several improvements and retouch, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (8)
1. a kind of gate driving circuit, including M cascade shift register cells and M grades of gate drive signal output ends,
It is characterized in that, the gate driving circuit further includes output control unit and pre-charge control unit, wherein
The output control unit includes M-1 grades of output control modules；
The pre-charge control unit includes M-1 grades of preliminary filling electric control modules；
N grades of output control modules are connected to the output end of N grades of shift register cells and N grades of gate drive signals export
Between end, for controlling output end and the institute of the N grades of shift register cells in N grades of gate drive signal output stages
N grades of gate drive signal output end connections are stated, control the N grades of shift register cells in N+1 grades of pre-charging stages
Output end be not connected to the N grades of gate drive signal output ends；
N grades of preliminary filling electric control modules are connected to the N grades of gate drive signal output ends and N+1 grades of gate drive signals
Between output end, in N grade gate drive signal output stages controls N grades of gate drive signal output ends and the
N+1 grades of gate drive signal output ends are not connected to, and it is defeated to control the N grades of gate drive signals in N+1 grades of pre-charging stages
Outlet is connected with N+1 grades of gate drive signal output ends；
M is the positive integer greater than 1, and N+1 is less than or equal to M, and N is positive integer.
2. gate driving circuit as described in claim 1, which is characterized in that all grades that the output control unit includes are defeated
Control module is all connect with a control clock signal terminal out；
N grades of output control modules are specifically used under the control of the control clock signal terminal, export rank in N grades of driving signals
The output end of section N grades of shift register cells of control is connect with N grades of gate drive signal output ends, in N+1 grades of preliminary fillings
The output end of electric N grades of shift register cells of stage control is not connected to N grades of gate drive signal output ends；
All grades of preliminary filling electric control modules that the pre-charge control unit includes also all are connect with the control clock signal terminal；
N grades of preliminary filling electric control modules are specifically used in N grades of gate drive signal output ends and the control clock signal terminal
Under control, the N grades of gate drive signal output ends and N+1 grades of grid are controlled in N grades of gate drive signal output stages
Pole driving signal output end is not connected to, and controls the N grades of gate drive signal output ends and the in N+1 grades of pre-charging stages
N+1 grades of gate drive signal output end connections.
3. gate driving circuit as claimed in claim 2, which is characterized in that the N grades of output control modules include: output
Transistor is controlled, grid is connect with the control clock signal terminal, and the first pole and the N grades of gate drive signal output ends connect
It connects, the second pole is connect with the output end of N grades of shift register cells；
The N grades of preliminary filling electric control modules include:
First preliminary filling electric control transistor, grid and the first pole are all connect with the N grades of gate drive signal output ends；With
And
Second preliminary filling electric control transistor, grid are connect with the control clock signal terminal, the first pole and first precharge
The second pole connection of transistor is controlled, the second pole is connect with the N+1 grades of gate drive signal output ends.
4. gate driving circuit as claimed in claim 3, which is characterized in that the output control transistor is p-type transistor,
The first preliminary filling electric control transistor and the second preliminary filling electric control transistor are all n-type transistor, the control clock
Signal end is used to export low level in the N grades of gate drive signal output stages and in the N+1 grades of pre-charging stages
Export high level.
5. gate driving circuit as claimed in claim 3, which is characterized in that
The output control transistor and the first preliminary filling electric control transistor are all n-type transistor, second precharge
Control transistor is p-type transistor, and the control clock signal terminal is used for defeated in the N grades of gate drive signal output stages
Out high level and the N+1 grades of pre-charging stages export low level.
6. a kind of driving method of gate driving circuit, applied to the grid as described in any claim in claim 1 to 5
Driving circuit, which is characterized in that the driving method of the gate driving circuit includes:
In N grades of gate drive signal output stages, N grades of output control modules control the defeated of N grades of shift register cells
Outlet is connect with N grades of gate drive signal output ends, and N grades of preliminary filling electric control modules control the N grades of gate drivings letter
Number output end and N+1 grades of gate drive signal output ends are not connected to；
In N+1 grades of pre-charging stages, N grades of output control modules control the output end of the N grades of shift register cells
It is not connected to the N grades of gate drive signal output ends, N grades of preliminary filling electric control modules control the N grades of gate drivings
Signal output end and N+1 grades of gate drive signal output end connections.
7. the driving method of gate driving circuit as claimed in claim 6, which is characterized in that when output control unit includes
All grades of output control modules are all connect with a control clock signal terminal, and all grades of precharge that pre-charge control unit includes
When control module is also all connect with the control clock signal terminal,
It is described in N grades of gate drive signal output stages, N grades of output control modules control N grades of shift register cells
Output end connect with N grades of gate drive signal output ends, N grades of preliminary filling electric control modules control the N grades of displacements and post
The output end of storage unit is not connected to step with the N grades of gate drive signal output ends and specifically includes: driving in N grades of grids
Dynamic signal output stage, under the control of the control clock signal terminal, N grades of output control modules control N grades of shift LDs
The output end of device unit is connect with N grades of gate drive signal output ends；In N grades of gate drive signal output stages, in N
Under the control of grade gate drive signal output end and the control clock signal terminal, N grades of preliminary filling electric control modules control the N
Grade gate drive signal output end and N+1 grades of gate drive signal output ends are not connected to；
It is described in N+1 grades of pre-charging stages, N grades of output control modules control the defeated of the N grades of shift register cells
Outlet is not connected to the N grades of gate drive signal output ends, the N grades of preliminary filling electric control module controls N grades of displacements
The output end of register cell and the N grades of gate drive signals output end Connection Step include: in N+1 grades of precharge ranks
Section, under the control of the control clock signal terminal, N grades of output control modules control the N grades of shift register cells
Output end is not connected to the N grades of gate drive signal output ends；In N+1 grades of pre-charging stages, in N grades of gate drivings
Under the control of signal output end and the control clock signal terminal, N grades of preliminary filling electric control modules control the N grades of gate drivings
Signal output end and N+1 grades of gate drive signal output end connections.
8. a kind of display device, which is characterized in that including the gate driving as described in any claim in claim 1 to 5
Circuit.
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| CN106920530A (en) * | 2017-05-11 | 2017-07-04 | 惠科股份有限公司 | Drive circuit, drive method of drive circuit and display device |
| TWI706406B (en) * | 2018-05-15 | 2020-10-01 | 矽創電子股份有限公司 | Display panel driving circuit |
| CN109523971B (en) * | 2018-12-24 | 2021-02-26 | 惠科股份有限公司 | Display panel drive circuit and display device |
| CN110767194A (en) * | 2019-11-11 | 2020-02-07 | 京东方科技集团股份有限公司 | Shifting register unit, grid driving circuit and display panel |
| CN111681582B (en) | 2020-06-02 | 2021-08-24 | Tcl华星光电技术有限公司 | Scanning driving method, scanning driving device, electronic apparatus, and storage medium |
| CN112017613A (en) | 2020-09-28 | 2020-12-01 | 北京奕斯伟计算技术有限公司 | Charge sharing circuit and method, display driving module and display device |
| CN116416928B (en) * | 2023-06-08 | 2023-09-19 | 惠科股份有限公司 | Display devices and electronic equipment |
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| KR20060050703A (en) * | 2004-08-27 | 2006-05-19 | 세이코 엡슨 가부시키가이샤 | Drive circuits for electro-optical devices, methods for driving the same, and electro-optical devices and electronic devices |
| CN102314828A (en) * | 2011-06-29 | 2012-01-11 | 友达光电股份有限公司 | Gate drive circuit |
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| CN103714792B (en) * | 2013-12-20 | 2015-11-11 | 京东方科技集团股份有限公司 | A kind of shift register cell, gate driver circuit and display device |
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| KR20060050703A (en) * | 2004-08-27 | 2006-05-19 | 세이코 엡슨 가부시키가이샤 | Drive circuits for electro-optical devices, methods for driving the same, and electro-optical devices and electronic devices |
| CN102314828A (en) * | 2011-06-29 | 2012-01-11 | 友达光电股份有限公司 | Gate drive circuit |
| CN102708778A (en) * | 2011-11-28 | 2012-10-03 | 京东方科技集团股份有限公司 | Shift register and drive method thereof, gate drive device and display device |
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