CN109523971B - Display panel drive circuit and display device - Google Patents
Display panel drive circuit and display device Download PDFInfo
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- CN109523971B CN109523971B CN201811587919.XA CN201811587919A CN109523971B CN 109523971 B CN109523971 B CN 109523971B CN 201811587919 A CN201811587919 A CN 201811587919A CN 109523971 B CN109523971 B CN 109523971B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
The invention discloses a display panel driving circuit and a display device, wherein the display panel driving circuit comprises a gate driving circuit and a charging circuit, the charging circuit comprises a controlled end, a power supply input end and a power supply output end, the controlled end is respectively connected with an Mth signal output end of the gate driving circuit and an Mth +1 th signal output end of the gate driving circuit, the power supply input end is connected with a gate starting voltage output end, the power supply output end is connected with an M +2 th signal output end of the gate driving circuit, the power supply input end and the power supply output end of the charging circuit are conducted when an Mth row pixel unit of a display panel is started and are turned off when the Mth +1 row pixel unit of the display panel is started, and N is larger than or equal to 3.
Description
Technical Field
The present invention relates to the field of display panel technologies, and in particular, to a display panel driving circuit and a display device.
Background
A TFT-LCD (Thin Film Transistor Liquid Crystal Display) is one of the major types of flat panel displays, and has become an important Display platform in modern IT and video products. The TFT-LCD mainly adopts a driving principle that a system main board processes R/G/B compression signals, control signals and power data through a TCON (Timing Controller) IC on a PCB board and then is connected with a display area through an S-COF (Source-Chip on Film) and a G-COF (Gate-Chip on Film), so that the LCD can obtain required power and signals.
In order to increase the charging time, an interlaced pre-charging technique is adopted in the exemplary architecture, that is, the M +2 th row gate is turned on while the M +2 th row gate is turned on for charging, so that the M +2 th row pixel can be charged in advance, and then the M +2 th row pixel is charged to the target voltage at the next time, thereby obtaining a longer charging time. However, the exemplary technology mainly realizes the interlaced pre-charging through TCON control G-COF, and has limitations.
Disclosure of Invention
The invention mainly aims to provide a charging circuit, and aims to solve the limitation of realizing a pre-charging function through a control gate driving circuit of a time schedule controller.
The invention provides a display panel driving circuit, which is set to output line scanning signals to a display panel line by line, wherein the display panel comprises N lines of pixel units, and the display panel driving circuit comprises:
a gate turn-on voltage output terminal configured to output a gate turn-on voltage;
the gate driving circuit comprises N signal output ends which are in one-to-one correspondence with the N rows of the pixel units, and is set to output row scanning signals to the N rows of the pixel units corresponding to the display panel line by line through the N signal output ends;
the charging circuit comprises a controlled end, a power input end and a power output end, wherein the controlled end is respectively connected with the Mth signal output end and the (M + 1) th signal output end of the gate driving circuit, the power input end is connected with the gate starting voltage output end, and the power output end is connected with the (M + 2) th signal output end of the gate driving circuit;
the power input end and the power output end of the charging circuit are connected when the Mth row of pixel units of the display panel are started, and are disconnected when the M +1 th row of pixel units of the display panel are started, wherein N is larger than or equal to 3.
Optionally, the charging circuit comprises:
the switching circuit is set to output the grid starting voltage to the pixel units in the M +2 th row for charging when being conducted and stop charging the pixel units in the M +2 th row when being turned off;
and the switch control circuit is arranged to output a first control signal to control the switch circuit to be switched on when the pixel units in the M & ltth & gt row of the display panel are switched on, and output a second control signal to control the switch circuit to be switched off when the pixel units in the M & lt +1 & gt row of the display panel are switched on.
Optionally, the display panel driving circuit further includes a first unidirectional conducting circuit and a second unidirectional conducting circuit, an input end of the first unidirectional conducting circuit is connected with an mth signal output end of the gate driving circuit, an input end of the second unidirectional conducting circuit is connected with an M +1 th signal output end of the gate driving circuit, an output end of the first unidirectional conducting circuit is connected with a controlled end of the charging circuit, and an output end of the second unidirectional conducting circuit is connected with a controlled end of the charging circuit. Optionally, the first unidirectional conducting circuit and the second unidirectional conducting circuit are both diodes.
Optionally, the switch control circuit comprises:
the grounding resistor comprises a first end and a second end, the first end is grounded, and the second end is connected with the controlled end of the switch circuit;
the signal latch circuit comprises a first signal input end, a second signal input end and a signal output end, wherein the first signal end is connected with the second end of the grounding resistor, the second signal input end is the signal input end of the switch control circuit, and the signal output end of the signal latch circuit correspondingly outputs a level signal according to the line scanning signal received by the second signal input end;
and the level flip circuit is used for carrying out signal flip on the level signal output by the signal latch circuit and outputting the level signal to the switch circuit.
Optionally, the signal latch circuit includes a D flip-flop, a clock input end of the D flip-flop is a second signal input end of the signal latch circuit, a data input end of the D flip-flop is a first signal input end of the signal latch circuit, and a data output end of the D flip-flop is a signal output end of the signal latch circuit.
Optionally, the level flip circuit is an inverter, a signal input end of the inverter is connected to a signal output end of the signal latch circuit, and a signal output end of the inverter is connected to a controlled end of the switch circuit.
Optionally, the switching circuit is an NMOS transistor, a gate of the NMOS transistor is a controlled end of the switching circuit, a drain of the NMOS transistor is connected to the gate-on voltage output end, and a source of the NMOS transistor is connected to the M +2 th signal output end of the gate driving circuit.
The present invention further provides a display panel driving circuit configured to output line scanning signals to a display panel line by line, the display panel including N lines of pixel units, the display panel driving circuit including:
the gate driving circuit comprises N signal output ends which are in one-to-one correspondence with the N rows of the pixel units, and is set to output row scanning signals to the N rows of the pixel units corresponding to the display panel line by line through the N signal output ends;
the NMOS tube is set to output a gate turn-on voltage to the pixel units in the (M + 2) th row for charging when being conducted and stop charging the pixel units in the (M + 2) th row when being turned off;
the grounding resistor comprises a first end and a second end, the first end is grounded, and the second end is connected with the grid electrode of the NMOS tube;
the D trigger comprises a clock input end, a data input end and a data output end, wherein the data input end is connected with the second end of the grounding resistor, the clock input end is respectively connected with the Mth signal output end and the M +1 th signal output end of the gate driving circuit, and the data output end is set to correspondingly output a level signal according to the line scanning signal received by the clock input end;
and the phase inverter is used for inverting the level signal output by the D trigger and outputting the level signal to the NMOS tube, wherein N is greater than or equal to 3.
The present invention also provides a display device, comprising:
the display panel comprises N rows and J columns of pixel units;
and a driving device including a timing control board, a source driving circuit, and the display panel driving circuit as described above.
The technical scheme of the invention is that a display panel driving circuit is composed of a gate driving circuit and a charging circuit and is arranged to output line scanning signals to a display panel line by line, the display panel comprises N lines of pixel units, the gate driving circuit is arranged to output the line scanning signals to the N lines of pixel units corresponding to the display panel line by line through N signal output ends, a power supply input end of the charging circuit is connected with a gate starting voltage output end, a controlled end of the charging circuit is respectively connected with an Mth signal output end and an M +1 th signal output end of the gate driving circuit, the N lines of pixel units of the display panel are started line by line according to the line scanning signals, when the pixel units of the Mth line of the display panel are started, the charging circuit is conducted, the gate starting voltage is output to the pixel units of the M +2 line of the display panel for pre-charging, when the pixel units of the M +1 line of the display panel are started, the charging circuit is turned off, the gate start voltage stops precharging the pixel units of the (M + 2) th row of the display panel, the display panel driving circuit receives signals of the time sequence control board to automatically realize the interlaced precharging, and the time sequence control board does not need to additionally design a control program to control the gate driving circuit to work, so that the interlaced precharging diversity of the display panel is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a block diagram of a display panel driving circuit according to a first embodiment of the present invention;
FIG. 2 is a timing diagram of a row scanning signal in an embodiment of a display panel driving circuit according to the invention;
FIG. 3 is a block diagram of a display panel driving circuit according to a second embodiment of the present invention;
FIG. 4 is a block diagram of a display panel driving circuit according to a third embodiment of the present invention;
FIG. 5 is a block diagram of a display panel driving circuit according to a fourth embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a display panel driving circuit according to an embodiment of the invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the descriptions relating to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and/or" appearing throughout is: the method comprises three parallel schemes, wherein the scheme is taken as an A/B (A/B) as an example, the scheme comprises the scheme A, the scheme B or the scheme A and the scheme B simultaneously satisfy, in addition, the technical schemes between the various embodiments can be combined with each other, but the technical schemes must be based on the realization of the technical schemes by a person skilled in the art, and when the technical schemes are mutually contradictory or can not be realized, the combination of the technical schemes is not considered to exist, and the protection scope of the invention is not within the protection scope of the invention.
The display panel driving circuit 100 according to the present invention is configured to output row scanning signals to the display panel 200 row by row, and the display panel 200 includes N rows of pixel units.
As shown in fig. 1, fig. 1 is a block diagram of a display panel driving circuit 100 according to a first embodiment of the present invention, where the display panel driving circuit 100 includes:
a gate turn-on voltage output terminal configured to output a gate turn-on voltage Vgh;
a gate driving circuit 110, including N signal output terminals, such as G1, G2, etc., corresponding to the N rows of pixel units one by one, and configured to output row scanning signals to the N rows of pixel units corresponding to the display panel 200 row by row through the N signal output terminals;
the charging circuit 120 comprises a controlled end, a power input end and a power output end, wherein the controlled end is respectively connected with the mth signal output end and the (M + 1) th signal output end of the gate driving circuit 110, the power input end is connected with the gate turn-on voltage Vgh output end, and the power output end is connected with the (M + 2) th signal output end of the gate driving circuit 110;
the power input end and the power output end of the charging circuit 120 are turned on when the mth row of pixel units of the display panel 200 is turned on, and are turned off when the M +1 th row of pixel units of the display panel 200 is turned on, where N is greater than or equal to 3.
In the embodiment, the display panel 200 includes, but is not limited to, a liquid crystal display panel, an organic light emitting diode display panel, a field emission display panel, a plasma display panel, and a curved panel, and the liquid crystal panel includes a thin film transistor liquid crystal display panel, a TN (Twisted Nematic) panel, a VA (Vertical Alignment) panel, an IPS (In-Plane Switching) panel, and the like.
The display panel 200 includes a plurality of pixel units, and a pixel matrix with N rows × J columns is formed on the display panel 200, the number of the pixel units in each row is greater than 0, and the pixel units may be pixels or sub-pixels, which are specifically selected according to actual situations, and are not limited specifically here.
In this embodiment, the gate driving circuit 110 may be a GOA (gate drive on array) driving integrated circuit or a conventional gate driving integrated circuit, when the gate driving circuit 110 is the GOA driving integrated circuit, the GOA driving integrated circuit provides a control signal from an external circuit and generates a line scanning signal to the display panel 200 to implement line-by-line turn-on, and when the gate driving circuit 110 is the conventional gate driving integrated circuit, the gate driving circuit 110 receives a gate turn-on voltage Vgh and a gate turn-off voltage Vgl provided by the timing controller, and generates the line scanning signal to implement line-by-line turn-on.
The gate-on voltage Vgh at the gate-on voltage output terminal is provided by the power management integrated circuit on the timing control board, and has a voltage value of about 30V.
As shown in fig. 2, fig. 2 is a timing diagram of row scan signals in an embodiment of the display panel driving circuit 100 of the invention, in which row output high levels (i.e., gate-on voltages Vgh) of each row scan signal are sequentially spaced by the same phase, pixel units in each row of the display panel 200 are turned on when receiving the row output high level, and turned off when receiving the row output low level (i.e., gate-off voltages Vgl), pixel units in each row of the display panel 200 are sequentially turned on from a first row to an nth row when receiving the row scan signals, and the pixel units of the display panel 200 at least include 3 rows.
In this embodiment, the charging circuit 120 includes at least one charging circuit, which is connected between every two signal terminals of the second signal output terminal to the nth signal terminal of the gate driving circuit 110, respectively, the controlled terminal of the charging circuit 120 is connected to the mth and M +1 signal output terminals of the gate driving circuit 110, respectively, the power input terminal is connected to the gate-on voltage Vgh output terminal of the power management integrated circuit, and the power output terminal is connected to the M +2 th row of pixel cells of the display panel 200, and assuming that the gate driving circuit 110 has 4 signal output terminals, respectively, a charging circuit 120 is provided between the second signal output terminal and the third signal output terminal of the gate driving circuit 110, and between the third signal output terminal and the fourth signal output terminal of the gate driving circuit 110, taking the charging circuit provided between the second signal output terminal and the third signal output terminal of the gate driving circuit 110 as an example, at this time, M is equal to 1, the controlled terminal of the charging circuit 120 is connected to the first signal output terminal and the second signal output terminal of the gate driving circuit 110, the power input terminal of the charging circuit 120 is connected to the gate-on voltage output terminal, and the power output terminal is connected to the 3 rd row pixel unit of the display panel 200.
The display panel driving circuit 100 operates:
the gate driving circuit 110 outputs row scanning signals to the N rows of pixel units of the display panel 200 row by row;
when the M-th row of pixel cells of the display panel 200 is turned on (i.e., the M-th row of pixel cells receives the gate-on voltage Vgh), the charging circuit 120 is turned on, the power input terminal and the power output terminal of the charging circuit 120 are turned on, and the gate-on voltage Vgh output by the power management integrated circuit is pre-charged for the M + 2-th row of pixel cells of the display panel 200;
when the M +1 th row of pixel cells of the display panel 200 are turned on (i.e., the M +1 th row of pixel cells receive the gate-on voltage Vgh), the charging circuit 120 is turned off, and the gate-on voltage Vgh output by the power management integrated circuit stops precharging the M +2 th row of pixel cells of the display panel 200;
when the M +2 th row of pixel cells of the display panel 200 are turned on, the display panel 200 itself is charged.
It is understood that when the pixel units in the M +1 th row are turned on, the charging circuit 120 located between the M +2 th pixel unit and the M +3 th pixel unit of the gate driving circuit 110 is turned on to charge the pixel units in the M +3 th row of the display panel 200, and so on.
The display panel driving circuit 100 is composed of a gate driving circuit 110 and a charging circuit 120, and is configured to output row scanning signals to a display panel 200 row by row, the display panel 200 includes N rows of pixel units, the gate driving circuit 110 is configured to output row scanning signals to the N rows of pixel units corresponding to the display panel 200 row by row through N signal output ends, a power input end of the charging circuit 120 is connected with a gate start voltage Vgh output end, a controlled end of the charging circuit 120 is respectively connected with an mth signal output end and an M +1 signal output end of the gate driving circuit 110, the N rows of pixel units of the display panel 200 are started row by row according to the row scanning signals, when the M rows of pixel units of the display panel 200 are started, the charging circuit 120 is conducted, and outputs the gate start voltage Vgh to the M +2 rows of pixel units of the display panel 200 for pre-charging, when the pixel cells in the (M + 1) th row of the display panel 200 are turned on, the charging circuit 120 is turned off, the gate-on voltage Vgh stops precharging the pixel cells in the (M + 2) th row of the display panel 200, the display panel driving circuit 100 automatically realizes the interlace precharging when outputting the row scanning signal, and the timing control board does not need to design a control program additionally to control the operation of the gate driving circuit 110, so that the diversity of the interlace precharging of the display panel 200 is improved.
As shown in fig. 3, fig. 3 is a block diagram of a display panel driving circuit 100 according to a second embodiment of the present invention, in which the charging circuit 120 includes:
the switching circuit 20 is configured to output the gate-on voltage Vgh to the M +2 th row of pixel units for charging when being turned on, and stop charging the M +2 th row of pixel units when being turned off;
the switch control circuit 10 is configured to output a first control signal to control the switch circuit 20 to be turned on when the mth row of pixel units of the display panel 200 is turned on, and output a second control signal to control the switch circuit 20 to be turned off when the M +1 th row of pixel units of the display panel 200 is turned on.
In this embodiment, the power input terminal of the switch circuit 20 is connected to the gate-on voltage Vgh output terminal, the power output terminal is connected to the M +2 th row of pixel units of the display panel 200, and charges the M +2 th row of pixel units of the display panel 200 when the switch circuit is turned on, and the controlled terminal is connected to the switch control circuit 10 and is correspondingly turned on or off according to the control signal output by the switch control circuit 10.
The signal terminal of the switch control circuit 10 is connected to the mth signal output terminal and the M +1 th signal output terminal of the gate driving circuit 110, and outputs a first control signal when the mth row of pixel units of the display panel 200 receives the gate-on voltage Vgh and turns on, the first control signal controls the switch circuit 20 to turn on, so as to charge the M +2 th row of pixel units of the display panel 200, and outputs a second control signal when the M +1 th row of pixel units of the display panel 200 receives the gate-on voltage Vgh and turns off, the second control signal has a polarity opposite to that of the first control signal and controls the switch circuit 20 to turn off, so as to stop charging the M +2 th row of pixel units of the display panel 200.
The switch circuit 20 is a switch device or an integrated circuit with on/off capability, such as a switch chip, an MOS transistor, a triode, and the like, and may be specifically selected according to actual requirements, which is not limited herein.
As shown in fig. 4, fig. 4 is a schematic block diagram of a display panel driving circuit 100 according to a third embodiment of the present invention, in this embodiment, the display panel driving circuit 100 further includes a first unidirectional conducting circuit 30 and a second unidirectional conducting circuit 40, an input terminal of the first unidirectional conducting circuit 30 is connected to an mth signal output terminal of the gate driving circuit 110, an input terminal of the second unidirectional conducting circuit 40 is connected to an M +1 signal output terminal of the gate driving circuit 110, an output terminal of the first unidirectional conducting circuit 30 is connected to a controlled terminal of the charging circuit 120, and an output terminal of the second unidirectional conducting circuit 40 is connected to a controlled terminal of the charging circuit 120.
In this embodiment, because the signal terminal of the charging circuit 120 is connected to the mth signal output terminal and the M +1 th signal output terminal of the gate driving circuit 110, in order to avoid the signals output by the mth signal output terminal and the M +1 th signal output terminal of the gate driving circuit 110 from being fed back to other row pixel units of the display panel 200, a unidirectional conduction circuit is respectively disposed between the mth signal output terminal and the M +1 th signal output terminal of the gate driving circuit 110 and the controlled terminal of the charging circuit 120, thereby avoiding the row scanning signal output by the gate driving circuit 110 from causing a malfunction to the pixel units of the display panel 200.
The unidirectional circuit has the characteristics of unidirectional conduction and reverse-phase cut-off, and may adopt components such as a diode and an optocoupler, and in an optional embodiment, the first unidirectional circuit 30 and the second unidirectional circuit 40 are both diodes.
As shown in fig. 5, fig. 5 is a block diagram of a display panel driving circuit 100 according to a fourth embodiment of the present invention, in which the switch control circuit 10 includes:
a ground resistor R1 including a first terminal connected to ground and a second terminal connected to the controlled terminal of the switch circuit 20;
the signal latch circuit 11 includes a first signal input end, a second signal input end and a signal output end, the first signal end is connected to the second end of the ground resistor R1, the second signal input end is the signal input end of the switch control circuit 10, and the signal output end of the signal latch circuit 11 outputs a level signal according to the line scanning signal received by the second signal input end;
and a level flip circuit 12 configured to flip the level signal output from the signal latch circuit 11 and output the level signal to the switch circuit 20.
In this embodiment, the signal latch circuit 11 changes the output state under the action of a specific input pulse level, including but not limited to a high level signal or a rising edge signal, the second signal input terminal of the signal latch circuit 11 is an enable terminal, the first signal input terminal of the signal latch circuit 11 is a signal input terminal of the signal latch circuit 11, the signal latch circuit 11 assigns the level signal of the input terminal to the signal output terminal only when the second signal input terminal receives the high level or rising edge signal, the state of the output terminal of the signal latch circuit 11 does not change with the state of the input terminal, and the level flip circuit 12 inverts the level signal after receiving the level signal output by the signal latch circuit 11, so that the level signal of the input terminal of the signal latch circuit 11 is opposite to the previous state, thereby ensuring that the signal latch circuit 11 is inverted when receiving the level signal, and further, the level flip circuit 12 is ensured to stably output the control signal to the switch circuit 20, so that the switch circuit 20 is reliably turned on or off.
The initial voltage of the first signal end of the signal latch circuit 11 is zero, when the second signal end receives the gate-on voltage Vgh in the line scanning signal, the voltage of the first signal end is fed back to the signal output end, that is, the low level is continuously output to the level flip circuit 12, the level flip circuit 12 inverts the low level and outputs the high level to the switch circuit 20, the switch circuit 20 is turned on, the charging circuit 120 starts to charge the pixel units of the display panel 200 in an interlaced manner, when the second signal end receives the gate-on voltage Vgh in the line scanning signal again, the voltage of the first signal end is at the high level, the signal latch circuit 11 outputs the high level to the level flip circuit 12, the level flip circuit 12 outputs the low level to the switch circuit 20, and the switch circuit 20 is turned off, thereby stopping the pre-charging.
The level flip circuit 12 may be composed of symmetrical switch transistors and resistors, or may be composed of an inverter D2, which is selected according to actual requirements.
As shown in fig. 6, fig. 6 is a schematic circuit diagram of a display panel driving circuit according to an embodiment of the present invention, in the embodiment, the signal latch circuit 11 includes a D flip-flop D1, a clock input terminal of the D flip-flop D1 is a second signal input terminal of the signal latch circuit 11, a data input terminal of the D flip-flop D1 is a first signal input terminal of the signal latch circuit 11, and a data output terminal of the D flip-flop D1 is a signal output terminal of the signal latch circuit 11.
The D flip-flop D1 has two stable states, "1" and "0", and can be turned from one stable state to the other under the action of a certain external signal, the D flip-flop D1 is turned over in the front edge of the clock pulse signal, the secondary state of the flip-flop depends on the state of the data input terminal D before the rising edge of the pulse arrives, when the row scan signal input to the M-th row of pixel cells of the display panel 200 rises from the gate-off voltage Vgl to the gate-on voltage Vgh, the M-th signal output terminal of the gate driving circuit 110 outputs the rising edge pulse signal to the clock input terminal C of the D flip-flop D1, at this time, the D flip-flop D1 outputs the data input terminal D at a low level to the data output terminal Q, and the level flip-flop 12 switches the low level to output the high level to the switch circuit 20 and the data input terminal D, thereby controlling the switch circuit 20 to be turned off and the data input terminal D to be re-valued, so that D flip-flop D1 effects the toggling of the next state.
In an alternative embodiment, the level flip circuit 12 is an inverter D2, a signal input terminal of the inverter D2 is connected to a signal output terminal of the signal latch circuit 11, and a signal output terminal of the inverter D2 is connected to the controlled terminal of the switch circuit 20.
In this embodiment, the level flip-flop 12 employs an inverter D2, and the inverter D2 inverts the level signal output by the D flip-flop D1 from high level to low level or from low level to high level after receiving the level signal, and feeds back the inverted level signal to the data input terminal of the D flip-flop D1.
In an alternative embodiment, the switch circuit 20 is an NMOS transistor Q1, the gate of the NMOS transistor Q1 is the controlled terminal of the switch circuit 20, the drain of the NMOS transistor Q1 is connected to the gate-on voltage Vgh output terminal, the source of the NMOS transistor Q1 is connected to the M +2 th signal output terminal of the gate driving circuit 110, and the NMOS transistor Q1 is turned on when receiving a high level and turned off when receiving a low level.
The present invention further provides a display panel driving circuit 100 configured to output row scanning signals to a display panel 200 row by row, where the display panel 200 includes N rows of pixel units, and the display panel driving circuit 100 includes:
the gate driving circuit 110 includes N signal output ends corresponding to the N rows of pixel units one to one, and is configured to output row scanning signals to the N rows of pixel units corresponding to the display panel 200 row by row through the N signal output ends;
an NMOS transistor Q1 configured to output a gate-on voltage to charge the M +2 th row of pixel cells when turned on, and to stop charging the M +2 th row of pixel cells when turned off;
a ground resistor R1, including a first terminal and a second terminal, wherein the first terminal is grounded, and the second terminal is connected with the gate of the NMOS transistor Q1;
the D flip-flop D1 includes a clock input terminal, a data input terminal and a data output terminal, the data input terminal is connected to the second terminal of the ground resistor R1, the clock input terminal is connected to the mth signal output terminal and the M +1 th signal output terminal of the gate driving circuit 110, respectively, and the data output terminal is configured to output a level signal according to the line scanning signal received by the clock input terminal;
and the inverter D2 is set to perform signal inversion on the level signal output by the D trigger D1 and output the level signal to the NMOS transistor Q1, wherein N is greater than or equal to 3.
The present invention further provides a display device, which includes a display panel 200, wherein the display panel 200 includes N rows and J columns of pixel units; the driving apparatus includes a timing control board, a source driving circuit, and the display panel driving circuit 100 as described above, and the specific structure of the display panel driving circuit 100 refers to the above embodiments, and since the display apparatus adopts all technical solutions of all the above embodiments, the display apparatus at least has all beneficial effects brought by the technical solutions of the above embodiments, and details are not repeated here.
In this embodiment, the source driving circuit and the display panel driving circuit 100 respectively receive the control signal, the data signal and the clock signal output by the timing control board, and thus, the image display of the display panel 200 is realized.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A display panel drive circuit arranged to output row scanning signals to a display panel row by row, the display panel including N rows of pixel cells, comprising:
a gate turn-on voltage output terminal configured to output a gate turn-on voltage;
the gate driving circuit comprises N signal output ends which are in one-to-one correspondence with the N rows of the pixel units, and is set to output row scanning signals to the N rows of the pixel units corresponding to the display panel line by line through the N signal output ends;
the charging circuit comprises a controlled end, a power input end and a power output end, wherein the controlled end is respectively connected with the Mth signal output end and the (M + 1) th signal output end of the gate driving circuit, the power input end is connected with the gate starting voltage output end, and the power output end is connected with the (M + 2) th signal output end of the gate driving circuit;
the power input end and the power output end of the charging circuit are connected when the Mth row of pixel units of the display panel are started, and are disconnected when the M +1 th row of pixel units of the display panel are started, wherein N is larger than or equal to 3.
2. The display panel driving circuit according to claim 1, wherein the charging circuit includes:
the switching circuit is set to output the grid starting voltage to the pixel units in the M +2 th row for charging when being conducted and stop charging the pixel units in the M +2 th row when being turned off;
and the switch control circuit is arranged to output a first control signal to control the switch circuit to be switched on when the pixel units in the Mth row of the display panel are switched on, and output a second control signal to control the switch circuit to be switched off when the pixel units in the M +1 th row of the display panel are switched on.
3. The display panel driving circuit according to claim 2, further comprising a first unidirectional conducting circuit and a second unidirectional conducting circuit, wherein an input terminal of the first unidirectional conducting circuit is connected to the mth signal output terminal of the gate driving circuit, an input terminal of the second unidirectional conducting circuit is connected to the M +1 th signal output terminal of the gate driving circuit, an output terminal of the first unidirectional conducting circuit is connected to the controlled terminal of the charging circuit, and an output terminal of the second unidirectional conducting circuit is connected to the controlled terminal of the charging circuit.
4. The display panel driving circuit according to claim 3, wherein the first unidirectional conducting circuit and the second unidirectional conducting circuit are both diodes.
5. The display panel drive circuit according to claim 2, wherein the switch control circuit comprises:
the grounding resistor comprises a first end and a second end, the first end is grounded, and the second end is connected with the controlled end of the switch circuit;
the signal latch circuit comprises a first signal input end, a second signal input end and a signal output end, wherein the first signal end is connected with the second end of the grounding resistor, the second signal input end is the signal input end of the switch control circuit, and the signal output end of the signal latch circuit correspondingly outputs a level signal according to the line scanning signal received by the second signal input end;
and the level flip circuit is used for carrying out signal flip on the level signal output by the signal latch circuit and outputting the level signal to the switch circuit.
6. The display panel driving circuit according to claim 5, wherein the signal latch circuit comprises a D flip-flop, a clock input of the D flip-flop is a second signal input of the signal latch circuit, a data input of the D flip-flop is a first signal input of the signal latch circuit, and a data output of the D flip-flop is a signal output of the signal latch circuit.
7. The display panel driving circuit according to claim 5, wherein the level-shifter circuit is an inverter, a signal input terminal of the inverter is connected to a signal output terminal of the signal latch circuit, and a signal output terminal of the inverter is connected to the controlled terminal of the switch circuit.
8. The display panel driving circuit of claim 2, wherein the switching circuit is an NMOS transistor, a gate of the NMOS transistor is a controlled terminal of the switching circuit, a drain of the NMOS transistor is connected to the gate-on voltage output terminal, and a source of the NMOS transistor is connected to the (M + 2) th signal output terminal of the gate driving circuit.
9. A display panel drive circuit arranged to output row scanning signals to a display panel row by row, the display panel including N rows of pixel cells, comprising:
the gate driving circuit comprises N signal output ends which are in one-to-one correspondence with the N rows of the pixel units, and is set to output row scanning signals to the N rows of the pixel units corresponding to the display panel line by line through the N signal output ends;
the NMOS tube is set to output a gate turn-on voltage to the pixel units in the (M + 2) th row for charging when being conducted and stop charging the pixel units in the (M + 2) th row when being turned off;
the grounding resistor comprises a first end and a second end, the first end is grounded, and the second end is connected with the grid electrode of the NMOS tube;
the D trigger comprises a clock input end, a data input end and a data output end, wherein the data input end is connected with the second end of the grounding resistor, the clock input end is respectively connected with the Mth signal output end and the M +1 th signal output end of the gate driving circuit, and the data output end is set to correspondingly output a level signal according to the line scanning signal received by the clock input end;
and the phase inverter is used for inverting the level signal output by the D trigger and outputting the level signal to the NMOS tube, wherein N is greater than or equal to 3.
10. A display device, comprising:
the display panel comprises N rows and J columns of pixel units;
a driving apparatus comprising a timing control board, a source driving circuit, and the display panel driving circuit of any one of claims 1 to 9.
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| CN115547271B (en) * | 2021-12-30 | 2023-08-25 | 惠科股份有限公司 | Display panel and display device |
| CN115719585A (en) * | 2022-11-15 | 2023-02-28 | 武汉华星光电技术有限公司 | Display panel and display device |
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