TWI706406B - Display panel driving circuit - Google Patents

Abstract

The present invention provides a panel drive circuit, which includes a gate drive circuit, at least one connection circuit and a control circuit. The gate driving circuit is coupled to a plurality of gate lines and generates a plurality of gate signals to the gate lines. The connecting circuit connects the Mth gate line and a Pth gate line of one of the gate lines, and M and P are positive integers. And, the control circuit is coupled to the connection circuit and controls the connection circuit. The gate drive circuit outputs the gate signal to the Mth gate line, and during the scanning of the Mth gate line, the control circuit controls the connecting circuit to conduct the Mth gate line and the Pth gate line A connection path between gate lines.

Description

Panel drive circuit

The invention relates to a driving circuit, in particular to a panel driving circuit designed for power saving.

The thin film transistor liquid crystal display includes a display panel and a driving circuit. The driving circuit controls the output voltage of the pixel transistors of the display panel, and controls the liquid crystal arrangement direction in the display panel, thereby controlling the light transmittance to produce gray-scale color effects. The driving circuit is electrically connected to the gate terminal of the pixel transistor, and is responsible for the switching of each column of pixel transistors, turning on a whole column of pixel transistors at a time during scanning. When the pixel transistor is turned on (ON), the driving circuit transmits the voltage that controls the brightness and gray level to the pixels of the display panel through the channel formed by the source and drain terminals of the pixel transistor, and drives the pixels, that is, controls the liquid crystal in the display panel Arrangement direction.

Furthermore, there are parasitic capacitances between the circuits and components in the display panel due to the coupling effect. For example, the equivalent capacitance of a gate line to the ground can include the parasitic capacitance between the gate line and the source line, the parasitic capacitance between the gate line and the common line, and the parasitic capacitance between the gate line and other gate lines. Moreover, the gate line is connected to the gate terminal of the pixel transistor, so the parasitic capacitance between the gate terminal and the source terminal of the pixel transistor also affects the signal on the gate line, that is, the equivalent capacitance of the gate line to the ground terminal also includes The parasitic capacitance between the gate terminal and the source terminal of the pixel transistor. These parasitic capacitances affect the power of the drive circuit Power consumption, and the size of the parasitic capacitance is proportional to the size of the display panel and the panel resolution. In this way, the driving circuit controls the gate current consumption of the pixel transistor through the gate line is also proportional to the size of the display panel and the panel resolution.

Therefore, the present invention provides a panel driving circuit to reduce power consumption during driving of the display panel.

The object of the present invention is to provide a panel driving circuit which reduces power consumption during driving of the display panel.

The present invention discloses a panel drive circuit, which includes a gate drive circuit, at least one connection circuit and a control circuit. The gate driving circuit is coupled to a plurality of gate lines and generates a plurality of gate signals to the gate lines. The connecting circuit connects the Mth gate line and a Pth gate line of one of the gate lines, and M and P are positive integers. And, the control circuit is coupled to the connection circuit and controls the connection circuit. Wherein, the gate driving circuit outputs the gate signal to the Mth gate line, and during the scanning of the Mth gate line, the control circuit controls the connecting circuit to conduct the Mth gate line and the Mth gate line. A connection path between P gate lines.

10: Gate drive circuit

14: select circuit

15: select circuit

16: select circuit

20: Control circuit

30: Source drive circuit

31: source line

40: Connection circuit

41: Connection circuit

42: Connection circuit

CG[X]~CG[X+N]: Gate control signal

CG[X+1]: Gate control signal

CG[X+2]: Gate control signal

EQ[X]~EQ[X+N-1]: Connection control signal

EQ[X+1]: Connection control signal

EQ[X+2]: Connection control signal

G0: Gate signal

G1: Gate signal

G2: Gate signal

GL0: gate line

GL1: Gate line

GL2: Gate line

GLN: gate line

GM: Gate signal

GND: Reference voltage

GP: Gate signal

GQ: Gate signal

LC: liquid crystal capacitor

S0: Source signal

S1: Source signal

S2: Source signal

SN: Source signal

SC: storage capacitor

t1: time

t2: time

t3: time

t4: time

t5: time

t6: time

t7: time

t8: time

VGH: first gate voltage

VGL: second gate voltage

The first figure: it is a schematic diagram of an embodiment in which the panel driving circuit of the present invention is applied to a panel; the second figure: it is a circuit diagram of the first embodiment of the control circuit, the gate drive circuit and the connection circuit of the present invention; The third figure: it is the waveform diagram of the first driving embodiment of the gate signal of the present invention; the fourth diagram: it is the waveform diagram of the second driving embodiment of the gate signal of the present invention; the fifth diagram: it is The waveform diagram of the third driving embodiment of the gate signal of the present invention; the sixth diagram: it is the waveform diagram of the fourth driving embodiment of the gate signal of the present invention; the seventh diagram: it is the control circuit of the present invention, The circuit diagram of the second embodiment of the gate driving circuit and the connecting circuit; and the eighth figure: it is a waveform diagram of the fifth driving embodiment of the gate signal of the present invention.

In the specification and subsequent patent applications, certain words are used to refer to specific elements. However, those with ordinary knowledge in the technical field of the present invention should understand that manufacturers may use different terms to refer to the same element, and, The scope of this specification and subsequent patent applications does not use differences in names as a way of distinguishing elements, but uses differences in the overall technology of elements as a criterion for distinguishing. The "include" mentioned in the entire specification and subsequent patent applications is an open term, so it should be interpreted as "include but not limited to". Furthermore, the term "coupling" here includes any direct and indirect connection means. Therefore, if it is described that a first device is coupled to a second device, it means that the first device can be directly connected to the second device, or can be indirectly connected to the second device through other devices or other connection means.

In order to enable your reviewer to have a further understanding and understanding of the features of the present invention and the effects achieved, I would like to illustrate with examples. The description is as follows: Please refer to the first figure, which shows the panel driving circuit of the present invention applied to the panel Schematic diagram of the embodiment. As shown in the figure, the panel drive circuit includes a gate drive circuit 10, a control circuit 20 and One less connecting circuit 40 can further include a source driving circuit 30. The gate driving circuit 10 is coupled to a plurality of gate lines GL0, GL1, GL2-GLN, and generates a plurality of gate signals G0, G1, G2-GN, and outputs them to the gate lines GL0-GLN. The connecting circuit 40 connects at least two gate lines of the gate lines GL0-GLN. The control circuit 20 is coupled to the gate drive circuit 10, the source drive circuit 30 and the connection circuit 40, and controls the gate drive circuit 10, the source drive circuit 30 and the connection circuit 40, wherein the control circuit 20 can be a timing controller . The source driving circuit 30 generates complex source signals S0, S1, S2-SN to the complex source lines 31. The panel includes a plurality of pixels, and each pixel includes a transistor, a liquid crystal capacitor LC and a storage capacitor SC. The gate driving circuit 10 controls the conduction of the transistors and transmits the source signals S0-SN to the liquid crystal capacitor LC and the storage capacitor SC.

Now for the operation description of the panel driving circuit of the present invention, for example, the connecting circuit 40 connects one of the gate lines GL0-GLN to the Mth gate line and the Pth gate line, and M and P are positive integers. . In the embodiment of the first figure, the gate line GL0 may be the M-th gate line, and the gate line GL1 may be the P-th gate line. However, it is for illustrative purposes only and does not limit the embodiment of the present invention. . When the gate driving circuit 10 outputs the gate signal G0 to the Mth gate line (such as the gate line GL0 shown in the first figure), and during the scanning of the Mth gate line, the control circuit 20 controls the connection circuit 40 to be turned on A connection path between the Mth gate line and the Pth gate line (such as the gate line GL1 shown in the first figure), that is, the Mth gate line and the Pth gate line are connected to each other. In this way, the M-th gate line and the P-th gate line can share power, that is, the M-th gate line and the P-th gate line share power with each other. Thereafter, when the gate driving circuit 10 scans the Mth gate line or the Pth gate line, the gate driving circuit 10 can consume less power to separate the Mth gate line and the Pth gate line. The level is pulled to a forbidden level or a consistent level. Therefore, the panel driving circuit of the present invention can reduce power consumption during driving of the display panel. In an embodiment of the present invention, the connection circuit 40 may be a switch circuit.

Please refer to the second figure, which is a circuit diagram of the first embodiment of the control circuit, gate drive circuit and connection circuit of the present invention. As shown in the figure, the control circuit 20 outputs gate control signals CG[X]~CG[X+N] and connection control signals EQ[X]~EQ[X+N-1], and controls the gate drive circuit 10 and Connect circuit 40. The gate driving circuit 10 controls the levels of the gate signals G0, G1, G2-GN according to the gate control signals CG[X]~CG[X+N]. The connection control signal EQ[X]~EQ[X+N-1] controls the connection circuit 40, a connection control signal EQ[X] controls the connection circuit 40, and conducts between the Mth gate line and the Pth gate line Connection path. The gate drive circuit 10 includes a plurality of selection circuits 14, 15 which are coupled to the control circuit 20 and are respectively coupled to the Mth gate line and the Pth gate line, due to the second embodiment Take the M-th gate line and the P-th gate line for illustration. Therefore, the second figure only shows two selection circuits 14 and 15 respectively receiving the gate control signal CG[X] and the gate control signal CG[X+ 1], but not limited to this. The selection circuits 14 and 15 receive a first gate voltage VGH and a second gate voltage VGL. In this way, the gate control signal CG[X] and the gate control signal CG[X+1] control the selection circuits 14, 15 to output the gate signal GM according to the first gate voltage VGH or the second gate voltage VGL , GP, that is, the level of the control gate signals GM, GP is the level of the first gate voltage VGH or the second gate voltage VGL. Wherein, the level of the first gate voltage VGH is the enable level, and the level of the second gate voltage VGL is the disable level.

Furthermore, the selection circuits 14 and 15 of the embodiment in FIG. 2 further receive a reference voltage GND. However, they may not receive the reference voltage GND, and the level of the reference voltage GND is a reference level. That is, the levels of the gate signals GM and GP output by the selection circuits 14 and 15 can be changed from the enable level to the disable level, or the gate signals GM and GP can be changed from the enable level After being the reference level, it changes to the forbidden level. In addition, the first gate voltage VGH and the second gate voltage VGL may be provided by a charge pump or other power supply circuits, and the reference voltage GND may be provided by a charge pump or a ground terminal voltage.

Please refer to the third figure, which is a waveform diagram of the first driving embodiment of the gate signal of the present invention. As shown in the figure, during time t1 and time t2, the level of the gate signal G0 is changed to the enable level (the level of the first gate voltage VGH), and then from the enable level to the disable level (Level of the second gate voltage VGL). This period is the scanning period of the gate signal G0 scanning the gate line GL0. Similarly, the period between time t3 and time t4 is the scanning period of the gate signal G1 scanning the gate line GL1 The period, and the period between time t5 and time t6 and the period between time t7 and time t8 are the scanning periods during which other scanning signals scan other gate lines.

Referring back to the second and third figures, the control circuit 20 generates a gate control signal CG[X] to the selection circuit 14, and the control selection circuit 14 outputs the first gate voltage VGH as the voltage of the gate signal G0, that is, the control gate The level of the pole signal G0 is the enable level to scan the gate line GL0. In addition, in the embodiment in which the selection circuit 14 includes receiving the reference voltage GND, the control circuit 20 controls the selection circuit 14 to output the reference voltage GND first, and then output the first gate voltage VGH, so that the level of the gate signal G0 is changed from the reference voltage The reference level of GND is raised to the enable level of the first gate voltage VGH. In an embodiment of the present invention, since the reference voltage GND is the ground terminal voltage, and the second gate voltage VGL is a negative voltage, by outputting the ground terminal voltage to the gate line GL0, it can be pulled up without power consumption. The voltage of the gate signal G0 to the ground terminal voltage. Continuing, the first gate voltage VGH is output to the gate line GL0, and the voltage of the gate signal G0 is raised to the first gate voltage VGH, as the first gate voltage VGH is pulled up from the reference voltage GND to the gate signal G0 Compared with the first gate voltage VGH, the voltage of the gate signal G0 is raised from the second gate voltage VGL to save a lot of power. Thus, the power supply circuit that provides the first gate voltage VGH can save a lot of power. The current Igh consumed by the first gate voltage VGH to raise the voltage of the gate signal G0 from the reference voltage GND to the first gate voltage VGH can be expressed as follows: Igh=Frame Rate×Cgate×(VGH-0)---- ------------------------------(1) Among them, Frame Rate is the picture update rate or frame rate; Cgate is the equivalent capacitance value that can be observed on the gate line.

In the same way, when changing the level of the gate signal G0 from the enable level to the disable level, the level of the gate signal G0 can be changed to the reference level of the reference voltage GND. The reference level changes to the disable level of the second gate voltage VGL. The second gate voltage VGL pulls down the voltage of the gate signal G0 from the reference voltage GND to the second gate voltage VGL, which is compared to the second gate voltage VGL. The voltage VGL pulls down the voltage of the gate signal G0 from the first gate voltage VGH, which saves a lot of power. Thus, the power supply circuit that provides the second gate voltage VGL can save a lot of power. The current Igl consumed by the second gate voltage VGL to pull down the voltage of the gate signal G0 from the reference voltage GND to the second gate voltage VGL can be expressed as follows: Igl=Frame Rate×Cgate×(VGL-0)---- ------------------------------(2)

As above, the control circuit 20 generates the gate control signal CG[X+1] to the selection circuit 15. At the beginning of time t1, the control selection circuit 15 outputs the second gate voltage VGL as the voltage of the gate signal G1, that is, control The level of the gate signal G1 is the disable level, and the gate line GL1 is not scanned. In addition, in the embodiment where the selection circuit 15 includes the receiving reference voltage GND, before scanning the gate line GL1, the control circuit 20 controls the selection circuit 15 to output the reference voltage GND first, and then when the gate line GL1 is to be scanned, the second output A gate voltage VGH, so that the panel driving circuit can reduce the power consumption during driving of the display panel.

Furthermore, before the gate signal G0 corresponding to the gate line GL0 is changed from the enable level to the reference level or the disable level of the second gate voltage VGL, in order to save the gate driving circuit 10 from scanning another gate For the power consumption of the gate line (for example, the gate line GL1), the control circuit 20 controls the connection circuit 40 to conduct the connection path between the gate line GL0 and the gate line GL1. In this way, the gate line GL0 and the gate line GL1 are electrically connected to each other through the connection path, so the gate line GL0 and the gate line GL1 share the voltages of the gate signals G0 and G1 on the gate lines GL0 and GL1. As shown in the third figure, the voltage of the gate signal G1 on the gate line GL1 (refer to The voltage GND) is raised by the voltage of the gate signal G0 (first gate voltage VGH) on the gate line GL0, and the voltage of the gate signal G0 on the gate line GL0 (first gate voltage VGH) is reduced. As shown in the third figure, the voltages of the gate signals G0 and G1 located on the gate lines GL0 and GL1 share a half of the first gate voltage VGH (VGH/2). That is, the gate signal G0 on the gate line GL0 raises the level of the gate signal G1 on the gate line GL1, and the level of the gate signal G0 on the gate line GL0 drops. In other words, when the connection path between the M-th gate line and the P-th gate line is turned on, the gate signal on the M-th gate line is pulled up to the level of the gate signal on the P-th gate line. And the level of the gate signal at the Mth gate line drops.

At this time, the levels on the gate line GL0 and the gate line GL1 are both at half the level of the first gate voltage VGH. In this way, when scanning the gate line GL1, the first gate voltage VGH raises the voltage of the gate signal G1 of the gate line GL1 from half of the first gate voltage VGH to the first gate voltage VGH, which can reduce power consumption , The consumed current Igh can be expressed as follows: Igh=Frame Rate×Cgate×(VGH-VGH/2)------------------------- ---------(3)

Based on the above, during the period when the panel driving circuit of the present invention drives the panel, the gate signal corresponding to the Mth gate line scans the Mth gate line, and the level of the gate signal corresponding to the Mth gate line is Before the transition from the enable level to the disable level, the control circuit 20 controls the connection circuit 40 to conduct the connection path between the M-th gate line and the P-th gate line to save power consumption during panel driving. In addition, when the control circuit 20 controls the connection circuit 40 to conduct the connection path between the Mth gate line and the Pth gate line, the gate drive circuit 10 stops outputting the gate signal corresponding to the Mth gate line. And the gate signal corresponding to the P-th gate line. For example, when connecting the connection path between the gate line GL0 and the gate line GL1, the gate driving circuit 10 stops outputting the gate signal G0 corresponding to the gate line GL0 and the gate signal G1 corresponding to the gate line GL1, namely Stop outputting voltage to the gate lines GL0 and GL1.

Furthermore, after connecting the connection path between the gate line GL0 and the gate line GL1 for an appropriate period of time, the appropriate time is determined according to requirements, and the control circuit 20 controls the connection circuit 40 to disconnect the gate line GL0 and the gate line GL1 The connection path of the gate line GL0, that is, the connection path between the gate line GL0 and the gate line GL1 is disconnected before the level of the gate signal G0 of the gate line GL0 changes to the disabled level. In other words, the control circuit 20 controls the connection circuit 40 to disconnect the connection path between the Mth gate line and the Pth gate line before the level of the gate signal of the Mth gate line changes to the disable level. Moreover, after the connection circuit 40 disconnects the connection path between the gate line GL0 and the gate line GL1, the gate drive circuit 10 controls the level of the gate signal G0 corresponding to the gate line GL0 to change to the disabled level, First change to the reference level of the reference voltage GND.

It can be seen from the above description that in the embodiment where the selection circuit 14 includes receiving the reference voltage GND, when the connection path between the gate line GL0 and the gate line GL1 is connected, the level on the gate line GL1 is from the reference level The level of the first gate voltage VGH is changed to half. That is, the control circuit 20 controls the connection circuit 40 to turn on the connection path between the Mth gate line and the Pth gate line before the gate drive circuit 10 controls the level of the gate signal corresponding to the Pth gate line Change to the reference level. Thereafter, after the connection circuit 40 disconnects the connection path between the gate line GL0 and the gate line GL1, the gate driving circuit 10 controls the gate signal G1 corresponding to the gate line GL1 to turn into an enable level to scan the second gate The level of the gate line GL1, that is, the gate signal G1 is changed from the level of half of the first gate voltage VGH to the level of the first gate voltage VGH. Continue, the power on the gate line GL1 can also be shared with other gate lines, that is, the gate signal G1 of the gate line GL1 raises the level of the gate signal G2 of the gate line GL2, and the level of the gate signal G1 Bit lowered. The technical content of the remaining gate lines sharing power can be implemented as in the scanning mode of the gate line GL0 and the gate line GL1 in the embodiment of the third figure, and will not be described again.

In addition, the connecting circuit 40 can further connect the gate line GL0 and the gate line GL2, and conduct the connection path between the gate line GL0 and the gate line GL2, that is, the gate line GLO is electrically connected to the gate line at the same time. GL1 and GL2 allow the gate lines GL0, GL1 and GL2 to share power with each other to save power. It can be seen that the power sharing mechanism of the present invention does not restrict two gate lines to share power, and two or more gate lines can be electrically connected to each other to share power according to usage needs.

Please refer to the fourth figure, which is a waveform diagram of the second driving embodiment of the gate signal of the present invention. The difference between the embodiment in FIG. 4 and the embodiment in FIG. 3 is that the third diagram illustrates that the Mth gate line and the Pth gate line are adjacent gate lines. However, the technology of the present invention can also be applied to the power sharing of non-adjacent gate lines in the embodiment in FIG. 4, and the driving method is the same as that in FIG.

Please refer to the fifth figure, which is a waveform diagram of the third driving embodiment of the gate signal of the present invention. As shown in the figure, the fifth embodiment uses the gate line GL0 to be connected to other gate lines before the reference level of the reference voltage GND is lowered to the disable level of the second gate voltage VGL to save gate driving The circuit 10 controls the power to reduce the voltage of the gate signal G0 of the gate line GL0 from the reference voltage GND to the second gate voltage VGL. As shown in Figure 5, when the voltage of the gate signal G0 of the gate line GL0 is the reference voltage GND and the voltage of the gate signal G1 of the gate line GL1 is the second gate voltage VGL, the gate line GL0 is connected to the gate Line GL1, so the power of the two gate signals G0 and G1 are shared with each other, that is, the voltage of the gate signal G0 drops to half of the second gate voltage VGL, and the voltage of the gate signal G1 rises to half of the second gate Polar voltage VGL. Since the voltage of the second gate voltage VGL pull-down gate signal G0 is from half of the second gate voltage VGL to the second gate voltage VGL, it pulls down the gate signal G0 from the reference voltage GND compared to the second gate voltage VGL The voltage to the second gate voltage VGL saves a lot of power. The power supply circuit that provides the second gate voltage VGL can save a lot of power. The current Igl consumed can be expressed as follows: Igl=Frame Rate×Cgate×(VGL -VGL/2)----------------------------------(4)

On the contrary, the third and fourth embodiments use the voltage of the gate signal G0 of the gate line GL0 to decrease from the enable level of the first gate voltage VGH to the voltage before the reference level of the reference voltage GND. Share the power to other gate lines to save other gate lines’ power from the disable level of the second gate voltage VGL or the reference level of the reference voltage GND to the enable level of the first gate voltage VGH .

Therefore, according to the embodiment of FIG. 5, during the scanning period between time t1 and time t2, the gate driving circuit 10 controls the level of the gate signal G0 of the gate line GL0 from the disable level of the second gate voltage VGL After the voltage level rises to the reference level of the reference voltage GND, the level of the gate signal G0 is controlled to rise to the enable level of the first gate voltage VGH. Thereafter, the gate driving circuit 10 controls the level of the gate signal G0 to change to a reference level, and the control circuit 20 controls the connecting circuit 40 to conduct the connection path between the gate line GL0 and the gate line GL1. Before turning on the connection path between the gate line GL0 and the gate line GL1, the gate driving circuit 10 controls the level of the gate signal G1 corresponding to the gate line GL1 to be the disable level of the second gate voltage VGL. After the connection path between the gate line GL0 and the gate line GL1 is turned on, the gate signal G0 located on the gate line GL0 pulls up the level of the gate signal G1 located on the gate line GL1 and is located on the gate line GL0 The level of the gate signal G0 drops.

Referring again to the fifth figure, before the level of the gate signal G0 of the gate line GL0 changes to the disabled level, the control circuit 20 controls the connection circuit 40 to disconnect the connection path between the gate line GL0 and the gate line GL1. After the connection circuit 40 disconnects the connection path between the gate line GL0 and the gate line GL1, the gate drive circuit 10 controls the level of the gate signal G0 corresponding to the gate line GL0 to change to the second gate voltage VGL forbidden Can be in place. Moreover, after the connection circuit 40 disconnects the connection path between the gate line GL0 and the gate line GL1, the gate driving circuit 10 also controls the level of the gate signal G1 corresponding to the gate line GL1 to change to the reference voltage GND. This behavior does not consume power, and the gate driving circuit 10 controls the level of the gate signal G1 to change to the enable level of the first gate voltage VGH. In addition, while the control circuit 20 controls the connection circuit 40 to conduct the connection path between the Mth gate line and the Pth gate line, the gate drive circuit 10 stops outputting corresponding to the Mth gate. The gate signal of the gate line (for example, gate line GL0) and the gate signal corresponding to the P-th gate line (for example, gate line GL1).

Please refer to the sixth figure, which is a waveform diagram of the fourth driving embodiment of the gate signal of the present invention. The difference between the embodiment in FIG. 6 and the embodiment in FIG. 5 is that the fifth diagram illustrates that the Mth gate line and the Pth gate line are adjacent gate lines. However, the technology of the present invention can also be applied to the power sharing of non-adjacent gate lines in the embodiment in FIG. 6, and the driving method is the same as that in FIG.

Please refer to the seventh figure, which is a circuit diagram of the second embodiment of the control circuit, gate drive circuit and connection circuit of the present invention. As shown in the figure, the seventh embodiment adds a connecting circuit 41 between the Mth gate line and the Qth gate line, and adds a connecting circuit 42 between the Pth gate line and the Qth gate line. Between the polar lines, Q is a positive integer. In this way, the power on the Mth gate line can be shared to the other two gate lines through the two connecting circuits 40 and 41 (the seventh embodiment is shared to the Pth gate line and the Qth gate line) , And the power on the P-th gate line can be shared to other gate lines through the connection circuit 42 (the seventh embodiment is shared to the Q-th gate line). The connection circuits 40, 41, 42 are coupled to the control circuit 20, and receive connection control signals EQ[X], EQ[X+1], and EQ[X+2]. Connect the control signals EQ[X], EQ[X+1] and EQ[X+2] to control the connection circuits 40, 41, and 42 to turn on or off the Mth gate line and the Pth gate line, Qth The connection path between the gate lines, and the connection path between the P-th gate line and the Q-th gate line. The selection circuits 14, 15, and 16 of the gate drive circuit 10 respectively output gate signals GM, GP, GQ to the first according to the gate control signals CG[X], CG[X+1], CG[X+2] M gate lines, P gate lines and Q gate lines, that is, output the first gate voltage according to the gate control signals CG[X], CG[X+1], CG[X+2] VGH, the second gate voltage VGL or the reference voltage GND to the Mth gate line, the Pth gate line and the Qth gate line. It means that the levels of the gate signals GM, GP, and GQ can be the enable level of the first gate voltage VGH, the disable level of the second gate voltage VGL, and the reference level of the reference voltage GND.

Please refer to the seventh and eighth pictures. The eighth figure is a waveform diagram of the fifth driving embodiment of the gate signal of the present invention. As shown in the figure, during the scanning period at time t1 and time t2, the level of the gate line GL0 (the Mth gate line) is reduced from the enable level of the first gate voltage VGH to the reference level of the reference voltage GND The power before the bit is shared to the gate line GL1 (the P-th gate line). The technical content is as in the scanning period of time t1 and time t2 in the third figure, and will not be described again. Furthermore, before the level of the gate line GL0 drops from the reference level of the reference voltage GND to the disable level of the second gate voltage VGL, the power of the gate line GL2 (the Qth gate line) is shared to the gate The technical content of the polar line GL0 is as shown in the scanning period of time t1 and time t2 in the fifth figure, and will not be repeated. Therefore, the gate line GL0 shares power with the gate line GL1, and the gate line GL0 shares power with the gate line GL2, so as to save the power consumption of the gate driving circuit 10 scanning the gate line GL1 and the gate line GL0. In addition, as shown in the figure, during the scanning period between time t3 and time t4, the level of the gate line GL1 (the Pth gate line) is reduced from the enable level of the first gate voltage VGH to the reference voltage GND. The power before the reference level is also shared to the gate line GL2 (the Q-th gate line). The technical content is as shown in the scanning period of time t1 and time t2 in the third figure, and will not be repeated. In addition, the control circuit 20 controls the connecting circuits 40, 41, 42 to conduct the Mth gate line and the Pth gate line, the Mth gate line and the Qth gate line, and the Pth gate line and the first gate line. During the connection path between the Q gate lines, the gate drive circuit 10 stops outputting corresponding to the Mth gate line (for example, gate line GL0) and corresponding to the Pth gate line (for example, gate line GL1) , The gate signal corresponding to the Q-th gate line (for example, the gate line GL2).

In summary, the present invention discloses a panel drive circuit, which includes a gate drive circuit, at least one connection circuit and a control circuit. The gate driving circuit is coupled to a plurality of gate lines and generates a plurality of gate signals to the gate lines. The connecting circuit connects the Mth gate line and a Pth gate line of one of the gate lines, and M and P are positive integers. The control circuit is coupled to the connection circuit and controls the connection circuit. The gate driving circuit outputs the gate signal to the Mth gate line, and during the scanning of the Mth gate line, The control circuit controls the connection circuit to conduct a connection path between the Mth gate line and the Pth gate line, so that power consumption during driving of the display panel can be reduced.

10‧‧‧Gate drive circuit

20‧‧‧Control circuit

14‧‧‧Select circuit

15‧‧‧Select circuit

40‧‧‧Connecting circuit

CG[X]~CG[X+N]‧‧‧Gate control signal

CG[X+1]‧‧‧Gate control signal

EQ[X]~EQ[X+N-1]‧‧‧Connection control signal

GM‧‧‧Gate signal

GND‧‧‧Reference voltage

GP‧‧‧Gate signal

VGH‧‧‧First gate voltage

VGL‧‧‧Second gate voltage

Claims (18)

A panel drive circuit, which includes: A gate drive circuit, coupled to multiple gate lines, generates multiple gate signals, and outputs them to the gate lines; At least one connection circuit connecting the Mth gate line and a Pth gate line of one of the gate lines, where M and P are positive integers; and A control circuit, coupled to the connection circuit, to control the connection circuit; Wherein, the gate driving circuit outputs the gate signal to the Mth gate line, and during the scanning of the Mth gate line, the control circuit controls the connecting circuit to conduct the Mth gate line and the Mth gate line. A connection path between P gate lines. The panel driving circuit described in item 1 of the scope of patent application, wherein, when the connection path between the Mth gate line and the Pth gate line is conductive, the gate located on the Mth gate line The pole signal pulls up the level of the gate signal on the Pth gate line, and the level of the gate signal on the Mth gate line drops. The panel driving circuit described in item 1 of the scope of patent application, wherein the control circuit controls the connection circuit to conduct the connection path between the Mth gate line and the Pth gate line before the gate drive The circuit controls the level of the gate signal corresponding to the P-th gate line to change from a disabled level to a reference level. For the panel driving circuit described in item 3 of the scope of patent application, wherein the control circuit controls the connecting circuit to conduct the connection path between the Mth gate line and the Pth gate line, and then corresponds to Before the level of the gate signal of the Mth gate line changes to the disable level, the control circuit controls the connection circuit to disconnect the Mth gate line and the Pth gate line After the connection path and the connection circuit disconnect the connection path between the Mth gate line and the Pth gate line, the gate drive circuit controls the gate corresponding to the Pth gate line The level of the signal is changed to a consistent level. The panel driving circuit described in item 1 of the scope of patent application, wherein, during the scanning of the Mth gate line by the gate signal corresponding to the Mth gate line, the time corresponding to the Mth gate line The level of the gate signal is a uniform energy level, and before changing to a disabled level, the control circuit controls the connection circuit to conduct the connection between the Mth gate line and the Pth gate line path. For the panel driving circuit described in item 5 of the scope of patent application, wherein the control circuit controls the connection circuit to conduct the connection path between the Mth gate line and the Pth gate line, and then corresponds to Before the level of the gate signal of the Mth gate line changes to the disable level, the control circuit controls the connection circuit to disconnect the Mth gate line and the Pth gate line The connection path. The panel drive circuit described in item 6 of the scope of patent application, wherein, after the connection circuit disconnects the connection path between the Mth gate line and the Pth gate line, the gate drive circuit controls the corresponding Before the level of the gate signal of the M-th gate line is changed to the forbidden level, it is changed to a reference level. For the panel drive circuit described in item 7 of the scope of patent application, wherein another connecting circuit connects the Mth gate line and a Qth gate line of the gate lines, and the gate drive circuit controls the corresponding After the level of the gate signal of the Mth gate line is changed to the reference level, the control circuit controls the other connecting circuit to conduct between the Mth gate line and the Qth gate line During the period during which the other connection circuit conducts the connection path between the Mth gate line and the Qth gate line, the gate drive circuit stops outputting corresponding to the Mth gate line The gate signal of and the gate signal corresponding to the Qth gate line, Q is a positive integer. For the panel driving circuit described in item 8 of the scope of patent application, wherein the gate driving circuit controls the level of the gate signal corresponding to the Qth gate line as the disable level, which is located at the Mth The gate signal of each gate line is pulled up to the level of the gate signal of the Q-th gate line, and the level of the gate signal of the M-th gate line is lowered. For the panel driving circuit described in item 9 of the scope of patent application, wherein the control circuit controls the other connection circuit to conduct the connection path between the Mth gate line and the Qth gate line, and then Before the level of the gate signal of the Mth gate line is changed to the disable level, the control circuit controls the other connection circuit to disconnect the Mth gate line and the Qth gate line After the other connection circuit disconnects the connection path between the Mth gate line and the Qth gate line, the gate drive circuit controls the corresponding to the Qth gate line Before the level of the gate signal is changed to the uniform energy level, it is changed to the reference level. For the panel driving circuit described in item 10 of the scope of patent application, wherein another connecting circuit connects the Pth gate line and the Qth gate line of the gate lines, corresponding to the Pth gate The level of the gate signal of the pole line is the enable level, and before changing to the disable level, the control circuit controls the other connecting circuit to conduct the P-th gate line and the Q-th gate A connection path between the pole lines, the gate signal located on the Pth gate line pulls up the level of the gate signal on the Qth gate line, and is located on the Pth gate line While the level of the gate signal drops and the another connecting circuit conducts the connection path between the Pth gate line and the Qth gate line, the gate drive circuit stops outputting corresponding to the Pth gate line. The gate signal of one gate line and the gate signal corresponding to the Qth gate line. For the panel driving circuit described in item 11 of the scope of patent application, wherein the control circuit controls the further connecting circuit to conduct the connection path between the Pth gate line and the Qth gate line, and then Before the level of the gate signal of the P-th gate line is changed to the disable level, the control circuit controls the further connecting circuit to disconnect the P-th gate line and the Q-th gate line The connection path between. For the panel drive circuit described in item 12 of the scope of patent application, wherein, after the further connection circuit disconnects the connection path between the Pth gate line and the Qth gate line, the gate drive circuit Control the level of the gate signal corresponding to the Q-th gate line to change to the enable level. For the panel driving circuit described in item 1 of the scope of the patent application, wherein the gate driving circuit controls the level of the gate signal corresponding to the Mth gate line to a uniform energy level, which is transformed into a prohibited level Before the energy level, it is first converted to a reference level, and the control circuit controls the connection circuit to conduct the connection path between the Mth gate line and the Pth gate line. For example, the panel driving circuit described in item 14 of the scope of patent application, wherein the gate driving circuit controls the level of the gate signal corresponding to the Pth gate line to a disable level, which is located at the Mth The gate signal of each gate line is pulled up to the level of the gate signal of the Pth gate line, and the level of the gate signal of the Mth gate line is lowered. For example, the panel driving circuit described in item 14 of the scope of patent application, wherein the control circuit controls the connection circuit to conduct the connection path between the Mth gate line and the Pth gate line, and then after Before the level of the gate signal of the M gate lines is changed to the disable level, the control circuit controls the connection circuit to disconnect the connection between the Mth gate line and the Pth gate line After the connection circuit disconnects the connection path between the Mth gate line and the Pth gate line, the gate drive circuit controls the gate signal corresponding to the Mth gate line The level is changed to the forbidden level. For example, the panel driving circuit described in item 14 of the scope of patent application, wherein the control circuit controls the connection circuit to conduct the connection path between the Mth gate line and the Pth gate line, and then after Before the level of the gate signal of the M gate lines is changed to the disable level, the control circuit controls the connection circuit to disconnect the connection between the Mth gate line and the Pth gate line After the connection circuit disconnects the connection path between the Mth gate line and the Pth gate line, the gate drive circuit controls the gate signal corresponding to the Pth gate line Before the level is changed to the uniform energy level, it is first changed to the reference level. For the panel drive circuit described in item 1 of the scope of patent application, wherein the control circuit controls the connection circuit to conduct the connection path between the Mth gate line and the Pth gate line during the period during which the gate The driving circuit stops outputting the gate signal corresponding to the Mth gate line and the gate signal corresponding to the Pth gate line.

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