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CN106505059B - Substrate structure - Google Patents

Substrate structure Download PDF

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Publication number
CN106505059B
CN106505059B CN201510652194.8A CN201510652194A CN106505059B CN 106505059 B CN106505059 B CN 106505059B CN 201510652194 A CN201510652194 A CN 201510652194A CN 106505059 B CN106505059 B CN 106505059B
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China
Prior art keywords
electric contact
contact mat
hollow
out parts
board structure
Prior art date
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Active
Application number
CN201510652194.8A
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Chinese (zh)
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CN106505059A (en
Inventor
潘嘉伟
高迺澔
张宏达
姜亦震
江东昇
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Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
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Publication of CN106505059A publication Critical patent/CN106505059A/en
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Publication of CN106505059B publication Critical patent/CN106505059B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05012—Shape in top view
    • H01L2224/05015—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/05076—Plural internal layers being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A substrate structure, comprising: the substrate structure comprises a substrate body and an electric contact pad arranged on the substrate body, wherein the electric contact pad is provided with at least one hollow part so that part of the surface of the substrate body is exposed out of the hollow part, and the rigidity of the electric contact pad is reduced, so that when the substrate structure is stressed, the counter torque generated by the electric contact pad is greatly reduced, and the problem of breakage of the substrate body is avoided.

Description

Board structure
Technical field
The present invention relates to a kind of board structures, more particularly to a kind of board structure of electric contact mat with improvement.
Background technique
With the evolution of semiconductor packaging, semiconductor device (Semiconductor device) has developed difference Encapsulation kenel.Wherein, sphere grid several-group type (Ball grid array, BGA), such as PBGA, EBGA, FCBGA etc., for one kind Advanced semiconductor packaging, it is characterized in that disposing semiconductor subassembly using a package substrate, and in the package substrate The back side, which is planted, sets the most tin balls (Solder ball) arranged at palisade array, makes to hold on the load-bearing part of same units area More input/output connecting pins (I/O connection) are received to meet the semiconductor core of height aggregation (Integration) The demand of piece, and entire encapsulation unit is welded by those tin balls and ties and is electrically connected to external electronic.
In addition, semiconductor package part is light and short, developing way of multi-functional, high speed and high frequency in order to meet, half Conductor chip develops towards fine rule road and small-bore.
Fig. 1 is the schematic cross-sectional view of existing semiconductor chip 1.As shown in Figure 1, providing one has multiple electric contact mats 100 have a substrate 10a and the line construction on substrate 10a with the ontology 10 of conductive trace 101, the ontology 10 10b, and the electric contact mat 100 and conductive trace 101 are set on line construction 10b.Then, an insulating protective layer 11 is formed In on the chip body 10, multiple apertures 110 are formed on the insulating protective layer 11, make the respectively electric contact mat 100 correspondence Expose to the respectively aperture 110.Later, it is formed by convex block underlying metal layer 130 multiple if the conductive component 13 of soldered ball is in the electricity Property engagement pad 100 on, make the conductive component 13 be electrically connected the electric contact mat 100, to complete existing chip package (Flip Chip Package) semiconductor chip 1.
In encapsulation making method, which is bound to package substrate (figure by those conductive components 13 of reflow On slightly), at this point, the semiconductor chip 1 is subjected to external force, for example, reflow oven can generate thermal stress to the inside of the semiconductor chip 1.
But when the inside of the semiconductor chip 1 generates thermal stress, which is solid because of its shape Disk (such as Fig. 1 ' shown in) and there is extremely strong rigidity, therefore the electric contact mat 100 can generate the power to contend with to the thermal stress Square, the torque especially to contend with caused by the edge of the electric contact mat 100 is maximum, causes to be located at the electric contact mat Line construction 10b fragmentation (Crack) due to bearing excessive stresses near 100 edge, K at fragmentation as shown in Figure 1.
Therefore, how to overcome above-mentioned problem of the prior art, have become want to solve the problems, such as at present in fact.
Summary of the invention
In view of the various shortcoming of the above-mentioned prior art, the present invention provides a kind of board structure, broken to avoid the substrate body The problem of splitting.
Board structure of the invention includes: substrate body；And electric contact mat, it is set in the substrate body and has An at least hollow-out parts, to enable the part of the surface of the substrate body expose to the hollow-out parts.
In board structure above-mentioned, which is line construction.
In board structure above-mentioned, which includes substrate and the line construction in the substrate, and the electricity Property engagement pad be set to the line construction on.
In board structure above-mentioned, also there is at least one conductive trace for being electrically connected the electric contact mat in the substrate body.
In board structure above-mentioned, the upper view plane shape of the electric contact mat is round or polygon.
In board structure above-mentioned, which is located at the edge of the electric contact mat.
In board structure above-mentioned, and the side view of the hollow-out parts corresponds to the side view of the electric contact mat.For example, The side of the parallel electric contact mat of the lateral surface of the hollow-out parts；Alternatively, the flat shape of the hollow-out parts is to have the ring-type of notch Or at least two interval sector；Alternatively, the upper view plane shape of the electric contact mat is round or polygon.
Further include insulating protective layer in board structure above-mentioned, is set in the substrate body, and the insulating protective layer has Aperture makes the electric contact mat expose to the aperture.
It further include the conductive component on the electric contact mat in board structure above-mentioned.
It further include the convex block underlying metal layer on the electric contact mat in board structure above-mentioned.
From the foregoing, it will be observed that board structure of the invention becomes the rigidity of the electric contact mat by the design of the hollow-out parts It is small, therefore compared with the prior art, when the board structure stress, which will not generate excessive because rigid too strong The torque to contend with is in the substrate body, therefore the problem of be avoided that substrate body rupture.
Detailed description of the invention
Fig. 1 is the schematic cross-sectional view of existing semiconductor chip；
Fig. 1 ' is the upper viewing view of existing electric contact mat；
Fig. 2 is the schematic cross-sectional view of board structure of the invention；
Fig. 2 ' is the schematic cross-sectional view of another embodiment of Fig. 2；
Fig. 2A to Fig. 2 I is the upper of the various embodiments of the first embodiment of the electric contact mat of board structure of the invention Planar view；And
Fig. 3 A to Fig. 3 C is the upper of the various embodiments of the second embodiment of the electric contact mat of board structure of the invention Planar view.
Description of symbols:
1 semiconductor chip
10 ontologies
10a, 20a substrate
10b, 20b line construction
100,200,300 electric contact mats
101,201 conductive traces
11,21 insulating protective layers
110,210 apertures
13,23 conductive components
130,230 convex block underlying metal layers
2 board structures
20,20 ' substrate bodies
200a, 300a hollow-out parts
At K fragmentation
The side R
S lateral surface.
Specific embodiment
Illustrate embodiments of the present invention below by way of particular specific embodiment, those skilled in the art can be by this explanation The revealed content of book is understood other advantages and efficacy of the present invention easily.
It should be clear that structure, ratio, size depicted in this specification institute attached drawing etc., only to cooperate disclosed in specification Content be not intended to limit the invention enforceable qualifications for the understanding and reading of those skilled in the art, therefore not Has technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size are not influencing institute of the present invention Under the effect of capable of generating and the purpose that can reach, it should all still fall in disclosed technology contents and obtain the range that can cover It is interior.Meanwhile in this specification cited such as "upper" and " one " term, be also only being illustrated convenient for narration, rather than to It limits the scope of the invention, relativeness is altered or modified, under the content of no substantial changes in technology, when being also considered as The enforceable scope of the present invention.
Fig. 2 is the schematic cross-sectional view of board structure 2 of the invention.As shown in Fig. 2, the board structure 2 includes: a substrate sheet Body 20, multiple electric contact mats 200 in the substrate body 20, multiple conductive traces 201 and an insulating protective layer 21.
The substrate body 20 includes line construction, for example, wiring board, with multiple dielectric layers and multiple lines Road floor, and the electric contact mat 200 and the conductive trace 201 are set on outermost dielectric layer and are electrically connected the line layer.
In another embodiment, as shown in Fig. 2 ', the substrate body 20 ' include a substrate 20a and be set to substrate 20a On a line construction 20b, and the electric contact mat 200 be set to line construction 20b on.For example, substrate 20a is semiconductor Substrate, such as wafer, chip, with the intermediate plate etc. of silicon perforation (Through-Silicon Via, abbreviation TSV), and the route knot Structure 20b has multiple dielectric layers (figure omits) and multiple route redistribution layers (redistribution layer, abbreviation RDL) (figure Slightly), and the electric contact mat 200 and the conductive trace 201 are set on outermost dielectric layer and are electrically connected route weight cloth Layer or the electric contact mat 200 and a part of the conductive trace 201 as route redistribution layer.
The electric contact mat 200 is electrically connected the conductive trace 201, and the electric contact mat 200 has at least one Hollow-out parts 200a, to enable the part of the surface of the substrate body 20 (or the line construction 20b) expose to hollow-out parts 200a.
In this present embodiment, hollow-out parts 200a is located at the edge of the electric contact mat 200, but is not connected to this and is electrically connected with The side R (as shown in Figure 2 A) of touch pad 200.
In addition, the forming method of hollow-out parts 200a is etching or the laser electric contact mat 200；Alternatively, can be directly electric Plating or coating form the electric contact mat 200 with hollow-out parts 200a.
In addition, since the respectively electric contact mat 200 and structure around conductive trace 201 and thereon are all the same, therefore in It is only painted single electric contact mat 200 in schema with conductive trace 201 to explain, states clearly hereby.
The insulating protective layer 21 has the aperture 210 of the corresponding exposed electric contact mat 200.For example, the insulation is protected The material of sheath 21 is anti-wlding or dielectric material, such as polyimide (Polyimide, abbreviation PI), benzocyclobutene (Benezocy-clobutene, abbreviation BCB) or poly- to diazole benzene (Polybenzoxazole, abbreviation PBO).
In addition, the board structure 2 further includes the conductive component 23 in the aperture 210, it is electrically connected the electricity Property engagement pad 200.
In this present embodiment, which is soldered ball, metal block etc., and the board structure 2 is made to pass through those conductive groups Part 23 combines other electronic building bricks (figure omits), for example, semiconductor crystal wafer, chip, intermediate plate or wiring board with silicon perforation.
In addition, a convex block underlying metal layer (Under Bump can be initially formed under the conductive component 23 Metallurgy, abbreviation UBM) 230, it is incorporated into the conductive component 23 more firmly on the electric contact mat 200.
Board structure 2 of the invention keeps this in electrical contact by forming hollow-out parts 200a on the electric contact mat 200 The rigidity of pad 200 becomes smaller, when 2 stress of board structure, especially thermal stress and when warpage occurs, the electric contact mat 200 will not generate the excessive torque to contend in the substrate body 20,20 ' because rigidity is too strong, therefore be avoided that the substrate The problem of line layer or RDL fracture of ontology 20,20 '.
In addition, the area of hollow-out parts 200a is bigger, then the effect that the stress of the electric contact mat 200 improves is better, i.e., The electric contact mat 200 has preferably elasticity and flexibility.It is upper when the electric contact mat 200 as shown in Fig. 2A to Fig. 2 H When view plane shape is round, the side shape of the corresponding electric contact mat 200 of the side view (i.e. arcuation) of hollow-out parts 200a Shape (i.e. arcuation), to enable the flat shape of hollow-out parts 200a be formed such as at least sector at two intervals or similar fan-shaped, and preferably Ground, the side R of the parallel electric contact mat 200 of the lateral surface S of hollow-out parts 200a, uses the hollow-out parts for obtaining maximum area 200a。
Preferably, the area of hollow-out parts 200a shown in Fig. 2 E is larger compared to existing electric contact mat, it is caused to be produced Raw torque is smaller, about only 92% of torque caused by existing electric contact mat.
Also, the flat shape of hollow-out parts 200a can also form the annular of tool notch, as shown in figure 2i, generated power Square about only 92% of torque caused by existing electric contact mat.
In addition, the upper view plane shape of the electric contact mat 300 can be other geometries, as shown in Fig. 3 A to Fig. 3 C Polygon, and the side view of the corresponding electric contact mat 200 of side view (i.e. flat) of hollow-out parts 200a is (i.e. straight Shape), to obtain the hollow-out parts 300a of maximum area.
Therefore, the shape aspect in relation to the electric contact mat and hollow-out parts is various, however it is not limited to above-mentioned.
In conclusion board structure of the invention, mainly by forming hollow-out parts, and the hollow out on the electric contact mat The side view in portion corresponds to the side view of the electric contact mat, to reduce the rigidity of the electric contact mat, therefore in the substrate knot When structure stress, the torque to contend with produced by the electric contact mat substantially reduces, thus the substrate body will not be chipping Problem.
Above-described embodiment is only to be illustrated the principle of the present invention and its effect, and is not intended to limit the present invention.Appoint What those skilled in the art without departing from the spirit and scope of the present invention, modifies to above-described embodiment.Therefore originally The rights protection scope of invention, should be as listed in the claims.

Claims (12)

1. a kind of board structure, it is characterized in that, which includes:
One substrate body；
Multiple electric contact mats, respectively the electric contact mat is set in the substrate body and is the single knot with an at least hollow-out parts Structure, to enable the part of the surface of the substrate body expose to the hollow-out parts；And
Multiple conductive components are set on the respectively electric contact mat,
Wherein, this at least a hollow-out parts are located under the conductive component.
2. a kind of board structure, it is characterized in that, which includes:
One substrate body, and the substrate body is line construction；
Multiple electric contact mats, respectively the electric contact mat is directly contacted and is set on the line construction, and the respectively electric contact mat For the single structure with an at least hollow-out parts, to enable the part of the surface of the substrate body expose to the hollow-out parts；And
Multiple conductive components are set on the respectively electric contact mat,
Wherein, this at least a hollow-out parts are located under the conductive component.
3. a kind of board structure, it is characterized in that, which includes:
One substrate body, the substrate body include substrate and the line construction in the substrate；
Multiple electric contact mats, respectively the electric contact mat is directly contacted and is set on the line construction, and the respectively electric contact mat For the single structure with an at least hollow-out parts, to enable the part of the surface of the substrate body expose to the hollow-out parts, and the electrical property Engagement pad；And
Multiple conductive components are set on the respectively electric contact mat,
Wherein, this at least a hollow-out parts are located under the conductive component.
4. such as board structure according to claim 1 or 2, it is characterized in that, it is also electrical at least one in the substrate body Connect the conductive trace of the electric contact mat.
5. such as board structure according to claim 1 or 2, it is characterized in that, the upper view plane shape of the electric contact mat is Round or polygon.
6. such as board structure according to claim 1 or 2, it is characterized in that, which is located at the side of the electric contact mat Edge.
7. such as board structure according to claim 1 or 2, it is characterized in that, the side view of the hollow-out parts corresponds to the electrical property The side view of engagement pad.
8. such as board structure according to claim 7, it is characterized in that, the parallel electric contact mat of the lateral surface of the hollow-out parts Side.
9. such as board structure according to claim 7, it is characterized in that, the flat shape of the hollow-out parts is to have the ring-type of notch Or at least two interval sector.
10. such as board structure according to claim 7, it is characterized in that, the upper view plane shape of the electric contact mat is circle Shape or polygon.
11. such as board structure according to claim 1 or 2, it is characterized in that, further include insulating protective layer, is set to the base On plate ontology, and the insulating protective layer has aperture, and the electric contact mat is made to expose to the aperture.
12. such as board structure according to claim 1 or 2, it is characterized in that, which further includes being electrically connected with set on this Convex block underlying metal layer in touch pad.
CN201510652194.8A 2015-09-07 2015-10-10 Substrate structure Active CN106505059B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW104129480A TWI562256B (en) 2015-09-07 2015-09-07 Substrate structure
TW104129480 2015-09-07

Publications (2)

Publication Number Publication Date
CN106505059A CN106505059A (en) 2017-03-15
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