CN106505059A - Substrate structure - Google Patents
Substrate structure Download PDFInfo
- Publication number
- CN106505059A CN106505059A CN201510652194.8A CN201510652194A CN106505059A CN 106505059 A CN106505059 A CN 106505059A CN 201510652194 A CN201510652194 A CN 201510652194A CN 106505059 A CN106505059 A CN 106505059A
- Authority
- CN
- China
- Prior art keywords
- electric contact
- board structure
- contact mat
- hollow
- substrate body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 43
- 239000010410 layer Substances 0.000 claims description 17
- 238000010276 construction Methods 0.000 claims description 12
- 239000011241 protective layer Substances 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 18
- 238000004806 packaging method and process Methods 0.000 description 5
- 230000035882 stress Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000006062 fragmentation reaction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000013467 fragmentation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- XLTRGZZLGXNXGD-UHFFFAOYSA-N benzene;1h-pyrazole Chemical compound C=1C=NNC=1.C1=CC=CC=C1 XLTRGZZLGXNXGD-UHFFFAOYSA-N 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011469 building brick Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920002577 polybenzoxazole Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05011—Shape comprising apertures or cavities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05012—Shape in top view
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05012—Shape in top view
- H01L2224/05015—Shape in top view being circular or elliptic
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/05076—Plural internal layers being mutually engaged together, e.g. through inserts
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A substrate structure, comprising: the substrate structure comprises a substrate body and an electric contact pad arranged on the substrate body, wherein the electric contact pad is provided with at least one hollow part so that part of the surface of the substrate body is exposed out of the hollow part, and the rigidity of the electric contact pad is reduced, so that when the substrate structure is stressed, the counter torque generated by the electric contact pad is greatly reduced, and the problem of breakage of the substrate body is avoided.
Description
Technical field
The present invention relates to a kind of board structure, more particularly to a kind of with the in electrical contact of improvement
The board structure of pad.
Background technology
With the evolution of semiconductor packaging, semiconductor device (Semiconductor device)
Different encapsulation kenels have been developed.Wherein, sphere grid several-group type (Ball grid array, BGA),
Such as PBGA, EBGA, FCBGA etc., are a kind of advanced semiconductor packaging, its feature
Be semiconductor subassembly is disposed using a base plate for packaging, and put in base plate for packaging back side plant many
Several stannum balls (Solder ball) into the arrangement of palisade array, make the bearing part of same units area
On can accommodate more input/output connection ends (I/O connection) to meet height aggregation
(Integration) demand of semiconductor chip, and whole encapsulation unit welds by mat those stannum balls
Tie and be electrically connected to external electronic.
Additionally, compact, multi-functional, at high speed and high frequency in order to meet semiconductor package part
The developing way of change, semiconductor chip develop towards fine rule road and small-bore.
Fig. 1 is the cross-sectional schematic of existing semiconductor chip 1.As shown in Figure 1, there is provided a tool
There are the body 10 of multiple electric contact mats 100 and conductive trace 101, the body 10 that there is a base
The bottom 10a and line construction 10b in substrate 10a, and the electric contact mat 100
With conductive trace 101 on line construction 10b.Then, an insulating protective layer 11 is formed
On the chip body 10, on the insulating protective layer 11, multiple perforates 110 are formed, made each
The electric contact mat 100 correspondingly exposes to the respectively perforate 110.Afterwards, by metal under projection
Layer 130 forms multiple conductive components 13 such as soldered ball on the electric contact mat 100, leads this
Electrical component 13 is electrically connected with the electric contact mat 100, to complete existing chip package (Flip Chip
Package semiconductor chip 1).
In encapsulation making method, the semiconductor chip 1 by reflow those conductive components 13 with
It is bound on base plate for packaging (figure is omited), now, the semiconductor chip 1 is subjected to external force, example
Such as, reflow oven can produce thermal stress to the inside of the semiconductor chip 1.
But, when the inside of the semiconductor chip 1 produces thermal stress, the electric contact mat 100
There is extremely strong rigidity because which is shaped as solid disk (as shown in Fig. 1 '), therefore this is electrically connected with
Touch pad 100 can produce the torque for contending with to the thermal stress, especially in the electric contact mat 100
Edge produced by the torque that contends with maximum, cause positioned at the electric contact mat 100
Line construction 10b near edge because bearing excessive stresses and fragmentation (Crack), such as Fig. 1 institutes
K at the fragmentation that shows.
Therefore, how to overcome above-mentioned problem of the prior art, real into desiring most ardently asking for solution at present
Topic.
Content of the invention
In view of the various shortcoming of above-mentioned prior art, the present invention provides a kind of board structure, to keep away
Exempt from the problem of the substrate body rupture.
The board structure of the present invention includes：Substrate body；And electric contact mat, which is located at this
In substrate body and with least hollow-out parts, to make the part surface of the substrate body expose to
The hollow-out parts.
In aforesaid board structure, the substrate body is line construction.
In aforesaid board structure, the substrate body includes substrate and located at the suprabasil line
Line structure, and the electric contact mat is on the line construction.
In aforesaid board structure, also there is at least one electric connection in the substrate body, and this is electrical
The conductive trace of engagement pad.
In aforesaid board structure, the upper view plane of the electric contact mat is generally circular in shape or polygon
Shape.
In aforesaid board structure, the hollow-out parts are located at the edge of the electric contact mat.
In aforesaid board structure, and the side view of the hollow-out parts is to should electric contact mat
Side view.For example, the side of the parallel electric contact mat of the lateral surface of the hollow-out parts；Or,
The flat shape of the hollow-out parts is the sector at ring-type or at least two intervals for having breach；Or, should
The upper view plane of electric contact mat is generally circular in shape or polygon.
In aforesaid board structure, also include insulating protective layer, in the substrate body, and
The insulating protective layer has perforate, makes the electric contact mat expose to the perforate.
In aforesaid board structure, also include the conductive component on the electric contact mat.
In aforesaid board structure, also include located at metal under the projection on the electric contact mat
Layer.
From the foregoing, it will be observed that the board structure of the present invention, by the design of the hollow-out parts, makes this electrical
The rigidity of engagement pad diminishes, therefore compared to prior art, when the board structure stress, the electricity
Property engagement pad will not be too strong and produce the excessive torque for contending with the substrate body because of rigidity
On, therefore it is avoided that the problem of the substrate body rupture.
Description of the drawings
Fig. 1 is the cross-sectional schematic of existing semiconductor chip；
Fig. 1 ' is the upper viewing view of existing electric contact mat；
Fig. 2 is the cross-sectional schematic of the board structure of the present invention；
Cross-sectional schematics of the Fig. 2 ' for another embodiment of Fig. 2；
Fig. 2A to Fig. 2 I is the first embodiment of the electric contact mat of the board structure of the present invention
The upper viewing view of various embodiments；And
Fig. 3 A to Fig. 3 C are the second embodiment of the electric contact mat of the board structure of the present invention
The upper viewing view of various embodiments.
Description of reference numerals：
1 semiconductor chip
10 bodies
10a, 20a substrate
10b, 20b line construction
100,200,300 electric contact mats
101,201 conductive traces
11,21 insulating protective layers
110,210 perforates
13,23 conductive components
130,230 projection underlying metal layers
2 board structures
20,20 ' substrate bodies
200a, 300a hollow-out parts
At K fragmentations
R sides
S lateral surface.
Specific embodiment
Embodiments of the present invention, art technology are described below by way of particular specific embodiment
Personnel can be understood other advantages and the work(of the present invention easily by content disclosed in the present specification
Effect.
It should be clear that structure, ratio, size depicted in this specification institute accompanying drawing etc., only in order to
Coordinate the content disclosed in description, for the understanding and reading of those skilled in the art, not
In order to limit enforceable qualificationss of the invention, therefore do not have technical essential meaning, any
The modification of structure, the change of proportionate relationship or the adjustment of size, can produce the present invention is not affected
Under raw effect and the purpose that can reach, still all should fall in disclosed technology contents
Obtain in the range of covering.Meanwhile, in this specification cited such as " on " and " one " etc.
Term, be also only and be easy to described to understand, and be not used to limit enforceable scope of the invention,
Its relativeness is altered or modified, under without essence change technology contents, when being also considered as this
Bright enforceable category.
Fig. 2 is the cross-sectional schematic of the board structure 2 of the present invention.As shown in Fig. 2 the substrate
Structure 2 includes：One substrate body 20, the multiple electric contact mats in the substrate body 20
200th, multiple conductive traces 201 and an insulating protective layer 21.
Described substrate body 20 includes line construction, for example, wiring board, and which has multiple
Dielectric layer and multiple line layers, and the electric contact mat 200 and the conductive trace 201 are located at most
On the dielectric layer of outer layer and it is electrically connected with the line layer.
In another embodiment, such as shown in Fig. 2 ', the substrate body 20 ' includes a substrate
The 20a and line construction 20b in substrate 20a, and the electric contact mat 200 is located at
On line construction 20b.For example, substrate 20a be semiconductor substrate, such as wafer, chip,
There is intermediate plate of silicon perforation (Through-Silicon Via, abbreviation TSV) etc., and the line
Line structure 20b has multiple dielectric layers (figure is omited) and multiple circuit redistribution layer (redistribution
Layer, abbreviation RDL) (figure is omited), and the electric contact mat 200 and the conductive trace 201
It is located on outermost dielectric layer and is electrically connected with the circuit redistribution layer or the electric contact mat
200 with the conductive trace 201 as circuit redistribution layer a part.
Described electric contact mat 200 is electrically connected with the conductive trace 201, and the electric contact mat
200 have at least hollow-out parts 200a, to make the substrate body 20 (or line construction 20b)
Part surface expose to hollow-out parts 200a.
In the present embodiment, hollow-out parts 200a are located at the edge of the electric contact mat 200, but
The side R (as shown in Figure 2 A) of the electric contact mat 200 is not connected.
Additionally, the forming method of hollow-out parts 200a is etching or the laser electric contact mat 200；
Or, can the electric contact mat 200 of Direct Electroplating or coating formation with hollow-out parts 200a.
Further, since respectively around the electric contact mat 200 and conductive trace 201 and thereon
Structure all same, therefore single electric contact mat 200 and conductive trace 201 is only illustrated in schema
To explain, state clearly hereby.
Described insulating protective layer 21 has the perforate 210 for correspondingly exposing the electric contact mat 200.
For example, the material of the insulating protective layer 21 is anti-wlding or dielectric material, such as pi
(Polyimide, abbreviation PI), benzocyclobutene (Benezocy-clobutene, referred to as
BCB) or poly- to diazole benzene (Polybenzoxazole, abbreviation PBO).
In addition, described board structure 2 also includes the conductive component 23 in the perforate 210,
Which is electrically connected with the electric contact mat 200.
In the present embodiment, the conductive component 23 is soldered ball, metal derby etc., makes the board structure
2 combine other electronic building bricks (figure is omited), for example, semiconductor die by those conductive components 23
Circle, chip, the intermediate plate or wiring board with silicon perforation.
Additionally, a projection underlying metal layer (Under can be initially formed under the conductive component 23
Bump Metallurgy, abbreviation UBM) 230, the conductive component 23 is more firmly incorporated into
On the electric contact mat 200.
The board structure 2 of the present invention is by forming hollow-out parts 200a in the electric contact mat 200
On, make the rigidity of the electric contact mat 200 diminish, when 2 stress of board structure, especially
When being thermal stress and warpage occurring, the electric contact mat 200 will not be produced because rigidity is too strong
The excessive torque for contending with therefore is avoided that the substrate body in the substrate body 20 on 20 '
20,20 ' line layer or the problem of RDL fractures.
Additionally, the area of hollow-out parts 200a is bigger, then the stress of the electric contact mat 200 changes
Kind effect is better, i.e., the electric contact mat 200 has preferably elasticity and flexibility.As schemed
Shown in 2A to Fig. 2 H, when the upper view plane of the electric contact mat 200 is generally circular in shape, this is engraved
The side view (i.e. arcuation) of empty portion 200a to should electric contact mat 200 side view (i.e.
Arcuation), to make the flat shape of hollow-out parts 200a be formed such as the fan-shaped or class at least two intervals
Like sector, and it is preferred that parallel electric contact mats 200 of the lateral surface S of hollow-out parts 200a
Side R, use hollow-out parts 200a for obtaining maximum area.
It is preferred that compared to existing electric contact mat, the face of hollow-out parts 200a shown in Fig. 2 E
Product is larger, causes the torque produced by which less, the power produced by about only existing electric contact mat
The 92% of square.
Also, the flat shape of hollow-out parts 200a can also form the annular of tool breach, such as Fig. 2 I
Shown, 92% of torque produced by the about only existing electric contact mat of torque produced by which.
In addition, the upper view plane shape of the electric contact mat 300 can be other geometries, such as
Polygon shown in Fig. 3 A to Fig. 3 C, and the side view (i.e. flat) of hollow-out parts 200a
To should electric contact mat 200 side view (i.e. flat), to obtain maximum area
Hollow-out parts 300a.
Therefore, various with the shape aspect of hollow-out parts about the electric contact mat, however it is not limited on
State.
In sum, board structure of the invention, main by being formed on the electric contact mat
Hollow-out parts, and the side view of the hollow-out parts to should electric contact mat side view, to subtract
The rigidity of the little electric contact mat, therefore when the board structure stress, the electric contact mat is produced
The torque that life contends with significantly reduces, thus the problem that the substrate body will not be chipping.
Principle and its effect of the above-described embodiment only in order to the illustrative present invention, not for
Limit the present invention.Any those skilled in the art can be in the spirit and the scope without prejudice to the present invention
Under, above-described embodiment is modified.Therefore the scope of the present invention, should be such as right
Listed by claim.
Claims (13)
1. a kind of board structure, it is characterized by, the board structure includes：
One substrate body；And
Multiple electric contact mats, its are located in the substrate body and there are at least hollow-out parts, with
The part surface of the substrate body is made to expose to the hollow-out parts.
2. board structure as defined in claim 1, it is characterized by, the substrate body is
Line construction.
3. board structure as defined in claim 1, it is characterized by, the substrate body bag
Containing substrate and located at the suprabasil line construction, and the electric contact mat is located at circuit knot
On structure.
4. board structure as defined in claim 1, it is characterized by, in the substrate body
Also there is at least one conductive trace for being electrically connected with the electric contact mat.
5. board structure as defined in claim 1, it is characterized by, the electric contact mat
Upper view plane is generally circular in shape or polygon.
6. board structure as defined in claim 1, it is characterized by, the hollow-out parts are located at
The edge of the electric contact mat.
7. board structure as defined in claim 1, it is characterized by, the side of the hollow-out parts
Face shape to should electric contact mat side view.
8. such as board structure according to claim 7, it is characterized by, outside the hollow-out parts
The side of the parallel electric contact mat in side.
9. such as board structure according to claim 7, it is characterized by, the hollow-out parts flat
Face is shaped as the sector at the ring-type for having breach or at least two intervals.
10. such as board structure according to claim 7, it is characterized by, the electric contact mat
Upper view plane is generally circular in shape or polygon.
11. board structures as defined in claim 1, it is characterized by, also include that insulation is protected
Sheath, its are located in the substrate body, and the insulating protective layer has perforate, are electrically connected with this
Touch pad exposes to the perforate.
12. board structures as defined in claim 1, it is characterized by, the board structure is also
Including the conductive component on the electric contact mat.
13. board structures as defined in claim 1, it is characterized by, the board structure is also
Including the projection underlying metal layer on the electric contact mat.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104129480A TWI562256B (en) | 2015-09-07 | 2015-09-07 | Substrate structure |
| TW104129480 | 2015-09-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106505059A true CN106505059A (en) | 2017-03-15 |
| CN106505059B CN106505059B (en) | 2019-11-08 |
Family
ID=58227341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510652194.8A Active CN106505059B (en) | 2015-09-07 | 2015-10-10 | Substrate structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106505059B (en) |
| TW (1) | TWI562256B (en) |
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| US20240049382A1 (en) * | 2022-08-04 | 2024-02-08 | Siliconware Precision Industries Co., Ltd. | Carrier structure |
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| US12219693B2 (en) * | 2022-08-04 | 2025-02-04 | Siliconware Precision Industries Co., Ltd. | Carrier structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106505059B (en) | 2019-11-08 |
| TW201711111A (en) | 2017-03-16 |
| TWI562256B (en) | 2016-12-11 |
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