CN106449635A - Novel low-trigger-voltage silicon-controlled rectifier and manufacturing method therefor - Google Patents

Abstract

The invention discloses a novel low-trigger voltage silicon-controlled rectifier and a manufacturing method thereof. The rectifier comprises: a semiconductor substrate; an N well (50) formed on one side of the substrate and a P well (60) on the other side; The equivalent PNP triode structure formed by doping in the N well (50) and the equivalent NPN triode structure formed by doping in the P well (60); the heavy weight inserted between the N well and the P well Doped N junction; the ESD implantation layer (40) formed in the P well region below the N junction, the present invention passes the N junction below the N well and the P well of the existing silicon controlled rectifier An additional P-type heavily doped ESD_IMP is added to the P well region, so that the N junction and the ESD_IMP below it form a vertical N+/P+ diode, thereby further reducing the reverse breakdown voltage of the N well to the P well, further reducing The trigger voltage for the hysteresis effect of the thyristor.

Description

A novel low trigger voltage silicon-controlled rectifier and its manufacturing method

technical field

The invention relates to the technical field of semiconductor integrated circuits, in particular to a novel low-trigger voltage silicon-controlled rectifier (SCR) and a manufacturing method thereof.

Background technique

In the field of ESD protection design, silicon-controlled rectifiers (SCR) have been widely valued because of their strong ESD leakage capability, but there are two serious defects in this type of device that limit their applications: the first defect is the snapback (hysteresis effect) ) The trigger voltage is very high, because its trigger voltage is mainly limited by the reverse breakdown voltage of the N well to the P well; latch-up effect.

In view of the first defect above, the industry has proposed some solutions to reduce the trigger voltage of snapback (hysteresis effect). Fig. 1 is a schematic structural view of a silicon-controlled rectifier (SCR) in the prior art. As shown in Fig. 1, the silicon-controlled rectifier (SCR) includes a plurality of shallow trench isolation layers (STI, Shallow Trench Isolation) 10, high Concentration N-type doping (N+) 20, high-concentration P-type doping (P+) 22, high-concentration N-type doping (N+) 24, high-concentration N-type doping (N+) 26, high-concentration P-type doping ( P+) 28, N well (N-Well) 50, P well (P-Well) 60, substrate (Psub) 70.

The whole device is placed on the substrate (Psub) 70, an N well (N-Well) 50 is formed on the left side of the substrate (Psub) 70, and a P well (P-Well) 60 is formed on the right side of the substrate (Psub) 70, and the high concentration N Type doping (N+) 20, high-concentration P-type doping (P+) 22 are placed on the upper part of N well (N-Well) 50, high-concentration P-type doping (P+) 22, N well (N-Well) 50 and Substrate (Psub) 70 constitutes an equivalent PNP transistor structure, high-concentration N-type doping (N+) 20 and N well (N-Well) 50 form a diffusion resistance equivalently connected to the base of the PNP transistor, and high-concentration P-type doping (P+) 22 and N well (N-Well) 50 constitute the emitter PN junction of the PNP transistor, and the substrate (Psub) 70 and N well (N-Well) 50 constitute the collector PN junction of the PNP transistor. High concentration N Type doping (N+) 26, high-concentration P-type doping (P+) 28 are placed on the top of P well (P-Well) 60, N well (N-Well) 50, substrate (Psub) 70 and high-concentration N-type doping The heterogeneous (N+) 26 constitutes an equivalent NPN triode structure, the N well (N-Well) 50 and the substrate (Psub) 70 constitute the collector PN junction of the NPN transistor, the substrate (Psub) 70 and the high-concentration N-type doped (N+ ) 26 constitutes the emitter PN junction of an equivalent NPN triode, high-concentration P-type doping (P+) 26, P-well (P-Well) 60, and substrate (Psub) 70 form a diffusion resistor connected to the base of the equivalent NPN triode High-concentration N-type doping (N+) 24 placed above the boundary between N-well (N-Well) 50 and P-well (P-Well) 60, high-concentration N-type doping (N+) 20, high-concentration P-type Shallow trench isolation layer (STI, Shallow Trench Isolation) 10 isolation; use metal to connect high-concentration N-type doping (N+) 20, high-concentration P-type doping (P+) 22 to form the anode A of this new low trigger voltage silicon-controlled ESD device, high-concentration N-type doping (N+) 26 and high-concentration P-type doping (P+) 28 are the cathode K of the novel low trigger voltage silicon-controlled ESD device of the present invention.

The silicon-controlled rectifier inserts a heavily doped N junction (high concentration N-type doping (N+) 24) across the N well and the P well between the N well and the P well, thereby reducing the N well to P well The purpose of the reverse breakdown voltage, but the reverse breakdown voltage of the N junction to the P well is still relatively high.

In order to further reduce the trigger voltage, another prior art silicon-controlled rectifier (SCR) type ESD device moves the high-concentration N-type doping (N+) 26 and high-concentration P-type doping (P+) 28 on the right to the right, As shown in Figure 2, an N-type gate-controlled diode 30 is added above the newly vacated P-well (P-Well) 60, and connected to the cathode K of the silicon-controlled rectifier (SCR), so as to further reduce the N-well For the purpose of the reverse breakdown voltage of the P well, but even so, the trigger voltage of the silicon controlled rectifier shown in Figure 2 is still relatively high, and the trigger voltage is also limited by the existing process parameters, and the degree of freedom of adjustment is limited. big.

Contents of the invention

In order to overcome the deficiencies in the above-mentioned prior art, the object of the present invention is to provide a novel low trigger voltage silicon-controlled rectifier and its manufacturing method, which uses the N-junction between the N-well and the P-well of the existing silicon-controlled rectifier An additional P-type heavily doped ESD_IMP is added to the P well region below, so that the N junction and the ESD_IMP below it form a vertical N+/P+ (ESD_IMP) diode, thereby further reducing the N well to P well. to the breakdown voltage.

In order to achieve the above and other purposes, the present invention proposes a novel low-trigger voltage silicon-controlled rectifier, which includes:

semiconductor substrate;

An N well (50) on one side and a P well (60) on the other side formed in the semiconductor substrate (70);

An equivalent PNP transistor structure formed by doping in the N well (50) and an equivalent NPN transistor structure formed by doping in the P well (60);

a heavily doped N-junction interposed between the N-well and the P-well;

An ESD implantation layer (40) is formed in the P well region below the N junction.

Further, high-concentration N-type doping (20), high-concentration P-type doping (22) are placed on the upper part of the N well (50), high-concentration P-type doping (P+) 22, N well (N-Well ) 50 and the substrate (Psub) 70 form an equivalent PNP transistor structure.

Further, the high-concentration N-type doping (20) and the N well (50) form a diffusion resistance equivalently connected to the base of the PNP transistor, and the high-concentration P-type doping (22) and the N The well (50) constitutes the emitter PN junction of the PNP transistor, and the base body and the N well (50) constitute the collector PN junction of the PNP transistor.

Further, placing high-concentration N-type doping (26) and high-concentration P-type doping (28) on the upper part of the P well (60), the N well (50), the base body and the high-concentration N-type Doping (26) constitutes the equivalent NPN triode structure.

Further, the N well (50) and the substrate constitute the collector PN junction of the NPN transistor, and the substrate 70 and the high-concentration N-type doping (26) constitute the emitter of the equivalent NPN transistor The PN junction, the high-concentration P-type doping (28), the P well (60), and the substrate form a diffused resistor connected to the base of the equivalent NPN transistor.

Further, between the high-concentration N-type doping (20), high-concentration P-type doping (22), the N junction, high-concentration N-type doping (26), and high-concentration P-type doping (28) The shallow trench isolation layer 10 is used for isolation.

Further, the silicon controlled rectifier adjusts the N+/P+ (ESD_IMP) diode in the vertical direction formed by the N junction and the ESD implant layer (40) by adjusting the dose of the ESD_IMP of the ESD implant layer (40). reverse breakdown voltage.

In order to achieve the above object, the present invention also provides a manufacturing method of a novel low trigger voltage silicon-controlled rectifier, comprising the following steps:

Step 1, providing a semiconductor substrate (70);

Step 2, generating an N well (50) on one side of the semiconductor substrate (70), and generating a P well (60) on the other side of the substrate (70);

Step 3, forming an equivalent PNP transistor structure by doping in the N well (50), and forming an equivalent NPN transistor structure by doping in the P well (60);

Step 4, inserting a heavily doped N junction across the N well (50) and the P well (60) between the N well (50) and the P well;

Step five, add an ESD implantation layer (40) in the P well region below the N junction.

Further, in step 5, adjust the reverse strike of the N+/P+ diode in the vertical direction formed by the N junction and the ESD implant layer (40) by adjusting the dose of the ESD_IMP of the ESD implant layer (40) wear voltage.

Further, the optimal ESD_IMP dose is determined according to the trigger voltage and leakage current performance of the silicon controlled rectifier.

Compared with the prior art, the present invention is a novel low-trigger voltage silicon controlled rectifier and its manufacturing method, which additionally adds a P well region under the N junction between the N well and P well of the existing silicon controlled rectifier A P-type heavily doped ESD_IMP makes the N junction and the ESD_IMP below it form a vertical N+/P+ (ESD_IMP) diode, thereby further reducing the reverse breakdown voltage of the N well to the P well.

Description of drawings

Fig. 1 is a structural schematic diagram of a silicon controlled rectifier in the prior art;

FIG. 2 is a schematic structural diagram of another silicon controlled rectifier in the prior art;

Fig. 3 is a circuit structure diagram of a preferred embodiment of a novel low-trigger voltage silicon-controlled rectifier of the present invention;

Fig. 4 is the flow chart of the steps of the manufacturing method of a novel low trigger voltage silicon controlled rectifier of the present invention;

FIG. 5 is a schematic diagram of an application scenario of the present invention.

detailed description

The implementation of the present invention is described below through specific examples and in conjunction with the accompanying drawings, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

FIG. 3 is a circuit structure diagram of a preferred embodiment of a novel low-trigger voltage silicon-controlled rectifier of the present invention. As shown in FIG. 3 , a novel low-trigger voltage silicon-controlled rectifier (SCR) of the present invention includes a substrate (Psub) 70, and an N-well (N-Well) 50 is formed on one side of the substrate (Psub) 70, and on the substrate ( A P well (P-Well) 60 is formed on the other side of the Psub) 70. In a preferred embodiment of the present invention, the N well 50 is arranged on the left side of the substrate (Psub) 70, and the P well (P-Well) 60 is arranged on the substrate ( On the right side of Psub) 70, high-concentration N-type doping (N+) 20 and high-concentration P-type doping (P+) 22 are placed on the upper part of N well (N-Well) 50, and high-concentration P-type doping (P+) 22, N The well (N-Well) 50 and the substrate (Psub) 70 form an equivalent PNP transistor structure, and the high-concentration N-type doping (N+) 20 and the N-well (N-Well) 50 form a diffusion resistance that is equivalently connected to the PNP transistor base. High-concentration P-type doping (P+) 22 and N well (N-Well) 50 constitute the emitter PN junction of the PNP transistor, and the substrate (Psub) 70 and N well (N-Well) 50 constitute the junction of the PNP transistor Collector PN junction, high-concentration N-type doping (N+) 26, high-concentration P-type doping (P+) 28 are placed on the upper part of P well (P-Well) 60, N well (N-Well) 50, substrate (Psub ) 70 and high-concentration N-type doping (N+) 26 form an equivalent NPN transistor structure, N well (N-Well) 50 and substrate (Psub) 70 constitute the collector PN junction of the NPN transistor, substrate (Psub) 70 and High-concentration N-type doping (N+) 26 constitutes the emitter PN junction of an equivalent NPN transistor, and high-concentration P-type doping (P+) 26, P-well (P-Well) 60, and substrate (Psub) 70 constitute a diffusion resistance connection To the base of the equivalent NPN transistor, high-concentration N-type doping (N+) 24 is placed on the upper part of the boundary between N well (N-Well) 50 and P well (P-Well) 60, and high-concentration N-type doping ( N+) 20, high concentration P-type doping (P+) 22, high concentration N-type doping (N+) 24, high concentration N-type doping (N+) 26, high concentration P-type doping (P+) 28 Trench isolation layer (STI, Shallow Trench Isolation) 10 isolation, ESD implantation layer (ESD_IMP) 40 is placed under the part of high-concentration N-type doping (N+) 24 located in P well (P-Well) 60, relatively Preferably, in order to ensure that there are all ESD_IMPs in the P well below the N+, it is best to exceed the right boundary of the high-concentration N-type doping (N+) 24 by about 0.5um; use metal to connect the high-concentration N-type doping (N+) 20, high Concentration P-type doping (P+) 22 constitutes the anode A of the novel low-trigger voltage silicon-controlled rectifier, and high-concentration N-type doping (N+) 26 and high-concentration P-type doping (P+) 28 are the novel low trigger voltage of the present invention. The cathode K of the voltage silicon controlled rectifier.

It can be seen that, on the basis of the silicon controlled rectifier (Fig. 1) of the prior art, the present invention additionally adds a heavily doped ESD_IMP in the P well region below the N junction between the N well/P well, to control the ESD_IMP The energy ensures that it is located under the N junction, and the present invention can adjust the reverse breakdown voltage of the N+/P+ diode by adjusting the dose of ESD_IMP. In a preferred embodiment of the present invention, the energy range of the ESD IMP: can be written as 10Kev-100Kev, and the dose range of the ESD IMP: 1.0E11cm ^-2 -1.0E16cm ^-2 .

It should be noted here that the ESD_IMP location can only be located in the P-well region below the N-junction, but cannot cover the entire N-junction. The optimal ESD_IMP dose can be determined according to the trigger voltage and leakage current performance of the silicon controlled rectifier.

FIG. 4 is a flow chart of the steps of a manufacturing method of a novel low-trigger voltage silicon-controlled rectifier according to the present invention. As shown in Figure 4, a method for manufacturing a novel low-trigger voltage silicon-controlled rectifier of the present invention comprises the following steps:

Step 401 , providing a semiconductor substrate (Psub) 70 .

Step 402, generate an N well (N-Well) 50 on one side of the semiconductor substrate (Psub) 70, and generate a P well (P-Well) 60 on the other side of the substrate (Psub) 70, preferably in the present invention In the embodiment, the N well 50 is disposed on the left side of the substrate (Psub) 70 , and the P well (P-Well) 60 is disposed on the right side of the substrate (Psub) 70 .

Step 403 , forming an equivalent PNP transistor structure on the top of the N well 50 by doping, and forming an equivalent PNP transistor structure on the top of the P well 60 by doping. Specifically, high-concentration N-type doping (N+) 20 and high-concentration P-type doping (P+) 22 are placed on the upper part of N well (N-Well) 50, and high-concentration P-type doping (P+) 22, N The well (N-Well) 50 and the substrate (Psub) 70 form an equivalent PNP transistor structure, and the high-concentration N-type doping (N+) 20 and the N-well (N-Well) 50 form a diffusion resistance that is equivalently connected to the PNP transistor base. High-concentration P-type doping (P+) 22 and N well (N-Well) 50 constitute the emitter PN junction of the PNP transistor, and the substrate (Psub) 70 and N well (N-Well) 50 constitute the junction of the PNP transistor Collector PN junction, high-concentration N-type doping (N+) 26, high-concentration P-type doping (P+) 28 are placed on the upper part of P well (P-Well) 60, N well (N-Well) 50, substrate ( Psub) 70 and high-concentration N-type doping (N+) 26 constitute an equivalent NPN transistor structure, N well (N-Well) 50 and substrate (Psub) 70 constitute the collector PN junction of the NPN transistor, substrate (Psub) 70 It forms the emitter PN junction of an equivalent NPN transistor with high-concentration N-type doping (N+) 26, and high-concentration P-type doping (P+) 26, P-well (P-Well) 60, and substrate (Psub) 70 form a diffusion resistance Connected to the base of the equivalent NPN transistor, between high-concentration N-type doping (N+) 20, high-concentration P-type doping (P+) 22 and high-concentration N-type doping (N+) 26, high-concentration P-type Doping (P+) 28 is isolated by shallow trench isolation layer (STI, Shallow Trench Isolation) 10

Step 404 , inserting a heavily doped N junction across the N well and the P well between the N well 50 and the P well 60 . That is, the high-concentration N-type doping (N+) 24 is placed on the upper part of the boundary between the N-well (N-Well) 50 and the P-well (P-Well) 60, and the high-concentration P-type doping (P+) 22 and the high-concentration Shallow Trench Isolation (STI, Shallow Trench Isolation) 10 is used to isolate between N-type doped (N+) 24 and between high-concentration N-type doped (N+) 24 and high-concentration N-type doped (N+) 26 .

Step 405, adding an ESD implant layer (ESD_IMP) 40 to the P well region below the N junction, the ESD implant layer (ESD_IMP) 40 can only be located in the P well region below the N junction, and cannot cover the entire N junction, The energy guarantee period for controlling the ESD IMP is located below the N junction, and the reverse breakdown voltage of the N+/P+ diode can be adjusted by adjusting the dose of ESD_IMP, which can be determined according to the trigger voltage and leakage current performance of the new silicon controlled rectifier Optimal ESD IMP dosage.

Step 406, using metal to connect high-concentration N-type doping (N+) 20 and high-concentration P-type doping (P+) 22 to form the anode A of the new low trigger voltage silicon controlled rectifier, and high-concentration N-type doping (N+) 26 1. The high-concentration P-type doping (P+) 28 is the cathode K of the novel low-trigger voltage silicon-controlled rectifier.

The new low trigger voltage silicon controlled rectifier of the present invention can be applied to the protection circuit of the input and output terminals and the protection circuit of the power supply to ground in the ESD protection circuit to improve the overall ESD protection capability of the chip, as shown in FIG. 5 .

In summary, the present invention is a novel low-trigger voltage silicon-controlled rectifier and its manufacturing method, which adds an additional P well region below the N junction between the N well and P well of the existing silicon controlled rectifier. The type of heavily doped ESD_IMP makes the N junction and the ESD_IMP below it form a vertical N+/P+ diode, thereby further reducing the reverse breakdown voltage of the N well to the P well.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Any person skilled in the art can modify and change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be listed in the claims.

Claims (10)

1. A novel low trigger voltage silicon-controlled rectifier, characterized in that the rectifier comprises: semiconductor substrate (70); An N well (50) on one side and a P well (60) on the other side formed in the semiconductor substrate (70); An equivalent PNP transistor structure formed by doping in the N well (50) and an equivalent NPN transistor structure formed by doping in the P well (60); a heavily doped N-junction (24) interposed between said N-well and said P-well; An ESD implantation layer (40) is formed in the P well region below the N junction (24). 2. a kind of novel low trigger voltage silicon-controlled rectifier as claimed in claim 1 is characterized in that: high-concentration N-type doping (20), high-concentration P-type doping (22) are placed in described N well (50) ), high-concentration P-type doping (P+) 22, N-well (N-Well) 50 and substrate (Psub) 70 form an equivalent PNP transistor structure. 3. A novel low-trigger voltage silicon-controlled rectifier as claimed in claim 2, characterized in that: the high-concentration N-type doping (20) and the N-well (50) form a diffusion resistance equivalently connected to the The base of the PNP transistor, the high-concentration P-type doping (22) and the N well (50) constitute the emitter PN junction of the PNP transistor, and the base and the N well (50) constitute the PNP transistor. collector PN junction. 4. a kind of novel low trigger voltage silicon-controlled rectifier as claimed in claim 3 is characterized in that: high-concentration N-type doping (26), high-concentration P-type doping (28) are placed in described P well ( 60) In the upper part, the N well (50), the base body and the high-concentration N-type doping (26) form the equivalent NPN triode structure. 5. A novel low-trigger voltage silicon-controlled rectifier as claimed in claim 4, characterized in that: said N well (50) and said substrate constitute the collector PN junction of the NPN triode, said substrate 70 and said substrate The high-concentration N-type doping (26) constitutes the emitter PN junction of the equivalent NPN transistor, and the high-concentration P-type doping (26), the P well (60), and the substrate form a diffusion resistor connected to the equivalent NPN transistor. The base of the NPN transistor. 6. a kind of novel low trigger voltage silicon-controlled rectifier as claimed in claim 5 is characterized in that: described high-concentration N-type doping (20), high-concentration P-type doping (22), described N junction ( 24), high-concentration N-type doping (26), and high-concentration P-type doping (28) are isolated by a shallow trench isolation layer (10). 7. a kind of novel low trigger voltage silicon-controlled rectifier as claimed in claim 6 is characterized in that: described silicon-controlled rectifier adjusts this N junction and this The reverse breakdown voltage of the N+/P+ (ESD_IMP) diode in the vertical direction formed by the ESD implant layer (40). 8. A method for manufacturing a novel low-trigger voltage silicon-controlled rectifier, comprising the steps of: Step 1, providing a semiconductor substrate (70); Step 2, generating an N well (50) on one side of the semiconductor substrate (70), and generating a P well (60) on the other side of the substrate (70); Step 3, forming an equivalent PNP transistor structure by doping in the N well (50), and forming an equivalent NPN transistor structure by doping in the P well (60); Step 4, inserting a heavily doped N junction across the N well (50) and the P well (60) between the N well (50) and the P well; Step five, add an ESD implantation layer (40) in the P well region below the N junction. 9. the manufacture method of a kind of novel low trigger voltage silicon-controlled rectifier as claimed in claim 8 is characterized in that: in step 5, adjust this N by adjusting the dosage of the ESD_IMP of described ESD implant layer (40) The reverse breakdown voltage of the N+/P+ (ESD_IMP) diode in the vertical direction formed by the junction and the ESD implant layer (40). 10. The manufacturing method of a novel low-trigger voltage silicon-controlled rectifier according to claim 9, wherein the optimum ESD_IMP dose is determined according to the trigger voltage and leakage current performance of the silicon-controlled rectifier.