CN107369682B - A new silicon controlled rectifier type ESD protection structure and its realization method - Google Patents

Abstract

The invention discloses a novel silicon-controlled rectifier type ESD protection structure and its realization method. The structure comprises: a semiconductor substrate (80); an N well (60) and a P well (70) formed on the semiconductor substrate; a high-concentration P Type doping (20), high-concentration N-type doping (28) is placed on the upper part of N well (60), and high-concentration P-type doping (20), N well (60) and P well (70) constitute an equivalent PNP Triode structure, high-concentration N-type doping (24), high-concentration P-type doping (26) placed on the upper part of P well (70), N well (60), matrix (80) and high-concentration N-type doping (24 ) constitutes an equivalent NPN triode structure, high-concentration N-type doping (22) is placed above the boundary between N-well (60) and P-well (70), high-concentration N-type doping (22) and high-concentration N-type doping An N-type gate (50) is placed above the (24), and the present invention can increase the sustaining voltage of the hysteresis effect of the ESD protection structure.

Description

A new silicon controlled rectifier type ESD protection structure and its realization method

technical field

The invention relates to the technical field of semiconductor integrated circuits, in particular to a novel silicon-controlled rectifier type ESD protection structure with low trigger voltage and high sustain voltage and its realization method.

Background technique

In the field of electrostatic (ESD, Electro-Static Discharge) protection design, Silicon Controlled Rectifier (SCR, Silicon Controlled Rectifier) has been widely valued because of its strong ESD discharge capability and small parasitic capacitance. Serious defects limit its application: the first defect is that the trigger voltage of the hysteresis effect is very high, because its trigger voltage is mainly determined by the high reverse breakdown voltage between the N well and the P well; the second defect is that the hysteresis effect The holding voltage of the hysteresis effect is very low, which can easily lead to latch-up effect.

Aiming at the defect of high trigger voltage, the industry has proposed various schemes to reduce the trigger voltage of the hysteresis effect, such as the silicon controlled rectifier type ESD protection structure shown in FIG. 1 and FIG. 2 .

The silicon controlled rectifier type ESD protection structure shown in Figure 1 is to insert an N-type heavy doping across the N well and P well between the N well and the P well, so as to reduce the reverse breakdown of the N well to the P well voltage purpose, thereby reducing the trigger voltage for the hysteresis effect. Specifically, the silicon-controlled rectifier (SCR) type shown in FIG. 1 includes a plurality of shallow trench isolation layers (STI, Shallow Trench Isolation) 10, high-concentration N-type doping (N+) 20, high-concentration P-type doping ( P+) 22, high-concentration N-type doping (N+) 24, high-concentration N-type doping (N+) 26, high-concentration P-type doping (P+) 28, N well (N-Well) 50, P well (P - Well) 60, Substrate (Psub) 70.

The entire ESD protection structure is placed on the substrate (Psub) 70, an N well (N-Well) 50 is formed on the left side of the substrate (Psub) 70, and a P well (P-Well) 60 is formed on the right side of the substrate (Psub) 70, with a high Concentration N-type doping (N+) 20, high-concentration P-type doping (P+) 22 are placed on the upper part of N well (N-Well) 50, high-concentration P-type doping (P+) 22, N well (N-Well) 50 and the substrate (Psub) 70 form an equivalent PNP transistor structure, and the high-concentration N-type doping (N+) 20 and the N-well (N-Well) 50 form a diffusion resistance equivalently connected to the base of the PNP transistor, and the high-concentration P-type The doping (P+) 22 constitutes the emitter of the PNP transistor, the substrate (Psub) 70 constitutes the collector of the PNP transistor, and the N well (N-Well) 50 constitutes the base of the PNP transistor, and the high-concentration N-type doping ( N+) 26, high-concentration P-type doping (P+) 28 placed on the top of P well (P-Well) 60, N well (N-Well) 50, substrate (Psub) 70/P well (P-Well) 60 and High-concentration N-type doping (N+) 26 constitutes an equivalent NPN transistor structure, N well (N-Well) 50 constitutes the collector of the NPN transistor, and high-concentration N-type doping (N+) 26 constitutes an equivalent NPN transistor emitter Pole, substrate (Psub) 70/P well (P-Well) 60 constitutes the base of an equivalent NPN transistor, and high-concentration N-type doping (N+) 24 is placed in N well (N-Well) 50 and P well (P -Well) above the boundary of 60, high-concentration N-type doping (N+) 20, high-concentration P-type doping (P+) 22, high-concentration N-type doping (N+) 24, high-concentration N-type doping (N+) 26. Use shallow trench isolation (STI, Shallow Trench Isolation) 10 between high-concentration P-type doping (P+) 28 to isolate; use metal to connect high-concentration N-type doping (N+) 20, high-concentration P-type doping (P+ ) 22 constitute the anode A of the silicon controlled rectifier (SCR) type ESD protection structure, high concentration N-type doping (N+) 26, high concentration P type doping (P+) 28 are connected with metal and then connected to the silicon controlled rectifier (SCR ) type ESD protection structure cathode K.

The silicon controlled rectifier type ESD protection structure shown in Fig. 2 is based on the silicon controlled rectifier type ESD protection structure shown in Fig. Miscellaneous (P+) 28 moves to the right, and an N-type gate 30 is added above the newly vacated P-well (P-Well) 60, and is connected to the cathode K of the silicon-controlled rectifier (SCR), forming the P-well 60 N-type gate-controlled diodes, by introducing N-type gated diodes (gate-controlled diodes), thereby further reducing the reverse breakdown voltage of the N-well to the P-well, but even so, the trigger voltage of the silicon-controlled rectifier shown in Figure 2 is relatively low High, and the trigger voltage is also limited by the existing process parameters, and the degree of freedom of adjustment is not large.

In view of the relatively low maintenance voltage of silicon controlled rectifiers, the industry generally realizes this by increasing the distance (c+d) from the P junction (22) in the N well of the silicon controlled rectifier to the N junction (26) in the P well, As shown in Figure 1, or through an external diode to achieve. But these two methods, especially the method of connecting external diodes, will greatly increase the layout area (Layout Area) of the silicon controlled rectifier type ESD protection structure.

The semiconductor industry has further proposed the existing novel silicon-controlled rectifier-type ESD protection structure as shown in Figure 3. Compared with the traditional silicon-controlled rectifier-type ESD protection structure (as shown in Figure 2), the new silicon-controlled rectifier-type ESD protection structure The anode A is directly connected to the P-type doping (P+) 22 in the N well (N-Well) 60 and the N-type doping between the N well (N-Well) 50 on the right side and the P well (P-Well) 60 interface. The impurity (N+) 24 is connected, and the N-type doping (N+) 20 on the left side of the P-type doping (P+) 22 in the N well (N-Well) 50 in FIG. 2 is removed. Because the N-type doping (N+) 24 between the N well (N-Well) 50 and the P well (P-Well) 60 interface in the novel silicon controlled rectifier is directly connected with the anode A, so the hysteresis of the novel silicon controlled rectifier The trigger voltage of the effect is directly determined by the breakdown voltage of the N-type doping (N+) 24/P well (P-Well) 60 and is greatly reduced. In addition, the N-type doping (N+) 24 is applied because it is directly connected to the anode A The positive pressure will reduce the probability of holes from P-type doping (P+) 22 incident to N well (N-Well) 50/P well (P-Well) 60 interface, so the silicon controlled rectifier type ESD protection structure The current gain of the parasitic triode P-type doped (P+) 22/N-well (N-Well) 50/P-well (P-Well) 60 will be reduced, so the holding voltage of the hysteresis effect of the novel silicon controlled rectifier will also be increased.

Verify and compare the actual hysteresis effect curve comparison results of the two silicon-controlled rectifier-type ESD protection structures shown in Figure 2 and Figure 3 in a low-voltage process platform, as shown in Figure 4, and the small square connection (NovelLVTSCR) is shown in Figure 4. 3 shows the hysteresis effect curve of the silicon controlled rectifier type ESD protection structure, and the small rhombus connection (STDLVTSCR) is the hysteresis effect curve of the silicon controlled rectifier type ESD protection structure shown in FIG. 2 . The hysteresis effect curve comparison chart shows that the trigger voltage of the hysteresis effect of the new silicon-controlled rectifier type ESD protection structure shown in Figure 3 is reduced from 11.2V to 8.4V, which is much smaller than the gate voltage of the peripheral interface circuit device of the low-voltage process platform. The transient breakdown voltage of the extreme oxide layer (about 11.6V); but the maintenance voltage of its hysteresis effect is only raised from 2.7V to 3.2V, which is already greater than the maximum operating voltage of the low-voltage process platform 2.5V peripheral interface circuit (Vddmax=2.75 V), but still less than the maximum operating voltage (Vddmax=3.65V) of the 3.3V IO peripheral interface circuit of the low-voltage process platform.

This shows that the new silicon-controlled rectifier type shown in Figure 3 is fully suitable for the ESD protection circuit design of the 2.5V peripheral interface circuit of this low-voltage process platform, but for the ESD protection circuit design of the peripheral interface circuit, it is necessary to further increase its maintenance voltage to above 4V.

Contents of the invention

In order to overcome the disadvantages of the prior art, the object of the present invention is to provide a novel silicon controlled rectifier type ESD protection structure and its implementation method, which can increase the sustaining voltage of the hysteresis effect of the ESD protection structure.

For reaching above-mentioned and other purpose, the present invention proposes a kind of novel silicon controlled rectifier type ESD protection structure, it is characterized in that, this ESD protection structure comprises:

a semiconductor substrate (80);

N well (60) and P well (70) formed in the semiconductor substrate;

The first high-concentration P-type doping (20), the first high-concentration N-type doping (28) are placed on the upper part of the N well (60), the first high-concentration P-type doping (20), the N well (60) and The P well (70) constitutes an equivalent PNP triode structure, the third high-concentration N-type doping (24), the second high-concentration P-type doping (26) are placed on the top of the P well (70), and the N well (60), The semiconductor substrate (80) and the third high-concentration N-type doping (24) form an equivalent NPN transistor structure, and the second high-concentration N-type doping (22) is placed at the boundary between the N well (60) and the P well (70) Above, an N-type gate (50) is placed between the second high-concentration N-type doping (22) and the third high-concentration N-type doping (24).

Further, connecting the first high-concentration P-type doping (20), the first high-concentration N-type doping (28), and the second high-concentration N-type doping (22) to form the anode of the ESD protection structure by using metal A, using metal to connect the N-type gate (50), the third high-concentration N-type doping (24), and the second high-concentration P-type doping (26) to form the cathode K of the ESD protection structure.

Further, the shallow trench isolation layer STI (10 ) isolation, the third high-concentration N-type doping (24) and the second high-concentration P-type doping (26) are isolated by a shallow trench isolation layer STI (10).

Further, a shallow trench isolation layer STI (10) is provided on the left side of the first high-concentration P-type doping (20).

Further, a shallow trench isolation layer STI (10) is placed on the right side of the second high-concentration P-type doping (26).

Further, by adjusting the size and depth of the first high-concentration N-type doping (28) and the distance between the first high-concentration N-type doping (28) and the first high-concentration P-type doping (20) To adjust the sustain voltage of the hysteresis effect, the distance between the first high-concentration N-type doping (28) and the first high-concentration P-type doping (20) ranges from 0.5 to 20um.

Further, the N-type gate (50) is placed above the second high-concentration N-type doping (22) and the third high-concentration N-type doping (24).

In order to achieve the above object, the present invention also provides a kind of realization method of novel ESD protection structure, comprises the steps:

Step 1, providing a semiconductor substrate (80);

Step 2, forming an N well (60) and a P well (70) in the semiconductor substrate (80);

Step 3, placing the first high-concentration P-type doping (20), the first high-concentration N-type doping (28) on the upper part of the N well (60), the first high-concentration P-type doping (20), the N well (60) and the P well (70) form an equivalent PNP transistor structure, the third high-concentration N-type doping (24), the second high-concentration P-type doping (26) are placed on the top of the P well (70), and the N well (60), the semiconductor substrate (80) and the third high-concentration N-type doping (24) form an equivalent NPN transistor structure, and the second high-concentration N-type doping (22) is placed in the N well (60) and the P well (70) An N-type gate (50) is placed above the boundary and between the second high-concentration N-type doping (22) and the third high-concentration N-type doping (24).

Further, after step three, it also includes: using metal to connect the first high-concentration P-type doping (20), the first high-concentration N-type doping (28), the second high-concentration N-type doping (22 ) forming the anode A of the ESD protection structure; using metal to connect the N-type gate (50), the third high-concentration N-type doping (24), and the second high-concentration P-type doping (26) to form the ESD protection structure of the cathode K.

Further, the shallow trench isolation layer STI (10 ) isolation, the third high-concentration N-type doping (24) and the second high-concentration P-type doping (26) are isolated by a shallow trench isolation layer STI (10).

Compared with the prior art, a novel silicon-controlled rectifier type ESD protection structure and its implementation method of the present invention, it is based on the existing silicon-controlled rectifier type ESD protection structure as shown in Figure 3, in the existing ESD protection A first high-concentration N-type doping (N+) 28 is inserted between the first high-concentration P-type doping (P+) 20 and the second high-concentration N-type doping (N+) 22 of the structure anode A, and the newly added The first high-concentration N-type doping (N+) 28 of the first high-concentration N-type doping (N+) 28 is also connected to the anode A, because the first high-concentration N-type doping (N+) 28 newly added has a very high positive voltage due to being connected to the anode during work, it can Greatly reduce the holes from the parasitic PNP transistor (high concentration P-type doping (P+) 20/N well (N-Well) 60/P well (P-Well) 70) in the novel silicon controlled rectifier type ESD protection structure The first high-concentration P-type doping (P+) 20 is implanted into the N well (N-Well) 60 and reaches the probability of the N well (N-Well) 60 and the P well (P-Well) 70 interface, thereby reducing the probability of the N well (N-Well) 60 and the P well (P-Well) 70 interface The current gain of the parasitic triode, so as to achieve the purpose of further increasing the holding voltage, here the newly added first high-concentration N-type doping (N+) 28 actually acts as a guard ring (GuardRing).

Description of drawings

1 is a schematic diagram of a prior art ESD protection structure;

2 is a schematic diagram of another existing silicon controlled rectifier type ESD protection structure;

FIG. 3 is a schematic diagram of another existing novel silicon-controlled rectifier-type ESD protection structure;

Fig. 4 is a schematic diagram comparing the hysteresis effect curves of the two silicon controlled rectifier ESD protection structures in Fig. 3 and Fig. 2;

Fig. 5 is the circuit structure figure of the preferred embodiment of a kind of novel silicon controlled rectifier type ESD protection structure of the present invention;

Fig. 6 is the step flowchart of the realization method of a kind of novel silicon controlled rectifier type ESD protection structure of the present invention;

FIG. 7 is a schematic diagram of an application scenario of the present invention.

Detailed ways

The implementation of the present invention will be described below through specific examples and in conjunction with the accompanying drawings, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

FIG. 5 is a circuit structure diagram of a preferred embodiment of a novel silicon controlled rectifier type ESD protection structure of the present invention. As shown in Figure 5, a novel silicon-controlled rectifier type ESD protection structure of the present invention comprises a plurality of shallow trench isolation layers (STI, Shallow Trench Isolation) 10, the first high-concentration P-type doping (P+) 20, the first Second high-concentration N-type doping (N+) 22, third high-concentration N-type doping (N+) 24, second high-concentration P-type doping (P+) 26, first high-concentration N-type doping (N+) 28 , N well (N-Well) 60 , P well (P-Well) 70 , substrate (Psub) 80 and N-type gate 50 .

The entire ESD protection structure is placed on the substrate (Psub) 80, an N well (N-Well) 60 is formed on the left side of the substrate (Psub) 80, and a P well (P-Well) 70 is formed on the right side of the substrate (Psub) 80. A high-concentration P-type doping (P+) 20, a first high-concentration N-type doping (N+) 28 are placed on the top of the N well (N-Well) 60, the first high-concentration P-type doping (P+) 20, N The well (N-Well) 60 and the P-well (P-Well) 70 constitute an equivalent PNP transistor structure, and the third high-concentration N-type doping (N+) 24 and the second high-concentration P-type doping (P+) 26 are placed The upper part of the P well (P-Well) 70, the N well (N-Well) 60, the substrate (Psub) 80/P well (P-Well) 70 and the third high-concentration N-type doping (N+) 24 constitute an equivalent NPN Triode structure, the second high-concentration N-type doping (N+) 22 is placed above the boundary between the N well (N-Well) 60 and the P well (P-Well) 70, and the first high-concentration P-type doping (P+) 20 , the first high-concentration N-type doping (N+) 28, and the second high-concentration N-type doping (N+) 22 are separated by a shallow trench isolation layer (STI, Shallow Trench Isolation) 10, and the first high-concentration P-type doping A shallow trench isolation layer (STI, Shallow Trench Isolation) 10 is placed on the left side of the impurity (P+) 20, and a shallow trench is used between the third high-concentration N-type doping (N+) 24 and the second high-concentration P-type doping (P+) 26 The channel isolation layer (STI, Shallow Trench Isolation) 10 is isolated, and the second high concentration P-type doping (P+) 26 is placed on the right side of the shallow trench isolation layer (STI, Shallow Trench Isolation) 10, and the second high concentration N-type doping Between the (N+) 22 and the third high-concentration N-type doping (N+) 24 is a part of the P well (P-Well) 70, and the N-type gate 50 is placed above the part of the P-well, and the N-type gate 50 is placed Above the second high-concentration N-type doping (N+) 22 and the third high-concentration N-type doping (N+) 24; use metal to connect the first high-concentration P-type doping (P+) 20, the first high-concentration N-type doping Miscellaneous (N+) 28 and second high-concentration N-type doping (N+) 22 constitute the anode A of the novel low-triggering voltage and high-sustaining voltage silicon-controlled rectifier type ESD protection structure, and connect the N-type gate 50 and the third high Concentration N-type doping (N+) 24 and second high-concentration P-type doping (P+) 26 constitute the cathode K of the novel low trigger voltage and high sustain voltage silicon-controlled rectifier ESD device.

It can be seen that the ESD protection structure of the present invention is realized on the basis of the existing silicon-controlled rectifier type ESD as shown in Figure 3, and the ESD protection structure of the present invention is actually in the high concentration P-type of the original silicon-controlled rectifier anode A A first high-concentration N-type doping (N+) 28 is inserted between the doping (P+) 20 and the high-concentration N-type doping (N+) 22, and the newly added first high-concentration N-type doping (N+) 28 is also connected to anode A, because the newly added first high-concentration N-type doping (N+) 28 has a very high positive voltage during work, which can reduce the parasitic PNP triode (P-type transistor) in this novel silicon controlled rectifier type ESD Doped (P+) 20/N well (N-Well) 60/P well (P-Well) 70) holes are injected into the N well (N-Well) from the first high-concentration P-type doped (P+) 20 60 and reach the probability of N well (N-Well) 60 and P well (P-Well) 70 interface, thereby reducing the current gain of the parasitic triode, so as to achieve the purpose of further increasing the maintenance voltage, here is a new addition The first high-concentration N-type doping (N+) 28 actually functions as a guard ring.

Simultaneously, the present invention can adjust the size and depth of the first high-concentration N-type doping (N+) 28 of the novel silicon controlled rectifier type ESD structure and the relationship between the first high-concentration N-type doping (N+) 28 and the first high-concentration The distance a between the P-type doping (P+) 20 is used to adjust the sustain voltage of the hysteresis effect, the distance between the first high-concentration N-type doping (28) and the first high-concentration P-type doping 20 a typical range is 0.5 ~ 20um.

FIG. 6 is a flow chart of the implementation method of a novel silicon controlled rectifier type ESD protection structure of the present invention. As shown in Figure 6, the realization method of a kind of novel silicon-controlled rectifier type ESD protection structure of the present invention comprises the following steps:

Step 601, providing a semiconductor substrate, in a specific embodiment of the present invention, providing a P-type substrate (P-Sub) 80 .

In step 602, an N well and a P well are formed in the semiconductor substrate, that is, an N well (N-Well) 60 and a P well (P-Well) 70. An N well (N-Well) 60 is formed on the left of Sub) 80, and a P well (P-Well) 70 is formed on the right of substrate (Psub) 80.

Step 603, placing the first high-concentration P-type doping (P+) 20 and the first high-concentration N-type doping (N+) 28 on the upper part of the N well (N-Well) 60, and the first high-concentration P-type doping ( P+) 20, N well (N-Well) 60 and P well (P-Well) 70 constitute an equivalent PNP transistor structure, the third high-concentration N-type doping (N+) 24, the second high-concentration P-type doping ( P+) 26 is placed on the top of P well (P-Well) 70, N well (N-Well) 60, substrate (Psub) 80 and third high-concentration N-type doping (N+) 24 form an equivalent NPN triode structure, the first The second high-concentration N-type doping (N+) 22 is placed above the boundary between the N-well (N-Well) 60 and the P-well (P-Well) 70, the first high-concentration P-type doping (P+) 20, the first high-concentration Concentration N-type doping (N+) 28, second high-concentration N-type doping (N+) 22 are isolated by shallow trench isolation layer (STI, Shallow Trench Isolation) 10, first high-concentration P-type doping (P+) Shallow trench isolation layer (STI, Shallow Trench Isolation) 10 is placed on the left side of 20, shallow trench isolation layer is used between the third high-concentration N-type doping (N+) 24 and the second high-concentration P-type doping (P+) 26 (STI, Shallow Trench Isolation) 10 isolation, the second high concentration P-type doping (P+) 26 is placed on the right side shallow trench isolation layer (STI, Shallow Trench Isolation) 10, the second high concentration N-type doping (N+) 22 and the third high-concentration N-type doping (N+) 24 is a part of the P well (P-Wel) 70, and the N-type gate 50 is placed above the part of the P well, and the N-type gate 50 is placed on the second highest Concentration N-type doping (N+) 22 and a third high concentration N-type doping (N+) 24 are above.

Step 604, use metal to connect the first high-concentration P-type doping (P+) 20, the first high-concentration N-type doping (N+) 28, and the second high-concentration N-type doping (N+) 22 to form the silicon controlled rectifier type The anode A of the ESD protection structure uses metal to connect the N-type gate 50, the third high-concentration N-type doping (N+) 24, and the second high-concentration P-type doping (P+) 26 to form the silicon controlled rectifier type ESD protection structure. The cathode K.

The new ESD of the present invention can be applied to the protection circuit of the input and output terminals and the protection circuit of the power supply to the ground in the ESD protection circuit to improve the overall ESD protection capability of the chip, as shown in FIG. 7 .

In summary, a novel silicon-controlled rectifier type ESD protection structure and its implementation method of the present invention, it is by on the basis of existing silicon-controlled rectifier type ESD protection structure as shown in Figure 3, in existing ESD protection structure anode A first N-type heavy doping is inserted between the P-type doping (P+) 20 (Fig. 4, corresponding to Fig. 3 as 22) and the N-type doping (N+) 22 (Fig. 4, corresponding to Fig. 3 as 24) of A Miscellaneous (N+) 28 (Fig. 4), the newly added first N-type heavily doped (N+) 28 is also connected to the anode A, because the newly added first N-type heavily doped (N+) 28 has Very high positive voltage can reduce the empty space of the parasitic PNP triode (P-type doping (P+) 20/N well (N-Well) 60/P well (P-Well) 70) in this novel silicon controlled rectifier type ESD. Holes are injected from high-concentration P-type doping (P+) 20 into N well (N-Well) 60 and reach the probability of N well (N-Well) 60 and P well (P-Well) 70 interfaces, thereby reducing this The current gain of the parasitic triode, so as to achieve the purpose of further increasing the holding voltage, the newly added N-type doping (N+) 28 here actually plays the role of a guard ring (Guard Ring).

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Any person skilled in the art can modify and change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be listed in the claims.

Claims (7)

1. A novel silicon controlled rectifier type ESD protection structure, is characterized in that, this ESD protection structure comprises: a semiconductor substrate (80); The N well (60) and the P well (70) formed in the semiconductor substrate; the first high-concentration P-type doping (20), the first high-concentration N-type doping (28) placed in the N well (60) ), the first high-concentration P-type doping (20), N well (60) and P well (70) constitute an equivalent PNP transistor structure, the third high-concentration N-type doping (24), the second high-concentration P Type doping (26) is placed on the upper part of P well (70), N well (60), semiconductor substrate (80) and the third high concentration N type doping (24) form an equivalent NPN triode structure, the second highest concentration The N-type doping (22) is placed above the boundary between the N-well (60) and the P-well (70), between the second high-concentration N-type doping (22) and the third high-concentration N-type doping (24) An N-type gate (50) is placed above; the first high-concentration N-type doping (28) is located between the first high-concentration P-type doping (20) and the second high-concentration N-type doping (22) Between; utilize metal to connect described first high-concentration P-type doping (20), first high-concentration N-type doping (28), second high-concentration N-type doping (22) constitute the anode A of this ESD protection structure , using metal to connect the N-type gate (50), the third high-concentration N-type doping (24), and the second high-concentration P-type doping (26) to form the cathode K of the ESD protection structure; Adjust the size and depth of the first high-concentration N-type doping (28) and the distance between the first high-concentration N-type doping (28) and the first high-concentration P-type doping (20). The maintaining voltage of the hysteresis effect, the distance between the first high-concentration N-type doping (28) and the first high-concentration P-type doping (20) ranges from 0.5 to 20um. 2. a kind of novel silicon-controlled rectifier type ESD protection structure as claimed in claim 1 is characterized in that: described first high-concentration P-type doping (20), the first high-concentration N-type doping (28), The second high-concentration N-type doping (22) is isolated by a shallow trench isolation layer STI (10), the third high-concentration N-type doping (24), the second high-concentration P-type doping (26) Isolate with shallow trench isolation layer STI (10). 3. A novel silicon controlled rectifier type ESD protection structure according to claim 2, characterized in that: a shallow trench isolation layer STI (10) is arranged on the left side of the first high-concentration P-type doping (20). 4. A novel silicon controlled rectifier type ESD protection structure according to claim 3, characterized in that: a shallow trench isolation layer STI (10) is placed on the right side of the second high-concentration P-type doping (26). 5. A novel silicon-controlled rectifier type ESD protection structure as claimed in claim 1, characterized in that: said N-type gate (50) is placed between said second high-concentration N-type doping (22) and the first Three high-concentration N-type doping (24) above. 6. A method for realizing a novel silicon controlled rectifier type ESD protection structure, comprising the steps of: Step 1, providing a semiconductor substrate (80); Step 2, forming an N well (60) and a P well (70) in the semiconductor substrate; Step 3, placing the first high-concentration P-type doping (20), the first high-concentration N-type doping (28) on the upper part of the N well (60), the first high-concentration P-type doping (20), the N well (60) and the P well (70) form an equivalent PNP transistor structure, the third high-concentration N-type doping (24), the second high-concentration P-type doping (26) are placed on the top of the P well (70), and the N well (60), the semiconductor substrate (80) and the third high-concentration N-type doping (24) form an equivalent NPN transistor structure, and the second high-concentration N-type doping (22) is placed in the N well (60) and the P well (70) Above the boundary, an N-type gate (50) is placed above the second high-concentration N-type doping (22) and the third high-concentration N-type doping (24); the first high-concentration N Type doping (28) is located between the first high-concentration P-type doping (20) and the second high-concentration N-type doping (22); after step 3, it also includes: using metal to connect the first High-concentration P-type doping (20), first high-concentration N-type doping (28), and second high-concentration N-type doping (22) constitute the anode A of the ESD protection structure; use metal to connect the N-type gate The pole (50), the third high-concentration N-type doping (24), and the second high-concentration P-type doping (26) constitute the cathode K of the ESD protection structure; Adjusting the size and depth of the first high-concentration N-type doping (28), and the distance between the first high-concentration N-type doping (28) and the first high-concentration P-type doping (20) To adjust the sustain voltage, the distance between the first high-concentration N-type doping (28) and the first high-concentration P-type doping (20) typically ranges from 0.5 to 20um. 7. the realization method of a kind of novel silicon-controlled rectifier type ESD protection structure as claimed in claim 6, is characterized in that: described first high-concentration P-type doping (20), first high-concentration N-type doping ( 28), the second high-concentration N-type doping (22) is isolated by a shallow trench isolation layer STI (10), the third high-concentration N-type doping (24), the second high-concentration P-type doping ( 26) are isolated by a shallow trench isolation layer STI (10).