CN106411319A - Clock generation circuit for analog-to-digital converter - Google Patents

Abstract

The invention discloses a clock generating circuit for an analog-to-digital converter, which includes a clock stabilization circuit and a two-phase non-overlapping clock generating circuit. The clock stabilization circuit includes a clock stabilization loop and a feedback signal generation circuit. In the feedback signal generation circuit, an active low-pass filter is used to generate a control signal to control the N-tube current modulation inverter, a clock stabilization loop is used to generate a stable clock signal, and the feedback signal is precisely modulated by filtering technology and current modulation technology. In the clock stabilization loop, the duty cycle of the output clock can be reduced through the loop structure. Under the adjustment of the feedback signal, the duty cycle of the output clock is increased by pulling up the PMOS transistor MP1, and finally achieves a 50% duty cycle of the output clock and stabilizes the clock. Reduce jitter. The clock stabilization circuit proposed by the present invention can be integrated in the ADC circuit. By adopting the structure proposed by the present invention, the quality of the clock signal can be significantly improved, the strict requirement of the ADC on the clock quality can be reduced, and the signal-to-noise ratio of the ADC can be improved.

Description

A Clock Generating Circuit for Analog-to-Digital Converter

technical field

The invention relates to the field of analog integrated circuits, in particular to a clock generating circuit structure that can be used in digital and analog mixed signal circuits.

Background technique

In the process of human beings using technology and wisdom to explore nature, the first signals obtained are analog signals, while computers can only process digital signals. It is necessary to use an analog-to-digital converter to quantize the analog signals that exist widely in nature into digital signals for people to use computers for processing and transmission. Therefore, the analog-to-digital converter is a bridge between the analog world and the digital world, and has important use value and broad application prospects.

With the continuous development of ADC (Analog-to-Digital Converter) toward high speed and high precision, the error caused by the phase noise caused by the sampling clock jitter to the sample-and-hold circuit has gradually become a major factor restricting the improvement of ADC performance. The principle of ADC performance degradation caused by sampling clock jitter is as follows. The jitter of the sampling clock is a short-term, non-accumulative variable that represents the time deviation between the actual timing position of the digital signal and its ideal position. The jitter generated by the clock signal will cause the internal circuit of the ADC to wrongly trigger the sampling time, resulting in missampling of the analog input signal in amplitude, thereby deteriorating the signal-to-noise ratio of the ADC. Therefore, in high-speed and high-precision ADC applications, a stable clock signal is required to reduce the impact of clock phase noise on ADC performance.

Contents of the invention

The invention provides a clock stabilizing technology, which feedbacks and adjusts the clock stabilizing loop through a feedback signal generating circuit to obtain a clock signal output with a stable duty ratio. The reduction of clock jitter is achieved through a low-pass filter and an N-tube current modulation inverter. The obtained stable clock signal passes through the two-phase non-overlapping circuit to obtain a two-phase non-overlapping clock signal.

In order to solve the above technical problems, the present invention proposes a clock generation circuit for analog-to-digital converters, including a clock stabilization circuit and a two-phase non-overlapping clock generation circuit, and the clock stabilization circuit includes a clock stabilization loop and a feedback signal Generate the circuit. A clock stabilization loop is used to generate a stable clock signal, and a feedback signal is generated by a feedback signal generation circuit to adjust the clock stabilization loop. The feedback signal generation circuit includes an active low-pass filter and an N-tube current modulation inverter.

The clock stabilization loop includes a pull-up PMOS transistor MP1, a two-input NAND gate NAND1 and 4 inverters, and the 4 inverters are respectively marked as inverter INV1, inverter INV2, and inverter INV3 And inverter INV4, wherein, the input end of the inverter INV1 is connected to the input clock signal, the output end of the inverter INV1 is connected to an input end of the two-input NAND gate NAND1; the output end of the two-input NAND gate NAND1 is connected to the inverter The input terminal of INV2, the output terminal of the inverter INV2 is connected to the drain of the pull-up PMOS transistor MP1 and the input terminal of the inverter INV3, the source of the pull-up PMOS transistor MP1 is connected to the power supply VDD, and the gate voltage of the pull-up PMOS transistor MP1 is connected From the feedback signal generating circuit; the output terminal of the inverter INV3 is connected to the input terminal of the inverter INV4, and the output terminal of the inverter INV4 is connected to the other input terminal of the two-input NAND gate NAND1.

The feedback signal generating circuit includes an active low-pass filter, an N-tube current modulation inverter, 3 two-input NAND gates, 3 inverters and 1 D flip-flop DFF; the 3 NAND gates are respectively Denoted as two-input NAND gate NAND2, two-input NAND gate NAND3 and two-input NAND gate NAND4, the three inverters are respectively denoted as inverter INV5, inverter INV6 and inverter INV7.

The active low-pass filter includes an operational amplifier AMP1, a resistor R1 and a capacitor C1; one end of the resistor R1 is connected to the output terminal of the inverter INV5, and the other end of the resistor R1 is connected to the negative phase input terminal of the operational amplifier AMP1 and One end of the capacitor C1; the other end of the capacitor C1 is connected to the output terminal of the operational amplifier AMP1 and the gate of the NMOS tube MN1; the positive phase input terminal of the operational amplifier is connected to the reference voltage VREF, and the negative phase input terminal of the operational amplifier AMP1 is connected to the resistor R1 and one terminal of the capacitor C1. The output terminal of the amplifier AMP1 is connected to the other terminal of the capacitor C1.

The N-tube current modulation inverter includes an NMOS transistor MN1, an NMOS transistor MN2 and a PMOS transistor MP2, wherein the NMOS transistor MN2 and the PMOS transistor MP2 form an inverter, and the NMOS transistor MN1 controls the current flowing through the inverter under the control of the gate voltage. The current of the N tube is adjusted; the source of the PMOS tube MP2 is connected to the power supply VDD, the gate of the PMOS tube MP2 is connected to the output terminal of the two-input NAND gate NAND4, and the drain of the PMOS tube MP2 is simultaneously connected to the drain of the NMOS tube MN2 and the inverter INV6 The drain of the NMOS transistor MN2 is connected to the drain of the PMOS transistor MP2, the gate of the NMOS transistor MN2 is connected to the output end of the two-input NAND gate NAND4, the source of the NMOS transistor MN2 is connected to the drain of the NMOS transistor MN1; the drain of the NMOS transistor MN1 The drain is connected to the source of the NMOS transistor MN2, the gate of the NMOS transistor MN1 is connected to the output terminal of the operational amplifier AMP1, and the source of the NMOS transistor MN1 is connected to the ground.

In the present invention, one input terminal of the two-input NAND gate NAND2 is connected to the output terminal of the inverter INV4, and the output terminal of the two-input NAND gate NAND2 is connected to the data input terminal D of the D flip-flop DFF; the clock input of the D flip-flop DFF The terminal CLK is connected to the output terminal of the inverter INV1, the output terminal of the D flip-flop DFF is connected to one input terminal of the two-input NAND gate NAND3, and the other input terminal of the two-input NAND gate NAND3 is connected to the output terminal of the inverter INV1, The output end of the two-input NAND gate NAND3 is connected to the input end of the inverter INV5; the two input ends of the two-input NAND gate NAND4 are respectively connected to the output ends of the inverter INV1 and the inverter INV2; the output of the inverter INV6 terminal is connected to the input terminal of the inverter INV7, and the output terminal of the inverter INV7 is connected to the other input terminal of the two-input NAND gate NAND2.

The two-phase non-overlapping clock generating circuit includes two two-input NAND gates and five inverters, wherein the two two-input NAND gates are respectively denoted as two-input NAND gate NAND5 and two-input NAND gate NAND6 , the five inverters are respectively recorded as inverter INV8, inverter INV9, inverter INV10, inverter INV11 and inverter INV12, the input end of inverter INV8 is connected to the output end of inverter INV2, The output terminal of the inverter INV8 is connected to one input terminal of the two-input NAND gate NAND5, the other input terminal of the two-input NAND gate NAND5 is connected to the output terminal of the inverter INV12, and the output terminal of the two-input NAND gate NAND5 is connected to the inverter. The input end of the inverter INV9; the output end of the inverter INV9 is connected to the input end of the inverter INV10, and the output end of the inverter INV10 is connected to one input end of the two-input NAND gate NAND6, and the other of the two-input NAND gate NAND6 One input terminal is connected to the output terminal of the inverter INV2, the output terminal of the two-input NAND gate NAND6 is connected to the input terminal of the inverter INV11; the output terminal of the inverter INV11 is connected to the input terminal of the inverter INV12.

Compared with the prior art, the clock generating circuit for the analog-to-digital converter of the present invention includes three parts: a clock stabilization loop, a feedback signal generating circuit, and a two-phase non-overlapping clock generating circuit. Among them, the clock stabilization loop converts the input clock signal into a clock signal with stable duty ratio and low jitter; the two-phase non-overlapping clock generation circuit converts the stable clock signal into a stable two-phase non-overlapping clock; the feedback signal generation The circuit provides a feedback adjustment signal for the circuit by collecting the input and output clock signals, so as to realize clock duty cycle adjustment and low jitter.

The clock stabilization circuit proposed by the present invention can be integrated in an ADC circuit. Compared with the method of using a low phase noise oscillator, the structure proposed by the present invention can adjust an input clock signal of any frequency. A stable and low-jitter clock signal can be obtained by passing an ordinary clock signal through the circuit structure of the present invention. By adopting the structure proposed by the invention, the quality of the clock signal can be significantly improved, the strict requirement of the ADC on the clock quality can be reduced, and the signal-to-noise ratio of the ADC can be improved.

Description of drawings

Fig. 1 is a schematic diagram of the working principle of the clock stabilization circuit in the present invention;

Fig. 2 is the schematic diagram of clock stabilization loop circuit in the present invention;

Fig. 3 is a schematic diagram of a feedback signal generation circuit in the present invention;

Fig. 4 is a schematic diagram of the overall clock stabilization circuit in the present invention;

Fig. 5 is a two-phase non-overlapping clock generation circuit in the present invention.

detailed description

The present invention will be further described in detail below in combination with specific embodiments.

As shown in Figure 1, the design idea of the present invention is to generate a stable clock signal through the clock stabilization loop, and the used clock stabilization loop itself realizes reducing the duty cycle of the output clock signal CLK_OUT through the NAND gate NAND1, and pulls up the PMOS transistor MP1 realizes increasing the duty cycle of the output clock signal CLK_OUT. Through the feedback signal generation circuit part, the feedback signal A is generated according to the input clock CLK and the output clock CLK_OUT, so as to realize the adjustment of the duty ratio of the output clock and the elimination of clock jitter.

As shown in Fig. 1, a kind of clock generation circuit for analog-to-digital converter proposed by the present invention includes a clock stabilization circuit and a two-phase non-overlapping clock generation circuit, and the clock stabilization circuit includes a clock stabilization loop and a feedback signal Generate the circuit. A clock stabilization loop is used to generate a stable clock signal, and a feedback signal is generated by a feedback signal generation circuit to adjust the clock stabilization loop. The feedback signal generation circuit includes an active low-pass filter and an N-tube current modulation inverter.

As shown in Figure 2, in the present invention, the clock stabilization loop includes a pull-up PMOS transistor MP1, a two-input NAND gate NAND1 and 4 inverters, and the 4 inverters are respectively denoted as inverter INV1 , inverter INV2, inverter INV3 and inverter INV4, wherein, the input end of the inverter INV1 is connected to the input clock signal, and the output end of the inverter INV1 is connected to an input end of the two-input NAND gate NAND1; the two-input NAND The output of the non-gate NAND1 is connected to the input of the inverter INV2, the output of the inverter INV2 is connected to the drain of the pull-up PMOS transistor MP1 and the input of the inverter INV3, and the source of the pull-up PMOS transistor MP1 is connected to the power supply VDD, the pull-up PMOS transistor MP1 gate voltage comes from the feedback signal generation circuit; the output terminal of the inverter INV3 is connected to the input terminal of the inverter INV4, and the output terminal of the inverter INV4 is connected to the other input of the two-input NAND gate NAND1 end.

As shown in Figure 3, in the present invention, the feedback signal generating circuit includes an active low-pass filter, an N-tube current modulation inverter, 3 two-input NAND gates, 3 inverters and 1 D trigger device DFF; the three NAND gates are respectively marked as two-input NAND gate NAND2, two-input NAND gate NAND3 and two-input NAND gate NAND4, and the three inverters are respectively marked as inverter INV5, inverter INV6 and inverter INV7.

The active low-pass filter includes an operational amplifier AMP1, a resistor R1 and a capacitor C1; one end of the resistor R1 is connected to the output terminal of the inverter INV5, and the other end of the resistor R1 is connected to the negative phase input terminal of the operational amplifier AMP1 and One end of the capacitor C1; the other end of the capacitor C1 is connected to the output terminal of the operational amplifier AMP1 and the gate of the NMOS tube MN1; the positive phase input terminal of the operational amplifier is connected to the reference voltage VREF, and the negative phase input terminal of the operational amplifier AMP1 is connected to the resistor R1 and one terminal of the capacitor C1. The output terminal of the amplifier AMP1 is connected to the other terminal of the capacitor C1.

The N-tube current modulation inverter includes an NMOS transistor MN1, an NMOS transistor MN2 and a PMOS transistor MP2, wherein the NMOS transistor MN2 and the PMOS transistor MP2 form an inverter, and the NMOS transistor MN1 controls the current flowing through the inverter under the control of the gate voltage. The current of the N tube is adjusted; the source of the PMOS tube MP2 is connected to the power supply VDD, the gate of the PMOS tube MP2 is connected to the output terminal of the two-input NAND gate NAND4, and the drain of the PMOS tube MP2 is simultaneously connected to the drain of the NMOS tube MN2 and the inverter INV6 The drain of the NMOS transistor MN2 is connected to the drain of the PMOS transistor MP2, the gate of the NMOS transistor MN2 is connected to the output end of the two-input NAND gate NAND4, the source of the NMOS transistor MN2 is connected to the drain of the NMOS transistor MN1; the drain of the NMOS transistor MN1 The drain is connected to the source of the NMOS transistor MN2, the gate of the NMOS transistor MN1 is connected to the output terminal of the operational amplifier AMP1, and the source of the NMOS transistor MN1 is connected to the ground.

As shown in Figure 4, in the feedback signal generation circuit and the clock stabilization loop, one input end of the two-input NAND gate NAND2 in the feedback signal generation circuit is connected to the output end of the inverter INV4 in the clock stabilization loop, The other input end of the two-input NAND gate NAND2 is connected to the output end of the inverter INV7, and the output end of the two-input NAND gate NAND2 is connected to the data input end D of the D flip-flop DFF.

The clock input end CLK of the D flip-flop DFF is connected to the output end of the inverter INV1 in the clock stabilization loop, the output end of the D flip-flop DFF is connected to one input end of the two-input NAND gate NAND3, and the other end of the two-input NAND gate NAND3 One input terminal is connected to the output terminal of the inverter INV1, the output terminal of the two-input NAND gate NAND3 is connected to the input terminal of the inverter INV5, and the output terminal of the inverter INV5 is connected to the resistor R1.

The two input ends of the two-input NAND gate NAND4 are respectively connected to the output ends of the inverter INV1 and the inverter INV2; the output end of the inverter INV6 is connected to the input end of the inverter INV7, and the output of the two-input NAND gate NAND4 The terminal is connected to the gates of the PMOS transistor MP2 and the NMOS transistor MN2. The output terminal of the inverter INV7 is connected to the other input terminal of the two-input NAND gate NAND2.

As shown in Figure 5, the two-phase non-overlapping clock generation circuit includes 2 two-input NAND gates and 5 inverters, wherein the two two-input NAND gates are respectively denoted as two-input NAND gates NAND5 and Two-input NAND gate NAND6, 5 inverters are recorded as inverter INV8, inverter INV9, inverter INV10, inverter INV11 and inverter INV12, and the input terminal of inverter INV8 is connected to the inverter The output end of the inverter INV2, the output end of the inverter INV8 is connected to one input end of the two-input NAND gate NAND5, the other input end of the two-input NAND gate NAND5 is connected to the output end of the inverter INV12, the two-input NAND gate The output end of NAND5 connects the input end of inverter INV9; The other input terminal of the NAND gate NAND6 is connected to the output terminal of the inverter INV2, and the output terminal of the two-input NAND gate NAND6 is connected to the input terminal of the inverter INV11; the output terminal of the inverter INV11 is connected to the input of the inverter INV12 end.

In the clock stabilization loop of the present invention, as shown in FIG. 2, when the feedback signal A is 1 (high level), the pull-up PMOS transistor is cut off, and the output clock CLK_OUT enters the NAND after passing through two inverters INV3 and INV4. Gate NAND1 input terminal B. When both node B and CLKN are 1, CLK_OUT is 1; when one of node B and CLKN is 0, CLK_OUT becomes 0, and clamps NAND1 output to 1, and CLK_OUT self-locks to low level 0. When the feedback signal A is 0, the pull-up PMOS transistor MP1 is turned on, and CLK_OUT becomes high level 1.

The feedback signal generation circuit of the present invention is shown in Figure 3, and the overall circuit of the clock stabilization circuit is shown in Figure 4. When the duty cycle of the output clock CLK_OUT is greater than 50%, the duty cycle of the node B signal is also greater than 50%, causing the node C signal to occupy The duty ratio of the node D is greater than 50%, so the duty ratio of the node D signal is greater than 50%. The node D is the negative phase input terminal of the operational amplifier AMP1, so the voltage of the node E at the output terminal of the operational amplifier AMP1 tends to decrease. Node E controls the NMOS tube modulation inverter, and the voltage decrease at point E causes the current of NMOS tube MN1 to decrease, and then the N tube current in the inverter composed of NMOS tube MN2 and PMOS tube MP2 decreases, that is, the N tube modulation inverter It is difficult for the voltage of the output node F to become low, causing the duty cycle of point F to be greater than 50%. The duty cycle of the feedback signal A is greater than 50%, so that the conduction time of the pull-up PMOS transistor is reduced, the high level time of the output clock CLK_OUT is reduced, and the duty cycle tends to 50%. Conversely, when the duty cycle of the output clock CLK_OUT is less than 50%, the duty cycle of the node B signal is less than 50%, causing the duty cycle of the node C signal to be less than 50%, so that the duty cycle of the node D signal is less than 50%, and the node D is The operational amplifier AMP1 has a negative input terminal, so the node E voltage at the output terminal of the operational amplifier AMP1 tends to increase. In turn, the current of the NMOS transistor MN1 increases, and the current of the N tube in the N-tube modulation inverter increases, that is, the voltage at the output node F of the N-tube modulation inverter tends to decrease, resulting in a decrease in the duty cycle of point F. The duty cycle of the feedback signal A is less than 50%, so the conduction time of the pull-up PMOS transistor increases, the high level time of the output clock CLK_OUT increases, and the duty cycle tends to 50%.

In the present invention, the two-phase non-overlapping clock generation circuit is shown in Figure 5, and the clock signal CLK_OUT with a duty ratio of 50% and low jitter output by the clock stabilization circuit is divided into two routes, and one route enters after being delayed by the inverter INV8 The NAND gate NAND5, the other way directly enters the inverter NAND6. The NAND gate only outputs a signal 0 when the input signals are all 1, and outputs a signal 1 when one of the input signals of the NAND gate is 0. Using this feature and the delay of the inverter, the output low level two-phase disjoint Stack clocks CLK_A and CLK_B.

Although the present invention has been described above in conjunction with the drawings, the present invention is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative, rather than restrictive. Under the inspiration, many modifications can be made without departing from the gist of the present invention, and these all belong to the protection of the present invention.

Claims (2)

1. a kind of clock generation circuit for analog-digital converter is not it is characterised in that inclusion Clock duty cycle stabilizer and two-phase are handed over Folded clock generation circuit, described Clock duty cycle stabilizer includes clock stable loop and feedback signal generating circuit；

Described clock stable loop includes pulling up PMOS MP1,1 two input nand gate NAND1 and 4 phase inverters, and 4 anti-phase Device is designated as phase inverter INV1, phase inverter INV2, phase inverter INV3 and phase inverter INV4 respectively, wherein, phase inverter INV1 input Connect input clock signal, phase inverter INV1 output end connects an input of two input nand gate NAND1；Two input with non- The output end of door NAND1 connects the input of phase inverter INV2, and the output end of phase inverter INV2 connects the leakage of pull-up PMOS MP1 Pole and the input of phase inverter INV3, the source electrode of pull-up PMOS MP1 connects power vd D, and pull-up PMOS MP1 grid voltage comes Self feed back signal generating circuit；The output end of phase inverter INV3 connects the input of phase inverter INV4, the output of phase inverter INV4 End connects another input of two input nand gate NAND1；

Described feedback signal generating circuit includes active low-pass filter, N tube current modulation inverter, 3 two input nand gates, 3 phase inverters and 1 d type flip flop DFF；This 3 NAND gates are designated as two input nand gate NAND2, two input nand gates respectively NAND3 and two input nand gate NAND4, this 3 phase inverters are designated as phase inverter INV5, phase inverter INV6 and phase inverter respectively INV7；

Described active low-pass filter includes 1 operational amplifier A MP1,1 resistance R1 and 1 electric capacity C1；Resistance R1 one end is even Connect the output end of phase inverter INV5, resistance R1 other end concatenation operation amplifier AMP1 negative-phase input and electric capacity C1 one end；Electricity Hold other end concatenation operation amplifier AMP1 output end and the NMOS tube MN1 grid of C1；Operational amplifier normal phase input end connects Reference voltage VREF, operational amplifier A MP1 negative-phase input connects one end of resistance R1 and electric capacity C1, operational amplifier A MP1 Output end connect to the other end of electric capacity C1；

Described N tube current modulation inverter includes NMOS tube MN1, NMOS tube MN2 and PMOS MP2, wherein NMOS tube MN2 and PMOS MP2 constitutes phase inverter, and NMOS tube MN1 is adjusted to the electric current of the N pipe flowing through phase inverter under grid voltage control； PMOS MP2 source electrode connects power vd D, and PMOS MP2 grid connects two input nand gate NAND4 output ends, and PMOS MP2 is leaked Pole is connected simultaneously to the drain electrode of NMOS tube MN2 and the input stage of phase inverter INV6；The drain electrode of NMOS tube MN2 connects PMOS MP2 Drain electrode, NMOS tube MN2 grid connects the output end of two input nand gate NAND4, and NMOS tube MN2 source electrode connects NMOS tube MN1 Drain electrode；The drain electrode of NMOS tube MN1 connects the source electrode of NMOS tube MN2, and the grid concatenation operation amplifier AMP1's of NMOS tube MN1 is defeated Go out end, the source electrode of NMOS tube MN1 connects ground；

One input of two input nand gate NAND2 connects the output end of phase inverter INV4, and two input nand gate NAND2's is defeated Go out the data input pin D that end connects d type flip flop DFF；The input end of clock CLK of d type flip flop DFF connects the output of phase inverter INV1 End, the output end of d type flip flop DFF connects an input of two input nand gate NAND3, and two input nand gate NAND3's is another One input connects the output end of phase inverter INV1, and the output end of two input nand gate NAND3 connects the defeated of phase inverter INV5 Enter end；Two inputs of two input nand gate NAND4 connect phase inverter INV1 and the output end of phase inverter INV2 respectively；Anti-phase The output end of device INV6 connects the input of phase inverter INV7, and the output end of phase inverter INV7 connects two input nand gate NAND2 Another input；

Overlapping clock-generating circuit does not include 2 two input nand gates and 5 phase inverters to described two-phase, wherein, 2 two input with Not gate is designated as two input nand gate NAND5 and two input nand gate NAND6 respectively, 5 phase inverters be designated as respectively phase inverter INV8, Phase inverter INV9, phase inverter INV10, phase inverter INV11 and phase inverter INV12, the input of phase inverter INV8 connects phase inverter The output end of INV2, the output end of phase inverter INV8 connects an input of two input nand gate NAND5, two input nand gates Another input of NAND5 connects the output end of phase inverter INV12, and the output end connection of two input nand gate NAND5 is anti-phase The input of device INV9；The output end of phase inverter INV9 connects the input of phase inverter INV10, the output end of phase inverter INV10 Connect an input of two input nand gate NAND6, another input of two input nand gate NAND6 connects phase inverter The output end of INV2, the output end of two input nand gate NAND6 connects the input of phase inverter INV11；Phase inverter INV11's is defeated Go out the input that end connects phase inverter INV12.

2. according to claim 1 analog-digital converter clock generation circuit it is characterised in that using clock stable loop produce Stable clock signal, is adjusted to clock stable loop by feeding back signal generating circuit generation feedback signal.