CN105763177B - A kind of hysteresis comparator - Google Patents

Abstract

The invention discloses a hysteresis comparator, which includes a two-stage operational amplifier for providing gain; a positive feedback circuit for obtaining a corresponding threshold voltage according to its setting parameters; an enabling control circuit for controlling the output by outputting an enabling signal The hysteresis comparator is in working state or static. For the hysteresis comparator, introducing a positive feedback circuit inside the operational amplifier is beneficial to integration, and different threshold voltages can be obtained by adjusting relevant parameters of the positive feedback circuit, so that the hysteresis comparator has good output characteristics. In addition, since the enable control circuit is added, the state of the hysteresis comparator can be controlled through the output signal of the enable control circuit, which is beneficial to reduce the power consumption of the hysteresis comparator.

Description

a hysteretic comparator

technical field

The invention relates to the field of electronic technology, in particular to a hysteresis comparator.

Background technique

The comparator takes an analog signal and a reference voltage as an input, and outputs a binary digital signal with only high and low levels, and can be used as an interface circuit between an analog circuit and a digital circuit. Generally, the noise of the comparator near the threshold voltage has a great influence, and the hysteresis comparator introduces positive feedback, which produces a "hysteresis" characteristic at the threshold point and has a strong anti-interference ability. In the prior art, an external positive feedback structure of an integrated operational amplifier is adopted, which is not conducive to circuit integration and has relatively high power consumption. In addition, the threshold voltage cannot be adjusted, resulting in poor output characteristics with hysteresis characteristics.

It can be seen that how to adjust the threshold voltage to obtain good output characteristics is an urgent problem to be solved by those skilled in the art.

Contents of the invention

The object of the present invention is to provide a hysteresis comparator for adjusting the threshold voltage to obtain good output characteristics.

In order to solve the above-mentioned technical problems, the present invention provides a hysteresis comparator, which includes a two-stage operational amplifier for providing gain; a positive feedback circuit for obtaining a corresponding threshold voltage according to its setting parameters; an enabling control circuit for passing An output enable signal controls the hysteresis comparator to be in a working state or static;

The two-stage operational amplifier includes: a differential amplifier circuit, a third NMOS and a current source;

The positive feedback circuit includes: a first inverter, a second inverter, a fifth NMOS, and a sixth NMOS;

Wherein, the gate of the sixth NMOS is connected to the differential amplifier circuit, the drain of the sixth NMOS is connected to the differential amplifier circuit and the gate of the third NMOS, and the source of the sixth NMOS connected to the drain of the fifth NMOS, the source of the fifth NMOS and the source of the third NMOS are grounded, the input terminal of the first inverter and the third NMOS are connected to the The current source is connected, the input terminal of the second inverter is connected with the output terminal of the first inverter, and the output terminal of the second inverter is used as the output terminal of the hysteresis comparator, and is connected with the output terminal of the first inverter. The gate of the fifth NMOS is connected.

Preferably, the differential amplifier circuit specifically includes: a first PMOS, a second PMOS, a first NMOS, and a second NMOS;

Wherein, the gate of the first PMOS is connected to the input voltage terminal, the source of the first PMOS and the source of the second PMOS are connected to the current source, and the drain of the first PMOS is connected to the The drain of the first NMOS is connected to the gate of the first NMOS, the gate of the second PMOS is connected to the reference voltage terminal, and the drain of the second PMOS is connected to the drain of the second NMOS and The drain of the sixth NMOS is connected, the gate of the first NMOS is connected to the gate of the second NMOS, and is connected to the gate of the sixth NMOS, the source of the first NMOS is connected to the second NMOS The source of the NMOS is grounded.

Preferably, the positive feedback circuit further includes a fourth NMOS;

Wherein, the gate of the fourth NMOS is connected to the drain of the NMOS, and is connected to the drain of the sixth NMOS and the gate of the third NMOS, and the source of the fourth NMOS is connected to the drain of the NMOS. The drain of the third NMOS is connected to the input terminal of the first inverter.

Preferably, the enabling control circuit specifically includes: a third inverter, a sixth PMOS, a seventh NMOS, an eighth NMOS, and a ninth NMOS;

Wherein, the input terminal of the third inverter and the gate of the sixth PMOS are used as the input terminal of the enabling control circuit, the output terminal of the third inverter is connected to the gate of the seventh NMOS pole, the gate of the eighth NMOS, the gate of the ninth NMOS are connected to the current source, the drain of the seventh NMOS is connected to the gate of the first NMOS and the gate of the second NMOS are connected, the drain of the eighth NMOS is connected to the gate of the fourth NMOS, the drain of the ninth NMOS is connected to the input terminal of the first inverter, and the source of the seventh NMOS , the source of the eighth NMOS and the source of the ninth NMOS are grounded, the source of the sixth PMOS is connected to the positive power supply terminal, and the drain of the sixth PMOS is connected to the current source.

Preferably, the current source specifically includes a third PMOS, a fourth PMOS, a fifth PMOS, and a seventh PMOS;

Wherein, the source of the third PMOS, the source of the fourth PMOS and the source of the fifth PMOS are all connected to the source of the sixth PMOS, and the drain of the third PMOS is connected to the source of the sixth PMOS. The gate of the third PMOS is connected, and is connected with the source of the seventh PMOS and the drain of the sixth PMOS, the gate of the fourth PMOS, the gate of the third PMOS and the The gates of the fifth PMOS are all connected, the drain of the fourth PMOS is connected to the source of the first PMOS and the source of the second PMOS, and the drain of the fifth PMOS is connected to the first PMOS. The input terminal of the inverter is connected, the drain of the seventh PMOS is connected to the input terminal of the bias circuit, and the gate of the seventh PMOS is connected to the output terminal of the third inverter.

Preferably, when the input signal of the input terminal of the enable control circuit is 1, the hysteresis comparator is controlled to be in the working state;

When the input signal at the input terminal of the enabling control circuit is 0, the hysteresis comparator is controlled to be static.

In the hysteresis comparator provided by the present invention, introducing a positive feedback circuit inside the operational amplifier facilitates integration, and different threshold voltages can be obtained by adjusting relevant parameters of the positive feedback circuit, so that the hysteresis comparator has good output characteristics. In addition, since the enable control circuit is added, the state of the hysteresis comparator can be controlled through the output signal of the enable control circuit, which is beneficial to reduce the power consumption of the hysteresis comparator.

Description of drawings

In order to illustrate the embodiments of the present invention more clearly, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. As far as people are concerned, other drawings can also be obtained based on these drawings on the premise of not paying creative work.

Fig. 1 is the structural diagram of the hysteresis comparator that embodiment one provides;

Fig. 2 is the hysteresis comparator circuit diagram that embodiment two provides;

Fig. 3 is the equivalent circuit diagram of Fig. 2 provided by the present invention;

4 is a schematic diagram of the voltage transfer characteristics of the hysteresis comparator provided by the present invention;

Among them, P1—first PMOS, P2—second PMOS, P3—third PMOS, P4—fourth PMOS, P5—fifth PMOS, P6—sixth PMOS, P7—seventh PMOS, N1—first NMOS, N2—second NMOS, N3—third NMOS, N4—fourth NMOS, N5—fifth NMOS, N6—sixth NMOS, N7—seventh NMOS, N8—eighth, NMOS N9—ninth NMOS, INV1— The first inverter, INV2—the second inverter, INV3—the third inverter.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The core of the present invention is to provide a hysteresis comparator.

In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

Embodiment one

FIG. 1 is a structural diagram of a hysteresis comparator provided in Embodiment 1. As shown in Figure 1, the hysteresis comparator includes a two-stage operational amplifier 1 for providing gain; a positive feedback circuit 2 for obtaining a corresponding threshold voltage according to its setting parameters; an enabling control circuit 3 for enabling the The hysteresis comparator can be controlled by signal to be in working state or static;

The two-stage operational amplifier 1 includes: a differential amplifier circuit, a third NMOS and a current source;

The positive feedback circuit 2 includes: a first inverter, a second inverter, a fifth NMOS, and a sixth NMOS;

Wherein, the gate of the sixth NMOS is connected to the differential amplifier circuit, the drain of the sixth NMOS is connected to the gate of the differential amplifier circuit and the third NMOS, the source of the sixth NMOS is connected to the drain of the fifth NMOS, and the drain of the fifth NMOS is connected to the gate of the third NMOS. The source of the NMOS and the source of the third NMOS are grounded, the input of the first inverter and the third NMOS are connected to the current source, the input of the second inverter is connected to the output of the first inverter, and the input of the first inverter is connected to the output of the first inverter. The output terminals of the two inverters serve as the output terminals of the hysteresis comparator and are connected with the gate of the fifth NMOS.

As shown in FIG. 1 , the hysteresis comparator includes three parts, a two-stage operational amplifier 1 , a positive feedback circuit 2 and an enabling control circuit 3 . In a specific implementation, the two-stage operational amplifier 1 provides an output voltage to provide working conditions for the hysteresis comparator. The positive feedback circuit 2 is introduced into the two-stage operational amplifier 1 , and different threshold voltages can be obtained by adjusting the relevant parameters of the fifth NMOS and the sixth NMOS in the positive feedback circuit 2 . Therefore, in a specific implementation, the fifth NMOS and the sixth NMOS with different parameters can be selected according to actual requirements, so that the threshold voltage can be adjusted to achieve the function of a hysteresis comparator.

Since the hysteresis comparator is usually integrated in other circuits, in order to cooperate with other circuits, the hysteresis comparator is usually in the working state, causing each device in the hysteresis comparator to be in the working state, so the power consumption is relatively high. It can be understood that, in some cases, the hysteresis comparator does not need to work, so the state of the hysteresis comparator can be controlled by the enable control circuit 3 in the present invention. For example, when the enabling control circuit 3 outputs a signal, the hysteresis comparator is in an active state, and when the enabling control circuit 3 outputs another signal, the hysteresis comparator is in a static state, that is, in a non-operating state.

For the hysteresis comparator provided in this embodiment, introducing a positive feedback circuit inside the operational amplifier facilitates integration, and different threshold voltages can be obtained by adjusting related parameters of the positive feedback circuit, so that the hysteresis comparator has good output characteristics. In addition, since the enable control circuit is added, the state of the hysteresis comparator can be controlled through the output signal of the enable control circuit, which is beneficial to reduce the power consumption of the hysteresis comparator.

Embodiment two

FIG. 2 is a circuit diagram of the hysteresis comparator provided by the second embodiment. FIG. 3 is an equivalent circuit diagram of FIG. 2 provided by the present invention. FIG. 4 is a schematic diagram of voltage transfer characteristics of the hysteresis comparator provided by the present invention. As shown in FIG. 2 , the differential amplifier circuit of the two-stage operational amplifier 1 specifically includes: a first PMOS, a second PMOS, a first NMOS, and a second NMOS;

Wherein, the gate of the first PMOS is connected to the input voltage terminal V _in , the source of the first PMOS and the source of the second PMOS are connected to the current source, the drain of the first PMOS is connected to the drain of the first NMOS and the first The gate of the NMOS is connected, the gate of the second PMOS is connected to the reference voltage terminal, the drain of the second PMOS is connected to the drain of the second NMOS and the drain of the sixth NMOS, the gate of the first NMOS is connected to the second NMOS The gate of the first NMOS is connected to the gate of the sixth NMOS, and the source of the first NMOS and the source of the second NMOS are grounded.

Preferably, the positive feedback circuit 2 also includes a fourth NMOS;

Wherein, the gate of the fourth NMOS is connected with the NMOS drain, and is connected with the drain of the sixth NMOS and the gate of the third NMOS, and the source of the fourth NMOS is connected with the drain of the third NMOS and the first inverter input connection.

Preferably, the enabling control circuit 3 specifically includes: a third inverter, a sixth PMOS, a seventh NMOS, an eighth NMOS, and a ninth NMOS;

Wherein, the input end of the third inverter and the gate of the sixth PMOS are used as the input end EN of the enable control circuit, the output end of the third inverter is connected to the gate of the seventh NMOS, the gate of the eighth NMOS, The gate of the ninth NMOS is connected to the current source, the drain of the seventh NMOS is connected to the gate of the first NMOS and the gate of the second NMOS, the drain of the eighth NMOS is connected to the gate of the fourth NMOS, and the drain of the ninth NMOS is connected to the gate of the fourth NMOS. The drain of the NMOS is connected to the input terminal of the first inverter, the source of the seventh NMOS, the source of the eighth NMOS, and the source of the ninth NMOS are grounded, the source of the sixth PMOS is connected to the positive terminal of the power supply, and the source of the sixth NMOS is connected to the positive terminal of the power supply. The drains of the six PMOSs are connected to the current source.

Preferably, the current source specifically includes a third PMOS, a fourth PMOS, a fifth PMOS, and a seventh PMOS;

Wherein, the source of the third PMOS, the source of the fourth PMOS and the source of the fifth PMOS are all connected to the source of the sixth PMOS, the drain of the third PMOS is connected to the gate of the third PMOS, and connected to the gate of the sixth PMOS. The source of the seventh PMOS is connected to the drain of the sixth PMOS, the gate of the fourth PMOS, the gate of the third PMOS and the gate of the fifth PMOS are all connected, and the drain of the fourth PMOS is connected to the source of the first PMOS It is connected to the source of the second PMOS, the drain of the fifth PMOS is connected to the input of the first inverter, the drain of the seventh PMOS is connected to the input of the bias circuit, and the gate of the seventh PMOS is connected to the third The output terminal of the inverter is connected.

The above part is a description of the specific connection structure in FIG. 2 , and the working principle of the hysteresis comparator will be described in detail below.

1) When the voltage Vin of the input voltage terminal < the voltage Vref of the reference voltage terminal, point A is low level, the third NMOS is cut off, point C is high level, point D is high level, and the fifth NMOS is turned on; when Vin When increasing, I2 and I1 decrease, and when IA>I2+I1, refer to Figure 4, the critical voltage Vin=Vref+Vth at this time, point A is high level, the third NMOS transistor is turned on, C, D point is low level, and the fifth NMOS transistor is cut off.

2) When Vin>Vref, point A is high level, the third NMOS transistor is turned on, points C and D are low level, the fifth NMOS transistor is cut off, I1=0; when Vin decreases, IB increases, When IA<I2, referring to FIG. 4 , the critical voltage Vin=Vref at this time, point A is at low level, the third NMOS transistor is cut off, and points C and D are at high level. The function of the fourth NMOS transistor is to speed up the conversion speed of the critical point. When the IA rises to the critical point, the fourth NMOS transistor is turned on and is in the saturation region, which will divert a large part of the current of the IC, so that the IA rises very quickly. Thereby accelerating the jump of the C point potential. Now quantitatively analyze the threshold voltage Vth of the hysteresis comparator. When reaching the critical point, IA=I1+I2, I1, I2 and IB constitute the relationship of the mirror current, I2=IB, I1=mIB (m is the sixth NMOS and the first, the first (2) aspect ratio ratio coefficient of NMOS), IA=(m+1)IB can be obtained. According to the current equation of IA and IB:

In the formula, Vs is the voltage at point S in the circuit; Vtp is the threshold voltage of the first PMOS and the second PMOS, which is generally a constant of 0.9V at room temperature; μp is the hole mobility, which is a constant, and Cox is the gate oxide per unit area The layer capacitance is a constant. According to the relationship between IA and IB, the relationship between Vin and Vref can be calculated, and then Vth can be obtained. It can also be seen from this that the size of Vth can be adjusted by adjusting the width-to-length ratio of the sixth NMOS tube.

As preferably, when the input signal of the input terminal of the enable control circuit is 1, the control hysteresis comparator is in the working state;

When the input signal at the input terminal of the enabling control circuit is 0, the hysteresis comparator is controlled to be static.

When EN is 1, the hysteresis comparator is in working state, the sixth PMOS is off, point E is at low level, the seventh NMOS, the eighth NMOS, and the ninth NMOS are off, and the seventh PMOS is on. size to obtain the required bias current.

When EN is 0, the hysteresis comparator is static, the sixth PMOS is turned on, the structure of the current source is destroyed, no bias current is generated, point E is at high level, the seventh NMOS, the eighth NMOS, and the ninth NMOS are turned on, The output of each level is pulled low, and the output of the hysteresis comparator is stable at 0, so as to avoid power loss caused by the occurrence of indeterminate states. The enabling control circuit can stabilize the working state and the static state of the hysteresis comparator, and is beneficial to the embedded integration of the circuit.

It can be seen that in the enable control circuit 3, the sixth PMOS controls the hysteresis comparator to be in the working state or static; the seventh NMOS, the eighth NMOS, and the ninth NMOS make the state of the hysteresis comparator in the static state more stable.

The hysteresis comparator provided by the present invention has been introduced in detail above. Each embodiment in the description is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and for the related information, please refer to the description of the method part. It should be pointed out that for those skilled in the art, without departing from the principle of the present invention, some improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Professionals can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software or a combination of the two. In order to clearly illustrate the possible For interchangeability, in the above description, the composition and steps of each example have been generally described according to their functions. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present invention.

The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be directly implemented by hardware, software modules executed by a processor, or a combination of both. Software modules can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other Any other known storage medium.

Claims (6)

1. a kind of hysteresis comparator, which is characterized in that including two-stage calculation amplifier, for providing gain；Positive-feedback circuit is used According to the corresponding threshold voltage of its arrange parameter acquisition；Enabled control circuit, for by exporting described in enable signal control Hysteresis comparator is in running order or static；

The two-stage calculation amplifier includes：Differential amplifier circuit, the 3rd NMOS and current source；

The positive-feedback circuit includes：First phase inverter, the second phase inverter, the 5th NMOS, the 6th NMOS；

Wherein, the grid of the 6th NMOS is connect with the differential amplifier circuit, drain electrode and the difference of the 6th NMOS Amplifying circuit is divided to be connected with the grid of the 3rd NMOS, the source electrode of the 6th NMOS connects with the drain electrode of the 5th NMOS It connects, the source electrode ground connection of the source electrode of the 5th NMOS and the 3rd NMOS, the input terminal of first phase inverter and described the Three NMOS are connect with the current source, and the input terminal of second phase inverter is connect with the output end of first phase inverter, institute Output end of the output end of the second phase inverter as the hysteresis comparator is stated, and is connect with the grid of the 5th NMOS.

2. hysteresis comparator according to claim 1, which is characterized in that the differential amplifier circuit specifically includes：First PMOS, the 2nd PMOS, the first NMOS and the 2nd NMOS；

Wherein, the grid of the first PMOS is connect with Input voltage terminal, the source electrode and the 2nd PMOS of the first PMOS Source electrode connect with the current source, the drain electrode and the first NMOS of the drain electrode of the first PMOS with the first NMOS Grid connects, and the grid of the 2nd PMOS is connect with reference voltage end, drain electrode and the 2nd NMOS of the 2nd PMOS Drain electrode connected with the drain electrode of the 6th NMOS, the grid connection of the grid of the first NMOS and the 2nd NMOS, and with institute State the grid connection of the 6th NMOS, the source electrode of the first NMOS and the source electrode ground connection of the 2nd NMOS.

3. hysteresis comparator according to claim 2, which is characterized in that the positive-feedback circuit further includes the 4th NMOS；

Wherein, the grid of the 4th NMOS and the 4th NMOS drain electrode connects, and with the drain electrode of the 6th NMOS and institute State the grid connection of the 3rd NMOS, the drain electrode of the source electrode of the 4th NMOS and the 3rd NMOS and first phase inverter Input terminal connects.

4. hysteresis comparator according to claim 3, which is characterized in that the enabled control circuit specifically includes：Third Phase inverter, the 6th PMOS, the 7th NMOS, the 8th NMOS and the 9th NMOS；

Wherein, input of the grid of the input terminal of the third phase inverter and the 6th PMOS as the enabled control circuit End, the output end of the third phase inverter and the grid of the 7th NMOS, grid, the 9th NMOS of the 8th NMOS Grid connected with the current source, the grid of the drain electrode and the grid and the 2nd NMOS of the first NMOS of the 7th NMOS It is all connected with, the drain electrode of the 8th NMOS is connect with the grid of the 4th NMOS, the drain electrode of the 9th NMOS and described the The input terminal of one phase inverter connects, the source electrode of the 7th NMOS, the source electrode of the 8th NMOS, the 9th NMOS source electrode Ground connection, the source electrode of the 6th PMOS are connect with power positive end, and the drain electrode of the 6th PMOS is connect with the current source.

5. hysteresis comparator according to claim 4, which is characterized in that the current source specifically includes the 3rd PMOS, Four PMOS, the 5th PMOS and the 7th PMOS；

Wherein, the source electrode of the source electrode of the 3rd PMOS, the source electrode of the 4th PMOS and the 5th PMOS is with described The source electrode of six PMOS connects, and the drain electrode of the 3rd PMOS is connected with the grid of the 3rd PMOS, and with the 7th PMOS Source electrode connected with the drain electrode of the 6th PMOS, the grid of the 4th PMOS, the grid of the 3rd PMOS and described The grid of five PMOS is all connected with, the source electrode of the drain electrode and the source electrode and the 2nd PMOS of the first PMOS of the 4th PMOS Connection, the drain electrode of the 5th PMOS are connect with the input terminal of first phase inverter, the drain electrode and biasing of the 7th PMOS The input terminal of circuit connects, and the grid of the 7th PMOS is connect with the output end of the third phase inverter.

6. hysteresis comparator according to claim 1 or 5, which is characterized in that the input terminal of the enabled control circuit When input signal is 1, it is in running order to control the hysteresis comparator；

When the input signal of the input terminal of the enabled control circuit is 0, controls the hysteresis comparator and be in static state.