CN103997204B - Charge pump circuit - Google Patents

Abstract

The invention discloses a charge pump circuit. The charge pump circuit is provided with a voltage output end and comprises a voltage source module, a feedback circuit, a comparator, a first PMOS transistor, a second PMOS transistor and a control circuit. The voltage source module provides a driving voltage. The feedback circuit provides a feedback voltage associated with the voltage output. The comparator compares the reference voltage with the feedback voltage to generate an error signal. The control circuit is configured to generate a detection signal by sampling the error signal at least twice according to the oscillation signal in a time domain, switch the first PMOS transistor through the detection signal and the error signal, and switch the second PMOS transistor through the error signal, thereby stabilizing a voltage level of the voltage output terminal.

Description

charge pump circuit

technical field

The present invention relates to a voltage stabilizing technology, and in particular to a charge pump circuit.

Background technique

With the development of electronic technology tending to be smaller and thinner, the driving voltage of today's electronic components, such as processors and memories, is gradually reduced. In addition, the tolerable range of the voltage ripple of the driving voltage is also reduced accordingly, so that the electronic components can work at a precise voltage.

Furthermore, the driving voltage of the electronic components may be provided by a charge pump circuit. The charge pump circuit raises (or lowers) its input voltage level by a predetermined ratio to generate voltages of different levels. When the output terminal of the charge pump circuit has a current change due to the load change, if the current cannot be detected and changed in real time, the output voltage will produce severe ripples with the change of the load current.

In order to stabilize the output voltage of the charge pump circuit, in the past, multiple comparators were used to detect level changes, and then adjust the output voltage to a desired level. For this analog detection mechanism, the circuit design is complicated due to the use of multiple comparators, and it is easy to increase power consumption and increase manufacturing cost.

Contents of the invention

In view of this, the object of the present invention is to provide a charge pump circuit in order to solve one of the problems mentioned in the prior art and/or other problems.

An embodiment of the present invention provides a charge pump circuit, which includes: a voltage source module, a feedback circuit, a comparator, a first PMOS transistor, a second PMOS transistor, and a control circuit. The charge pump circuit has a voltage output. The voltage source block includes a positive charge pump. The voltage source module is configured to provide a driving voltage. The feedback circuit is coupled to the voltage output terminal and provides a feedback voltage associated with the voltage output terminal. The comparator is coupled to the feedback circuit and the voltage source module, and compares the reference voltage and the feedback voltage to generate an error signal. The source of the first PMOS transistor is coupled to the driving voltage, and the drain of the first PMOS transistor is coupled to the voltage output terminal. The source of the second PMOS transistor is coupled to the driving voltage, and the drain of the second PMOS transistor is coupled to the voltage output terminal. The control circuit is coupled to the voltage source module, the comparator, the first PMOS transistor, and the second PMOS transistor. The control circuit is configured to generate a detection signal in the time domain according to the oscillation signal and the error signal at least twice, through the detection signal and the error The first PMOS transistor is switched by the error signal, and the second PMOS transistor is switched by the error signal, so as to stabilize the voltage level of the voltage output terminal.

In an exemplary embodiment of the present invention, the voltage source module includes an oscillator, an OR gate, a clock generator, and a positive charge pump. The oscillator is used to generate an oscillating signal. The OR gate receives the oscillation signal and the error signal. The clock generator is used for generating a clock signal according to the oscillation signal or the error signal. The positive charge pump generates the driving voltage according to the clock signal.

In an exemplary embodiment of the present invention, the feedback circuit includes a PMOS transistor string coupled between the voltage output terminal and the ground terminal.

In an exemplary embodiment of the present invention, the drain of each PMOS transistor in the PMOS transistor string is coupled to its own gate.

In an exemplary embodiment of the present invention, the inverting input terminal of the comparator is coupled to the reference voltage, and the non-inverting input terminal of the comparator is coupled to the feedback voltage.

In an exemplary embodiment of the present invention, the first PMOS transistor has a relatively wider channel width than the second PMOS transistor.

In an exemplary embodiment of the present invention, the channel widths of the first PMOS transistor and the second PMOS transistor are 90 microns and 10 microns, respectively.

In an exemplary embodiment of the present invention, the control circuit includes a detection circuit, a first switch control unit and a second switch control unit. The detection circuit receives the oscillating signal and the error signal, and the detection circuit is configured to sample the error signal respectively according to the rising edge and the falling edge of the oscillating signal. The first switch control unit switches the first PMOS transistor according to the detection signal and the error signal. The second switch control unit switches the second PMOS transistor according to the error signal.

In an exemplary embodiment of the invention, the detection circuit includes a first flip-flop, a second flip-flop and a NOR gate. The input terminal of the first flip-flop receives the detection signal, and the clock input terminal of the first flip-flop receives the oscillation signal. The input end of the second flip-flop receives the detection signal, and the inverting clock input end of the second flip-flop receives the oscillation signal. The first input terminal and the second input terminal of the NOR gate are respectively coupled to the output terminals of the first flip-flop and the second inverter, and the output terminal of the NOR gate outputs a detection signal.

In an exemplary embodiment of the present invention, when the control circuit determines that the voltage level of the voltage output terminal is within a predetermined ripple range, the first PMOS transistor is turned off.

Based on the above, in the present invention, since the control circuit samples the error signal at least twice in the time domain according to the oscillating signal to generate a detection signal, the first PMOS transistor is switched by the detection signal and the error signal, and the first PMOS transistor is switched by the error signal. Two PMOS transistors, and the first PMOS transistor may have a relatively wider channel width than the second PMOS transistor. Therefore, the voltage level output by the charge pump circuit can be properly adjusted without generating excessive voltage ripple, thereby solving the problems mentioned in the prior art.

It should be understood that the above-mentioned general description and the following specific embodiments are only illustrative and explanatory, and shall not limit the scope of the claimed claims of the present invention.

Description of drawings

The accompanying drawings, which are a part of the specification of the invention, illustrate example embodiments of the invention and together with the description serve to explain the principles of the invention.

FIG. 1 is a circuit block diagram of a charge pump circuit (charge pump circuit) 10 according to an exemplary embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating the implementation of the control circuit 140 in FIG. 1 .

3 and 4 are partial operation waveform diagrams of the detection circuit 142 in FIG. 2 .

Wherein, the reference signs are explained as follows:

10: Charge pump circuit

110: Voltage source module

112: Oscillator

114: OR gate

116: Clock generator

118: Positive charge pump

120: Feedback circuit

120_1～120_5: PMOS transistors

130: Comparator

140: Control circuit

142: detection circuit

144: First switch control unit

146: Second switch control unit

202: First Trigger

204: Second trigger

206: NOR Gate

A, B: sampling content

GND: ground terminal

Sdet: error signal

Shvosc: Oscillating signal

Sosc: clock signal

Svpon: heartbeat

SW1: First PMOS transistor

SW2: Second PMOS transistor

T_PUMP: voltage output terminal

Vdrive: drive voltage

Vfdbk: feedback voltage

Vpump: output voltage

Vref: reference voltage

detailed description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. In addition, elements/components using the same or similar symbols in the drawings and embodiments represent the same or similar parts.

FIG. 1 is a circuit block diagram of a charge pump circuit (charge pump circuit) 10 according to an exemplary embodiment of the present invention. 1, the charge pump circuit 10 includes a voltage source module (voltage source module) 110, a feedback circuit (feedback circuit) 120, a comparator (comparator) 130, a first PMOS transistor (first PMOS transistor) SW1, a second PMOS transistor (second PMOS transistor) SW2 and a control circuit (control circuit) 140 .

The charge pump circuit 10 has a voltage output T_PUMP. The voltage source module 110 includes a positive charge pump 118 . The voltage source module 110 is configured to provide a driving voltage Vdrive. The feedback circuit 120 is coupled to the voltage output terminal T_PUMP and provides a feedback voltage Vfdbk associated with the voltage output terminal T_PUMP. The comparator 130 is coupled to the feedback circuit 120 and the voltage source module 110 . The comparator 130 compares the reference voltage Vref and the feedback voltage Vfdbk to generate an error signal Sdet. The source of the first PMOS transistor SW1 is coupled to the driving voltage Vdrive, and the drain of the first PMOS transistor SW1 is coupled to the voltage output terminal T_PUMP. The source of the second PMOS transistor SW2 is coupled to the driving voltage Vdrive, and the drain of the second PMOS transistor SW2 is coupled to the voltage output terminal T_PUMP.

In this exemplary embodiment, the control circuit 140 is coupled to the voltage source module 110 , the comparator 130 , the first PMOS transistor SW1 and the second PMOS transistor SW2 . The first PMOS transistor SW1 may have a relatively wider channel width than the second PMOS transistor SW2. For example, the channel widths of the first PMOS transistor SW1 and the second PMOS transistor SW2 are respectively 90 micrometers and 10 micrometers (micrometer, μm), but not limited thereto.

The control circuit 140 is configured to generate the detection signal Svpon by sampling the error signal Sdet at least twice in the time domain according to the oscillating signal Shvosc. The first PMOS transistor SW1 is switched by the detection signal Svpon and the error signal Sdet, and the second PMOS transistor SW2 is switched by the error signal Sdet. In addition, it is assumed that the channel widths of the first PMOS transistor SW1 and the second PMOS transistor SW2 are 90 microns and 10 microns respectively. When the first PMOS transistor SW1 and the second PMOS transistor SW2 are turned on at the same time, it has the level effect of quickly adjusting (similar to coarse adjustment, channel width 100 microns) the output voltage Vpump; while only turning on the second PMOS transistor SW2 can produce Microstep adjustment (similar to fine adjustment, channel width 10 microns) level effect of the output voltage Vpump can avoid excessive voltage rise (or voltage burst).

For example, when the voltage level of the output voltage Vpump at the voltage output terminal T_PUMP has not reached the preset level, if both the first PMOS transistor SW1 and the second PMOS transistor SW2 are turned on (the channel width is equivalent to 100 microns), In order to make the output voltage Vpump quickly reach the preset level. After the output voltage Vpump reaches the preset level, if the output voltage Vpump does not fall below the preset level (preset ripple range) of ±0.1% over time, the control circuit 140 only switches the second PMOS The transistor SW2 (the channel width is equivalent to 10 microns), and the first PMOS transistor SW1 is turned off. And after the output voltage Vpump reaches the preset level, if the output voltage Vpump decreases over time by exceeding the preset level, for example 0.1%, the control circuit 140 can switch the first PMOS transistor SW1 and the second PMOS transistor SW2 again, to quickly adjust to preset levels. Therefore, the control circuit 140 can reduce the ripple variation of the output voltage Vpump, so the voltage level of the voltage output terminal T_PUMP can be stabilized.

On the other hand, the voltage source module 110 may include an oscillator 112 , an OR gate 114 , a clock generator 116 , and a positive charge pump 118 . The oscillator 112 is used to generate an oscillating signal Shvosc. The OR gate 114 receives the oscillation signal Shvosc and the error signal Sdet. The clock generator 116 is used for generating the clock signal Sosc according to the oscillation signal Shvosc or the error signal Sdet. The positive charge pump 118 generates the driving voltage Vdrive according to the clock signal Sosc. When the error signal Sdet generated by the comparator 130 represents a logic 1, it means that the output voltage Vpump has reached a preset level, and the OR gate 114 also outputs a logic 1 to turn off the clock generator 116 .

The feedback circuit 120 may include a PMOS transistor string composed of PMOS transistors 120_1 - 120_5 . The PMOS transistor strings ( 120_1 - 120_5 ) are coupled between the voltage output terminal T_PUMP and the ground terminal GND. The coupling of the PMOS transistors 120_4 and 120_5 can provide the feedback voltage Vfdbk. In addition, the feedback voltage Vfdbk can also be provided at the coupling position (not shown) of the PMOS transistors 120_3 and 120_4 , so the feedback voltage Vfdbk can be proportional to the output voltage Vpump. In addition, the drain of each PMOS transistor in the PMOS transistor strings ( 120_1 - 120_5 ) is coupled to its own gate, and this connection can produce an effect similar to that of a diode. The PMOS transistor string can also be replaced with a resistor string, but the PMOS transistor string can pass a smaller current.

The inverting input terminal of the comparator 130 is coupled to the reference voltage Vref, and the non-inverting input terminal of the comparator is coupled to the feedback voltage Vfdbk.

More clearly, the control circuit 140 includes a detection circuit 142 , a first switch control unit 144 and a second switch control unit 146 . As shown in FIG. 2 , the detection circuit 142 may include a first flip-flop 202 , a second flip-flop 204 and a NOR gate 206 . An input terminal of the first flip-flop 202 receives the detection signal Sdet, and a clock input terminal thereof receives the oscillation signal Shvosc. An input terminal of the second flip-flop 204 receives the detection signal Sdet, and an inverting clock input terminal thereof receives the oscillation signal Shvosc. The first input terminal and the second input terminal of the NOR gate 206 are respectively coupled to the output terminals of the first flip-flop 202 and the second flip-flop 204 , and the output terminal of the NOR gate 206 outputs the detection signal Svpon.

3 and 4 are partial operation waveform diagrams of the detection circuit 142 in FIG. 2 . Please refer to Figure 2 to Figure 4 together. It can be clearly seen from FIG. 3 that the detection circuit 142 receives the oscillation signal Shvosc and the error signal Sdet. For sampling, when the sampled contents of the first flip-flop 202 and the second flip-flop 204 are represented by symbols A and B respectively, A=0 and B=0. Then, the sampled contents A and B are passed through the NOR gate 206 to generate and output a logic 1 detection signal Svpon.

In addition, it can be clearly seen from FIG. 4 that the detection circuit 142 samples the error signal Sdet once on the rising edge and falling edge of the oscillation signal Shvosc respectively, wherein the sampled contents of the first flip-flop 202 and the second flip-flop 204 are respectively When represented by symbols A and B, A=0 and B=1. Then, the sampled contents A and B are passed through the NOR gate 206 to generate and output a logic 0 detection signal Svpon.

Table 1 shows the corresponding relationship between the sampling content, the truth table of the detection signal, and the working state.

【Table 1】

On the other hand, although Table 1 uses the first PMOS transistor SW1 and the second PMOS transistor SW2 as an implementation mode, those skilled in the art can change the design of the detection circuit 142 based on actual design or application requirements, so that the control circuit 140 More than two PMOS transistors with different channel widths can be correspondingly controlled.

Based on the above, the control circuit 140 uses a digital detection mechanism to detect signals in the time domain. Therefore, compared with the existing analog detection mechanism, the circuit design of the present invention is relatively simple, does not increase additional power consumption, and can also reduce manufacturing costs. .

In summary, in the present invention, since the control circuit samples the error signal at least twice in the time domain according to the oscillating signal to generate a detection signal, and then switches the first PMOS transistor through the detection signal and the error signal, and can pass the error signal to switch the second PMOS transistor, and the first PMOS transistor may have a relatively wide channel width relative to the second PMOS transistor. Therefore, the voltage level output by the charge pump circuit can be properly adjusted without generating excessive voltage ripple, thereby solving the problems mentioned in the prior art.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention shall be defined by the scope of the appended patent claims.

In addition, any embodiment of the present invention or the scope of patent claims of the application does not necessarily achieve all the objects or advantages or features disclosed in the present invention. In addition, the abstract and the title are only used to assist in the search of patent documents, and are not used to limit the scope of the claims of the present invention.

Claims (10)

1. a charge pump circuit, has a voltage output end, and this charge pump circuit includes:

One voltage source module, including a malleation electric charge pump, this voltage source module is configured to carry For a driving voltage；

One feedback circuit, couples this voltage output end, and offer is associated with this voltage output end A feedback voltage；

One comparator, couples this feedback circuit and this voltage source module, compares a reference voltage An error signal is produced with this feedback voltage；

One first PMOS transistor, its source electrode couples this driving voltage, and its drain electrode couples this Voltage output end；

One second PMOS transistor, its source electrode couples this driving voltage, and its drain electrode couples this Voltage output end；And

One control circuit, couples this voltage source module, this comparator, a PMOS crystalline substance Body pipe and this second PMOS transistor, this control circuit is configured in time domain according to one Oscillator signal samples at least twice and produces a detection signal in this error signal, by this inspection Survey signal and switch this first PMOS transistor with this error signal, and believed by this error Number switch this second PMOS transistor, thus stablize the voltage level of this voltage output end.

2. charge pump circuit as claimed in claim 1, wherein this voltage source module includes:

One oscillator, in order to produce this oscillator signal；

One or door, receive this oscillator signal and this error signal；

One clock pulse generator, in order to produce according to this oscillator signal or this error signal for the moment Arteries and veins signal；And

This malleation electric charge pump, produces this driving voltage according to this clock signal.

3. charge pump circuit as claimed in claim 1, wherein this feedback circuit includes:

One PMOS transistor string, is coupled between this voltage output end and an earth terminal.

4. charge pump circuit as claimed in claim 3, wherein this PMOS transistor string In the drain electrode of each PMOS transistor couple itself grid.

5. charge pump circuit as claimed in claim 1, the wherein anti-phase input of this comparator End couples this reference voltage, and the non-inverting input of this comparator couples this feedback voltage.

6. charge pump circuit as claimed in claim 1, a wherein PMOS crystal Pipe has relatively wide channel width relative to this second PMOS transistor.

7. charge pump circuit as claimed in claim 6, a wherein PMOS crystal Pipe is respectively 90 microns and 10 microns with the channel width of this second PMOS transistor.

8. charge pump circuit as claimed in claim 1, wherein this control circuit includes:

One testing circuit, receives this oscillator signal and this error signal, and this testing circuit is at this This error signal is sampled by the rising edge of oscillator signal, and this testing circuit is at this The drop edge of oscillator signal carries out another sub-sampling to this error signal；

One first switch control unit, switches this according to this detection signal and this error signal First PMOS transistor；And

One second switch control unit, switches the 2nd PMOS according to this error signal brilliant Body pipe.

9. charge pump circuit as claimed in claim 8, wherein this testing circuit includes:

One first trigger, its input receives this detection signal, and its clock input receives This oscillator signal；

One second trigger, its input receives this detection signal, its anti-phase clock input Receive this oscillator signal；And

One nor gate, its first input end, the second input are respectively coupled to this first trigger With the output of this second trigger, the output of this nor gate exports this detection signal.

10. charge pump circuit as claimed in claim 1, wherein judges when this control circuit Go out the voltage level of this voltage output end when one presets in the range of ripple, then close this first PMOS transistor.