CN106298553A - 封装模组及其制作方法 - Google Patents
封装模组及其制作方法 Download PDFInfo
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Abstract
本发明实施例公开了一种封装模组及其制作方法,该制作方法包含放置具有多个引脚的一引脚架于一电路基板上,接合引脚与电路基板上所对应的接合区,使引脚连接于接合区,切除引脚架的一连接部,以及弯折引脚,使引脚垂直于电路基板。通过引脚架将引脚设置在电路基板对应的接合区上,而后再切除连接部并折弯引脚,可以大幅提升封装模组的组装效率。
Description
技术领域
本发明是关于一种封装模组及其制作方法,且特别是关于一种外壳封装的封装模组及其制作方法。
背景技术
高效率、高密度以及高可靠性一直是现今电子装置的发展趋势,以达到节能、降低成本、以及良好的使用寿命的目的。举例而言,集成功率模组(Integrated Power Module,IPM),将多个半导体器件集成在一个器件封装里,为提升封装内的空间利用率提供了可能。
功率模块的封装形式种类繁多,如金属封装(Metal Packaging)、陶瓷封装(Ceramic Packaging)、塑胶封装(Plastic Packaging)等,其中塑胶封装具有较高的性价比,因此在民用以及工业应用的领域被大规模使用。
塑胶封装亦可再细分为塑封料(molding compound)封装与外壳(housing)封装两大类。塑封料封装是将塑封料包覆于元件以及基板以起到绝缘保护、环境保护、机械保护的功能。由于塑封料和其余材料之间热膨胀系数(CTE)不一致,故引起的热应力也会相应增加。所以,通常此类封装形式不易将尺寸做的非常大,从而在大功率领域应用被限制。
外壳封装则是采用独立的外壳实现元件的机械保护、电气绝缘等,然而,此种类型的封装组装较为费时费力,亦不利于大规模生产。
发明内容
因此,本发明便提出了一种封装模组的制造方法,可以用以提升外壳封装类型的封装模组的组装效率。
本发明的一实施方式提供了一种封装模组的制作方法,包含放置具有多个引脚的一引脚架于一电路基板上;接合引脚与电路基板上所对应的接合区,使引脚连接于接合区;切除引脚架的一连接部;以及弯折引脚,使引脚垂直于电路基板。
于一或多个实施例中,封装模组的制作方法还包含组装一外壳于电路基板,其中外壳具有多个穿孔,以供弯折的引脚穿过而外露于外壳。
于一或多个实施例中,封装模组的制作方法还包含填充一保护胶于外壳内,使保护胶覆盖电路基板。
于一或多个实施例中,封装模组的制作方法还包含设置一焊料于电路基板的接合区上;以及加热焊料。
于一或多个实施例中,封装模组的制作方法还包含设置多个电子元件于电路基板;以及打线接合部分的电子元件的接点至部分的接合区。
于一或多个实施例中,封装模组的制作方法还包含将引脚的弯折部进行变截面处理。变截面积处理包含将引脚的弯折部于厚度方向或宽度方向进行开槽、通孔或缩减。
本发明的另一实施方式提供了由上述方法所制作的封装模组。
本发明的又一实施方式提供了一种封装模组,包含一电路基板、一外壳以及多个引脚。电路基板具有多个接合区。外壳组装于电路基板,外壳具有多个穿孔。引脚连接于接合区,其中每一引脚包含焊接部、引脚本体、以及弯折部。焊接部连接于接合区之一。引脚本体垂直于电路基板,且穿过穿孔之一。弯折部连接焊接部与引脚本体,其中至少部分的弯折部具有变化的截面积。
于一或多个实施例中,弯折部在沿厚度方向相较于焊接部具有缩减的厚度。
于一或多个实施例中,弯折部在沿宽度方向相较于焊接部具有缩减的宽度。
于一或多个实施例中,弯折部具有至少一凹陷部,凹陷部位于弯折部的内侧或是外侧,且凹陷部为三角形、矩形、弧形、锯齿状或不规则形状凹槽。
本发明的外壳封装类型的封装模组与其制作方法,通过引脚架将引脚设置在电路基板对应的接合区上,而后再切除连接部与折弯引脚的设计,可以大幅缩短设置引脚所需要的时间以及人力,有效提升了封装模组的组装效率。
附图说明
为让本发明的上述和其他目的、特征、优点与实施例能更明显易懂,所附附图的详细说明如下:
图1A至图1F分别为本发明的封装模组的制作方法的一实施例不同阶段的示意图;
图2A与图2B分别为应用于本发明的封装模组的引脚的一实施例的正视图与侧视图;
图2C为图2B中的引脚的局部放大图;
图3A至图5B,其分别示出本发明的封装模组中引脚的弯折部于折弯前后的多个实施例的局部侧视图;
图6A至图7B,其分别示出本发明的封装模组中引脚的弯折部于折弯前后的多个实施例的局部正视图。
其中,附图标记说明如下:
110:电路基板
112:接合区
114:焊料
116:焊线
120:引脚架
130:引脚
132:焊接部
134:引脚本体
136:弯折部
138:凹陷部
140:外框架
150:连接部
160:电子元件
162:接点
170:外壳
172:穿孔
174:灌注口
180:保护胶
182:密封胶
D1、D2:方向
A-A、B-B:平面
具体实施方式
以下将以附图及详细说明清楚说明本发明的精神,任何所属技术领域中具有通常知识者在了解本发明的较佳实施例后,当可由本发明所教示的技术,加以改变及修饰,其并不脱离本发明的精神与范围。
参照图1A至图1F,其分别为本发明的封装模组的制作方法一实施例不同阶段的示意图。图1A为提供电路基板110,电路基板110具有多个接合区112。接合区112可以包含绝缘部分和电性连接部分,每个接合区112可具有多个不同的电性连接部分,但本发明并不以此为限。电路基板110可以为单层或多层的印刷电路板、敷铜陶瓷基板或是导线架等,本发明并不以此为限。本实施例中是以印刷电路板进行说明。
图1A中还包含将焊料114,如锡膏,设置在电路基板110的接合区112上,例如电性连接部分。焊料114可以通过如印刷的方式涂布在电路基板110上的接合区112,但本发明并不以此为限。
接着,于图1B中,将引脚架120放置在电路基板110上。引脚架120包含有多个引脚130、外框架140以及连接引脚130与外框架140的连接部150。引脚130的位置为对应于至少部分的接合区112。换言之,引脚130的一端与电路基板110的接合区112接触,并且焊料114可以位于接合区112与引脚130之间,但本发明并不以此为限。引脚130的另一端则是通过连接部150与外框架140连接。
如此一来,当要将引脚130放置在电路基板110上时,由于引脚130已经通过连接部150一体固定于外框架140上,因此,只需要一次作业即可将所有的引脚130放置到对应的接合区112上。相较于传统需要一个一个放置引脚130的工序,本发明可以一次将所有的引脚130放置到电路基板110上的预定位置,大幅缩短了组装引脚130所需要的时间。
图1B中还包含将电子元件160,例如半导体晶片,放置在电路基板110上,其中电子元件160可与部分的接合区112接合,以让焊料114连接接合区112与电子元件160,但本发明并不以此为限。引脚130可以围绕在电路基板110的边缘设置。
电路基板110与其上的电子元件160及引脚架120可以送入加热装置,例如回焊炉中,以加热焊料114,让焊料114接合引脚130与对应的接合区112,以及接合电子元件160与对应的接合区112等。如此一来,电子元件160以及引脚130便通过焊料114固定于电路基板110上。
接着参照图1C,电子元件160上可以具有多个接点162,部分的电子元件160的接点162可以通过焊线116连接至电路基板110的接合区112,或是连接至另一电子元件160的接点162等。如此一来,便可以让电子元件160通过电路基板110以及引脚130与外部沟通,但本发明并不以此为限。
接着,切除引脚架120的连接部150,让引脚架120的外框架140以及连接部150与引脚130分离,让引脚130继续保留在电路基板110上,如图1D所示。
接着,如图1E所示,将引脚130弯折,使得引脚130的一端垂直于电路基板110。为了便于弯折引脚130,可将引脚130的结构进行变截面处理,此部分将于后续的实施例中进行说明。
而后,图1F为将外壳170组装于电路基板110上,其中外壳170可以为塑胶外壳,但本发明并不以此为限。外壳170可以通过如射出成型的方式制作而成。外壳170上具有多个穿孔172,穿孔172的位置对应于引脚130,以供引脚130穿过而外露于外壳170。
图1F中还包含填充保护胶180于外壳170之中,使得保护胶180覆盖于电路基板110、电子元件160、以及部分的引脚130。保护胶180可由外壳170上的灌注口174填入外壳170内,但本发明并不以此为限。保护胶180除了用以保护电子元件160与其上的焊线116,亦可以用以电性隔离相邻的引脚130。保护胶180材料,举例而言,可以为具有流动性的胶体,如硅胶。
将外壳170组装于电路基板110上的步骤还包含有在外壳170与电路基板110之间的缝隙处涂上密封胶182,以通过密封胶182连接外壳170与电路基板110,并且隔离外界的水气。
综上所述,本发明的封装模组的制作方法可以利用引脚架将所有的引脚设置在电路基板的对应的接合区上,待引脚通过焊料固定于接合区上之后,再将引脚架的连接部切除,并弯折引脚。相较于传统需要一个一个组装引脚的方式,本方法则可以大幅提升封装模组的组装效率。
参照图2A与图2B,其分别为应用于本发明的封装模组的引脚一实施例的正视图与侧视图。引脚130包含有焊接部132、引脚本体134以及弯折部136。焊接部132可以为平行于电路基板110,且通过焊料114焊接于电路基板110上的接合区。引脚本体134则是垂直于电路基板110,用以穿过如图1F中的外壳170的穿孔172,弯折部136则是连接引脚本体134以及焊接部132。
如前所述,为了让引脚130更容易被折弯,引脚130的弯折部136可进行变截面处理,以让部分的弯折部136便于弯折。举例而言,此变截面处理包含,但不限于,将引脚130的弯折部136于其厚度方向D1或是宽度方向D2进行开槽、通孔或是缩减等,以减少局部的弯折部136的宽度和/或厚度(例如相较于焊接部132)等,让引脚130可以较为轻易地被弯折,但本发明并不以此为限。
接着参照图2A至图2C,其中图2C为图2B中的引脚130的局部放大图。更具体地说,引脚本体134可以垂直于电路基板110,焊接部132可以平行于电路基板110。弯折部136可以为平面A-A与平面B-B之间弯折的部分,但本发明并不以此为限。
前述的将弯折部136进行变截面处理的设计,可以使至少部分的弯折部136具有变化的截面积,例如,弯折部136内可以存在截面积小于平面A-A或是平面B-B位置处的截面积的区域。弯折部136的变截面设计可在制作引脚架110(见图1)时一并完成,举例而言,可以利用蚀刻或是机械加工等方式,将弯折部136沿其厚度方向D1或是宽度方向D2进行开槽、通孔或是缩减等,以减少局部的弯折部136的截面积,但本发明并不以此为限,弯折部136包含变化的截面积即可。
接着,请参照图3A至图5B,其分别示出本发明的封装模组中引脚的弯折部于折弯前后的多个实施例的局部侧视图。图3A、图4A与图5A为弯折部136被折弯前的侧视图,而图3B、图4B与图5B则是弯折部136被折弯之后的侧视图。具体而言,图3A至图5B中的弯折部136的截面积为沿着厚度方向D1变化,弯折部136上可以具有至少一个凹陷部138,凹陷部138可以位于弯折部136的内侧或是外侧,凹陷部138的深度较佳为不超过弯折部136的厚度的一半,以维持足够的机械强度,但本发明并不以此为限。
凹陷部138的形状可以为如图3A所示的三角形,如图4A所示的矩形,如图5A所示的锯齿状,或者在其他的实施例变化中,凹陷部138的形状可以为弧形或是其他的规则或不规则形状的凹槽。通过凹陷部138的设置,可以减少弯折部136于折弯时的应力,让弯折部136更容易被弯折。
请参照图6A至图7B,其分别示出本发明的封装模组中引脚的弯折部于折弯前后的多个实施例的局部正视图。图6A与图7A为弯折部136被折弯前的正视图,而图6B与图7B则是弯折部136被折弯之后的正视图。具体而言,图6A至图7B中的弯折部136的截面积为沿着宽度方向D2变化,弯折部136上可以具有至少一个凹陷部138,凹陷部138可以位于弯折部136的左右两侧,凹陷部138的宽度总和较佳为不超过弯折部136的宽度的一半,以维持足够的机械强度,但本发明并不以此为限。
凹陷部138的形状可以为如图6A所示的矩形,如图7A所示的弧状,或者在其他的实施例变化中,凹陷部138的形状可以为三角形、锯齿状或是其他的规则或不规则形状。
在部分的实施例中,弯折部136的截面积变化可不限于只沿厚度方向D1或是沿宽度方向D2作变化,而是可以同时沿厚度方向D1与宽度方向D2变化,本技术领域人员更可以按照不同的设计需求变更弯折部136中的凹陷部138的位置、数量与形状,不应以前述实施例为限,变截面设计亦可以通过设置通孔、缩减等方式实现,本发明并不以此为限。
本发明提出了一种外壳封装类型的封装模组与其制作方法,通过引脚架将引脚设置在电路基板对应的接合区上,而后再切除连接部并折弯引脚,可以大幅缩短设置引脚所需要的时间以及人力,有效提升了封装模组的组装效率。
虽然本发明已以一较佳实施例揭露如上,然其并非用以限定本发明,任何本领域技术人员,在不脱离本发明的精神和范围内,当可作各种的更动与润饰,因此本发明的保护范围当视后附的申请专利范围所界定者为准。
Claims (13)
1.一种封装模组的制作方法,包含:
放置具有多个引脚的一引脚架于一电路基板上;
接合所述多个引脚与该电路基板上所对应的多个接合区,使所述多个引脚连接于所述多个接合区;
切除该引脚架的一连接部;以及
弯折所述多个引脚,使所述多个引脚垂直于该电路基板。
2.如权利要求1所述的封装模组的制作方法,其特征在于,还包含:
组装一外壳于该电路基板,其中该外壳具有多个穿孔,以供所述多个弯折的引脚穿过而外露于该外壳。
3.如权利要求2所述的封装模组的制作方法,其特征在于,还包含:
填充一保护胶于该外壳内,使该保护胶覆盖该电路基板。
4.如权利要求1所述的封装模组的制作方法,其特征在于,还包含:
设置一焊料于该电路基板的所述多个接合区上;以及
加热该焊料。
5.如权利要求1所述的封装模组的制作方法,其特征在于,还包含:
设置多个电子元件于该电路基板;以及
打线接合部分的所述多个电子元件的接点至部分的所述多个接合区。
6.如权利要求1所述的封装模组的制作方法,其特征在于,还包含:
将所述多个引脚的弯折部进行变截面处理。
7.如权利要求6所述的封装模组的制作方法,其特征在于,该变截面积处理包含:
将所述多个引脚的弯折部于其厚度方向或宽度方向进行开槽、通孔或缩减。
8.一种使用如权利要求1-7项任一项的制作方法所制造的封装模组。
9.一种封装模组,包含:
一电路基板,具有多个接合区;
一外壳,组装于该电路基板,该外壳具有多个穿孔;以及
多个引脚,连接于所述多个接合区,其中每一所述多个引脚包含:
一焊接部,连接所述多个接合区之一;
一引脚本体,垂直于该电路基板,且穿过所述多个穿孔之一;以及
一弯折部,连接该焊接部与该引脚本体,其中至少部分的该弯折部具有变化的截面积。
10.如权利要求9所述的封装模组,其特征在于,该弯折部在沿厚度方向相较于该焊接部具有缩减的厚度。
11.如权利要求9或10所述的封装模组,其特征在于,该弯折部在沿宽度方向相较于该焊接部具有缩减的宽度。
12.如权利要求9所述的封装模组,其特征在于,该弯折部具有至少一凹陷部。
13.如权利要求12所述的封装模组,其特征在于,至少一该凹陷部位于该弯折部的内侧或是外侧,且至少一该凹陷部为三角形、矩形、弧形、锯齿状或不规则形状凹槽。
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108990309A (zh) * | 2017-05-31 | 2018-12-11 | 罗伯特·博世有限公司 | 用于在电路板上装配电子构件的连接装置和相应的方法 |
CN109994447A (zh) * | 2017-12-22 | 2019-07-09 | 三菱电机株式会社 | 半导体模块 |
CN110176451A (zh) * | 2019-05-13 | 2019-08-27 | 珠海格力电器股份有限公司 | 功率模块及其封装方法 |
CN110752197A (zh) * | 2019-09-30 | 2020-02-04 | 华为技术有限公司 | 引线框架、封装集成电路板、电源芯片及电路板的封装方法 |
CN115955802A (zh) * | 2022-12-26 | 2023-04-11 | 深圳市振华微电子有限公司 | 一种一体化多层全密封外壳 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108109977B (zh) * | 2018-02-12 | 2020-04-21 | 王艺蒲 | 一种用超声波铜线制造的集成电路芯片封装装置 |
US11342275B2 (en) * | 2020-10-22 | 2022-05-24 | Nxp Usa, Inc. | Leadless power amplifier packages including topside terminations and methods for the fabrication thereof |
US11984429B2 (en) * | 2021-09-30 | 2024-05-14 | Nxp Usa, Inc. | Leadless power amplifier packages including topside termination interposer arrangements and methods for the fabrication thereof |
US20240071892A1 (en) * | 2022-08-31 | 2024-02-29 | Texas Instruments Incorporated | Molded package with press-fit conductive pins |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4394530A (en) * | 1977-09-19 | 1983-07-19 | Kaufman Lance R | Power switching device having improved heat dissipation means |
US20020008312A1 (en) * | 2000-07-21 | 2002-01-24 | Yasushi Sasaki | Semiconductor device |
CN1879268A (zh) * | 2003-11-12 | 2006-12-13 | 浜松光子学株式会社 | 高频信号传输光学模块及其制造方法 |
US20130334672A1 (en) * | 2011-04-01 | 2013-12-19 | Fuji Electric Co., Ltd | Semiconductor device and manufacturing method thereof |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7226219B2 (en) * | 2003-11-12 | 2007-06-05 | Hamamatsu Photonics K.K. | High-frequency signal transmitting optical module and method of fabricating the same |
US7748873B2 (en) | 2004-10-07 | 2010-07-06 | Seoul Semiconductor Co., Ltd. | Side illumination lens and luminescent device using the same |
DE102007005630B4 (de) | 2007-02-05 | 2019-08-08 | Infineon Technologies Ag | Sensorchip-Modul und Verfahren zur Herstellung eines Sensorchip-Moduls |
CN201194383Y (zh) | 2008-05-09 | 2009-02-11 | 东莞市同和实业有限公司 | 一种网络滤波器 |
JP5984526B2 (ja) | 2012-06-20 | 2016-09-06 | 日本電波工業株式会社 | 表面実装型デバイス |
-
2015
- 2015-06-11 CN CN201510319405.6A patent/CN106298553A/zh active Pending
- 2015-08-17 TW TW104126650A patent/TW201643969A/zh unknown
-
2016
- 2016-03-14 US US15/068,658 patent/US9806010B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4394530A (en) * | 1977-09-19 | 1983-07-19 | Kaufman Lance R | Power switching device having improved heat dissipation means |
US20020008312A1 (en) * | 2000-07-21 | 2002-01-24 | Yasushi Sasaki | Semiconductor device |
CN1879268A (zh) * | 2003-11-12 | 2006-12-13 | 浜松光子学株式会社 | 高频信号传输光学模块及其制造方法 |
US20130334672A1 (en) * | 2011-04-01 | 2013-12-19 | Fuji Electric Co., Ltd | Semiconductor device and manufacturing method thereof |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108990309A (zh) * | 2017-05-31 | 2018-12-11 | 罗伯特·博世有限公司 | 用于在电路板上装配电子构件的连接装置和相应的方法 |
CN108990309B (zh) * | 2017-05-31 | 2021-02-12 | 罗伯特·博世有限公司 | 用于在电路板上装配电子构件的连接装置和相应的方法 |
CN109994447A (zh) * | 2017-12-22 | 2019-07-09 | 三菱电机株式会社 | 半导体模块 |
CN109994447B (zh) * | 2017-12-22 | 2023-05-12 | 三菱电机株式会社 | 半导体模块 |
CN110176451A (zh) * | 2019-05-13 | 2019-08-27 | 珠海格力电器股份有限公司 | 功率模块及其封装方法 |
CN110752197A (zh) * | 2019-09-30 | 2020-02-04 | 华为技术有限公司 | 引线框架、封装集成电路板、电源芯片及电路板的封装方法 |
WO2021063267A1 (zh) * | 2019-09-30 | 2021-04-08 | 华为技术有限公司 | 引线框架、封装集成电路板、电源芯片及电路板封装方法 |
CN110752197B (zh) * | 2019-09-30 | 2022-09-16 | 华为技术有限公司 | 引线框架、封装集成电路板、电源芯片及电路板的封装方法 |
US11887918B2 (en) | 2019-09-30 | 2024-01-30 | Huawei Technologies Co., Ltd. | Lead frame, packaged integrated circuit board, power chip, and circuit board packaging method |
CN115955802A (zh) * | 2022-12-26 | 2023-04-11 | 深圳市振华微电子有限公司 | 一种一体化多层全密封外壳 |
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