CN106252395A - A kind of thin film transistor (TFT) and preparation method thereof - Google Patents

Abstract

The invention discloses a thin film transistor and a preparation method thereof. The thin film transistor comprises: a substrate, a bottom gate, a bottom gate insulating layer, a channel, an etch stop layer, a source, a drain, a top gate insulating layer and a top gate, wherein the bottom gate is located on the substrate, The bottom gate insulating layer is on the bottom gate, the channel is on the bottom gate insulating layer, the etch stop layer is on the channel, the source and drain are on both sides of the channel, and the top gate insulating layer is on the source and the drain, the top gate is on the top gate insulating layer, and the source and drain overlap with one of the top gate or the bottom gate. Applying the thin film transistor structure provided by the present invention avoids the problem that the upper channel and the lower channel in the double gate thin film transistor in the prior art are difficult to be turned on at the same time, that is, the thin film transistor structure provided by the present invention can produce The relatively stable current/voltage improves the display performance of the AMOLED display.

Description

A kind of thin film transistor and its preparation method

technical field

The invention relates to the field of display technology, in particular to a thin film transistor and a preparation method thereof.

Background technique

With the continuous development of the field of display technology, Active Matrix Organic Light Emitting Diode (AMOLED) display screens have attracted widespread attention from all walks of life due to their advantages of high definition, high brightness, and fast response.

At present, most users regard large display and high resolution as the two commonly used criteria for selecting a display, and the electromigration ability of the display backplane directly affects the brightness and resolution of the display. Therefore, in the preparation Improving the electron mobility of the display backplane is an important aspect for users to consider.

When preparing the backplane of an AMOLED display, in order to improve the electron mobility of the backplane, there are two methods commonly used: the first one is to select a backplane material with relatively high electron mobility, for example, using low-temperature polysilicon (LTPS ) or oxide semiconductor as the backplane material, that is, using low-temperature polysilicon technology and oxide semiconductor technology to prepare thin-film transistors (TFTs) as the backplane of the AMOLED display. The second is to use a double-gate TFT as the backplane of the display to improve the electron migration capability of the backplane. Electron mobility of the plate.

The use of thin film transistors with a double-gate structure to make the backplane of the AMOLED display can indeed effectively improve the electron migration capability of the backplane. However, when a double-gate thin film transistor is working, it is usually required that the upper channel and the lower channel in the thin film transistor are turned on at the same time, otherwise a hump effect will be generated, that is, the operating current generated in the thin film transistor will be unstable, and then Affect the display performance of the display.

However, in practical applications, even if a voltage is applied to the top gate and the bottom gate at the same time, sometimes it is impossible to ensure that the upper channel and the lower channel are turned on at the same time. Therefore, using the double-gate thin film transistor structure in the prior art, sometimes It will cause the current output by the thin film transistor to be unstable, so that the display performance of the display screen is relatively low.

Contents of the invention

In view of the above problems, the present invention provides a thin film transistor, which is used to solve the problem that the upper channel and the lower channel in the double gate thin film transistor cannot are turned on at the same time, which leads to the problem that the display performance of the AMOLED display screen is relatively low.

The present invention provides a kind of thin film transistor, and this thin film transistor comprises:

A substrate, a bottom gate, a bottom gate insulating layer, a channel, an etch stop layer, a source, a drain, a top gate insulating layer, and a top gate, wherein the bottom gate is located on the substrate, and the The bottom gate insulating layer is located on the bottom gate, the channel is located on the bottom gate insulating layer, the etch stop layer is located on the channel, and the source and drain are respectively located on the bottom gate On both sides of the channel, the top gate insulating layer is located on the source and drain, the top gate is located on the top gate insulating layer, and the source and drain are connected to the One of the top gate or the bottom gate has an overlapping portion.

Preferably, the overlap between the source and the drain and the top gate and the bottom gate includes:

The top gate overlaps the source or the drain, and the bottom gate overlaps both the source and the drain.

Preferably, the overlap between the source and the drain and the top gate and the bottom gate includes:

The top gate overlaps both the source and the drain, and the bottom gate overlaps the source or the drain.

Preferably, the overlap between the source and the drain and the top gate and the bottom gate includes:

The top gate has an overlapping portion with the source and has no overlap with the drain, and the bottom gate has no overlap with the source and has an overlap with the drain.

Preferably, the overlap between the source and the drain and the top gate and the bottom gate includes:

The top gate has an overlapping portion with the drain and has no overlap with the source, and the bottom gate has no overlap with the drain and has an overlap with the source.

Correspondingly, the present invention also provides a method for preparing a thin film transistor, the method comprising:

depositing a first metal film on the substrate, and patterning the first metal film to form a bottom gate;

Depositing a bottom gate insulating film and a channel film in sequence on the bottom gate, and patterning the bottom gate insulating film and channel film respectively to form a bottom gate insulating layer and a channel;

depositing an etch stop layer on the trench, the etch stop layer protecting the trench;

Depositing a second metal film on the channel, and patterning the second metal film, forming a source electrode and a drain electrode at both ends of the channel;

depositing a top gate insulating layer on the source and drain;

A third metal film is deposited on the top gate insulating layer, and the third metal film is patterned to form a top gate, so that the source and drain are connected to the top gate or the bottom gate One of the poles has an overlapping portion.

Preferably, the patterning of the third metal film to form a top gate, so that the source and drain overlap with one of the top gate or the bottom gate, includes:

Image processing is performed on the third metal film to form a top gate, so that the top gate overlaps with the source or drain, then pattern processing is performed on the first metal film to form a bottom gate. Grid includes:

The first metal film is patterned to form a bottom gate, so that the bottom gate overlaps with both the source and the drain.

Preferably, the patterning of the third metal film to form a top gate, so that the source and drain overlap with one of the top gate or the bottom gate, includes:

Image processing is performed on the third metal film to form a top gate, so that the top gate overlaps with the source and drain, then pattern processing is performed on the first metal film to form Bottom gate consists of:

The first metal film is patterned to form a bottom gate, so that the bottom gate overlaps with the source or drain.

Preferably, the patterning of the third metal film to form a top gate, so that the source and drain overlap with one of the top gate or the bottom gate, includes:

Image processing is performed on the third metal film to form a top gate, so that the top gate overlaps with the source and does not overlap with the drain, then the first metal film is processed The patterning process to form the bottom gate includes:

The first metal film is patterned to form a bottom gate, so that the bottom gate has no overlap with the source and overlaps with the drain.

Preferably, the patterning of the third metal film to form a top gate, so that the source and drain overlap with one of the top gate or the bottom gate, includes:

patterning the third metal film to form a top gate, so that the top gate overlaps the drain and has no overlap with the source, and then performs patterning on the first metal film The patterning process to form the bottom gate includes:

The first metal film is patterned to form a bottom gate, so that the bottom gate has no overlap with the drain and overlaps with the source.

The invention provides a thin film transistor, which comprises: a substrate, a bottom gate, a bottom gate insulating layer, a channel, an etch stop layer, a source, a drain, a top gate insulating layer and a top gate, Wherein, the bottom gate is located on the substrate, the bottom gate insulating layer is located on the bottom gate, the channel is located on the bottom gate insulating layer, the etch stop layer is located on the channel, and the source and drain are respectively located on both sides of the channel. , the top gate insulating layer is located on the source and the drain, the top gate is located on the top gate insulating layer, and the source and drain overlap with one of the top gate or the bottom gate. Compared with the double-gate thin film crystal structure in the prior art, the top gate and the bottom gate overlap with the source and the drain, but in the double-gate thin film transistor structure provided by the present invention, when preparing the top When the gate and the bottom gate are used, the source and drain overlap with one of the top gate or the bottom gate. Such a thin film crystal structure can make the upper channel and the lower channel in the thin film transistor conduct simultaneously. . Therefore, the thin film transistor structure provided by this solution avoids the upper channel and the lower channel due to the overlap between the top gate and the bottom gate and the source and drain in the double gate thin film transistor in the prior art. The problem that channels are difficult to be turned on at the same time, that is, the thin film transistor structure provided by the present invention can generate relatively stable current/voltage, thereby improving the display performance of the AMOLED display.

Description of drawings

The accompanying drawings described here are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention, and do not constitute improper limitations to the present invention. In the attached picture:

Fig. 1 is a kind of thin film transistor structure in the prior art;

Fig. 2 is a kind of thin film transistor structure in the prior art;

Fig. 3 is a kind of thin film transistor structure in the prior art;

FIG. 4 is a structure of a thin film transistor provided in Embodiment 1 of the present invention;

FIG. 5 is a structure of a thin film transistor provided in Embodiment 1 of the present invention;

FIG. 6 is a thin film transistor structure provided by Embodiment 1 of the present invention;

FIG. 7 is a structure of a thin film transistor provided by Embodiment 1 of the present invention;

FIG. 8 is a structure of a thin film transistor provided by Embodiment 1 of the present invention;

9 is a schematic flowchart of a method for preparing a thin film transistor provided in Embodiment 1 of the present invention;

FIG. 10 is a structure of a thin film transistor provided by Embodiment 2 of the present invention;

FIG. 11 is a structure of a thin film transistor provided by Embodiment 2 of the present invention;

FIG. 12 is a structure of a thin film transistor provided by Embodiment 2 of the present invention;

FIG. 13 is a schematic flowchart of a method for manufacturing a thin film transistor provided in Embodiment 2 of the present invention;

FIG. 14 is a structure of a thin film transistor provided by Embodiment 3 of the present invention;

FIG. 15 is a structure of a thin film transistor provided by Embodiment 3 of the present invention;

FIG. 16 is a schematic flowchart of a method for manufacturing a thin film transistor provided in Embodiment 3 of the present invention;

FIG. 17 is a thin film transistor structure provided by Embodiment 4 of the present invention;

FIG. 18 is a structure of a thin film transistor provided by Embodiment 4 of the present invention;

FIG. 19 is a schematic flowchart of a method for manufacturing a thin film transistor provided in Embodiment 4 of the present invention;

FIG. 20 is a voltage-current curve diagram of a thin film transistor provided by the present invention;

FIG. 21 is a structure of a thin film transistor in the prior art.

detailed description

It has been recorded in the aforementioned background technology that in the prior art, double-gate thin film transistors are used to improve the electron migration capability of the AMOLED display backplane. Figure 1 shows a commonly used double-gate thin film transistor structure. The thin film The transistor specifically includes: a substrate 101, a bottom gate 102, a bottom gate insulating layer 103, a channel 104, an etch stop layer 105, a source 106, a drain 107, a top gate insulating layer 108, and a top gate 109, and The specific structure of the channel 104 is shown in Figure 2, including an upper channel 1041 and a lower channel 1042, wherein the top gate 109 overlaps with the source 106 and the drain 107, and the bottom gate 102 also overlaps with the source Both the pole 106 and the drain 107 have overlapping portions.

Because the double-gate thin film transistors in the prior art have the above-mentioned overlapping parts, after applying voltage to the top gate 109 and the bottom gate 102, it is impossible to ensure that the upper channel 1041 and the lower channel 1042 in the channel 104 are simultaneously conduction, resulting in a hump effect. As shown in Figure 3, if the lower channel 1042 in the channel 104 is turned on before the upper channel 1041, then when the source 106 is supplied with current, the route of the current in the channel 104 is "OA-AC-CD". , and then, the current is output from the drain 107; at this time, the upper channel in the channel 104 is turned on again, and the current will follow the route OB, and also output from the drain 107. Obviously, due to the upper channel 1041 and the lower channel 1041 The channels 1042 are not turned on at the same time, so the current output from the drain 107 will change, that is, a hump effect will be generated, and this hump effect will affect the display performance of the display screen.

In addition, as shown in FIG. 1 , since the top gate 109 overlaps with the source 106 and the drain 107 , and there is only a relatively thin top gate insulation between the top gate 109 and the source 106 and the gate 107 Layer 108, so it is easy to generate parasitic capacitance at the overlapping portion between the top gate 109 and the source 106 and drain 107, and the generation of such parasitic capacitance will also have a negative impact on the display performance of the display screen.

In view of the above problems, the present invention provides a thin film transistor, which is used to solve the problem that the upper channel and the lower channel in the double gate thin film transistor cannot Simultaneous conduction, which leads to the relatively low display performance of the AMOLED display, the structure of the thin film transistor specifically includes: a substrate, a bottom gate, a bottom gate insulating layer, a channel, an etch stop layer, a source, a drain electrode, a top gate insulating layer and a top gate, wherein the bottom gate is located on the substrate, the bottom gate insulating layer is located on the bottom gate, and the channel is located on the bottom gate On the insulating layer, the etching stopper layer is located on the channel, the source and the drain are respectively located on both sides of the channel, the top gate insulating layer is located on the source and the drain, The top gate is located on the top gate insulating layer, and the source and drain overlap with one of the top gate or the bottom gate.

Correspondingly, the present invention also provides a method for preparing a thin film transistor, which specifically includes:

Depositing a first metal film on the substrate, and patterning the first metal film to form a bottom gate; depositing a bottom gate insulating film and a channel film on the bottom gate in sequence, and separately patterning the bottom gate Patterning the bottom gate insulating film and the channel film to form a bottom gate insulating layer and a channel; depositing an etching stopper layer on the channel, and the etching stopper layer is used to protect the channel; Depositing a second metal film on the channel, and patterning the second metal film, forming a source electrode and a drain electrode on both ends of the channel; on the source electrode and the drain electrode Depositing a top gate insulating layer; depositing a third metal film on the top gate insulating layer, and patterning the third metal film to form a top gate, so that the source and drain are connected to the One of the top gate or the bottom gate has an overlapping portion.

In order to make the purpose of the present invention, technical solutions and advantages clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with specific embodiments 1, 2, 3 and 4 of the present invention and corresponding accompanying drawings, and embodiment 1, The structures of the thin film transistors provided in 2, 3 and 4 are based on the same inventive concept, that is, by changing the structure of the top gate and/or bottom gate, the upper channel and the lower channel are simultaneously turned on, avoiding the hump effect generation.

Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The technical solutions provided by various embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Example 1

The embodiment of the present invention provides a thin film transistor structure, which is used to solve the problem that the upper channel and the lower channel in the double gate thin film transistor cannot be simultaneously conduction, which leads to the problem that the display performance of the AMOLED display is relatively low. The thin film transistor structure provided by the present invention is shown in Figure 4 and Figure 5, and the thin film transistor specifically includes:

A substrate, a bottom gate, a bottom gate insulating layer, a channel, an etch stop layer, a source, a drain, a top gate insulating layer, and a top gate, wherein the bottom gate is located on the substrate, and the The bottom gate insulating layer is located on the bottom gate, the channel is located on the bottom gate insulating layer, the etch stop layer is located on the channel, and the source and drain are respectively located on the bottom gate On both sides of the channel, the top gate insulating layer is located on the source and the drain, the top gate is located on the top gate insulating layer, and the top gate is connected to the source Or the drain has an overlapping portion, and the bottom gate has an overlapping portion with both the source and the drain.

Specifically, the thin film transistor as shown in FIG. 4 , the thin film transistor specifically includes: a substrate 401, a bottom gate 402, a bottom gate insulating layer 403, a channel 404, an etch stop layer 405, a source 406, and a drain 407 , a top gate insulating layer 408 and a top gate 409, wherein the bottom gate 402 is located on the substrate 401, the bottom gate insulating layer 403 is located on the bottom gate 402, the channel 404 is located on the bottom gate insulating layer 403, and the The etch stop layer 405 is located on the channel 404, the source 406 and the drain 407 are respectively located on both sides 404 of the channel, the top gate insulating layer 408 is located on the source 406 and the drain 407, and the top gate 409 is located on the top gate On the insulating layer 408 , and the bottom gate 402 overlaps the source 406 and the drain 407 , and the top gate 409 overlaps the drain 407 but does not overlap the source 406 .

Specifically, the thin film transistor as shown in FIG. 5 , the thin film transistor specifically includes: a substrate 501, a bottom gate 502, a bottom gate insulating layer 503, a channel 504, an etching stopper layer 505, a source 506, and a drain 507 , a top gate insulating layer 508 and a top gate 509, wherein the bottom gate 502 is located on the substrate 501, the bottom gate insulating layer 503 is located on the bottom gate 502, the channel 504 is located on the bottom gate insulating layer 503, and the The etch stop layer 505 is located on the channel 504, the source 506 and the drain 507 are respectively located on both sides 504 of the channel, the top gate insulating layer 508 is located on the source 506 and the drain 507, and the top gate 509 is located on the top gate On the insulating layer 508 , and the bottom gate 502 overlaps with the source 506 and the drain 507 , and the top gate 509 overlaps with the source 506 but does not overlap with the drain 507 .

Compared with the double-gate thin film transistor in the prior art, the top gate and the bottom gate overlap with the source and the drain, and in the double-gate thin film transistor in FIG. 4 , the top gate 409 overlaps with the source The poles 406 have no overlapping portions.

The beneficial effects obtained by using the thin film transistor with the structure shown in Fig. 4 are specifically as follows:

As shown in Figure 6, because the top gate 409 does not overlap with the source 406, after the voltage is applied to the top gate 409, the top gate 409 generates an electric field in the top gate insulating layer 408, and the range of the generated electric field is It is determined by the structure of the top gate 409 . Specifically, as shown in FIG. 6, according to the shape of the top gate 409, the electric field generated in the top gate insulating layer 408 ranges from E to F. Therefore, the induced charges generated on the surface of the channel 404 are only distributed in the range of E to F. In the range, as the voltage of the top gate 409 increases, the upper channel EF in the channel 404 is turned on; while the bottom gate 402 overlaps with the source 406 and the drain 407, as shown in FIG. 6 In the structure of the bottom gate 402 shown, the generated electric field ranges from P to Q, that is, the range of induced charges that can be generated on the bottom gate insulating layer 403 is P to Q. As the voltage of the bottom gate 402 increases, the trench The entire lower channel in channel 404 will be turned on.

When a current is applied to the source 406, as shown in FIG. 6, the current input to the channel 404 from the edge O of the source 406 will lead to the drain 407 along the lower channel, and the upper channel will flow to the drain 407 because of the O point. There is no overlapping portion between the top gate 409 and the source 406 between point E and the current flowing from point O to the drain 407 directly along the upper channel (OF). However, the current flowing from point O can go along “OA-AB-BE-EF” (as shown in FIG. 7 ), so that it finally reaches the drain 407 .

For the sake of clarity, here is a detailed description of the current direction in the thin film transistor in Figure 4, specifically as shown in Figure 7, where the current direction along the lower channel is "OA-AB-BC-CD", and the current direction along the upper channel The direction of the current is "OA-AB-BE-EF".

It can be seen from this that since the top gate 409 and the source 406 have no overlapping portion, only when the lower channel in the channel 404 is turned on, the upper channel is turned on at the same time, that is, the upper channel and the upper channel are reached. The effect that the lower channel is turned on at the same time.

The principle of the current direction in the channel 504 of the thin film transistor in FIG. 5 is the same as that in the thin film transistor in FIG. 4 . In order to avoid repetition, the detailed description of the principle of the current direction in the thin film transistor in FIG. The specific current direction is shown in Figure 8: the current direction along the lower channel is "OA-AD-DE", and the current direction along the upper channel is "OB-BC-CD-DE".

Similarly, because the top gate 509 does not overlap with the drain 507, the upper channel will be turned on only when the lower channel in the channel 504 is turned on, that is, the upper channel and the lower channel are also reached. The effect of the channel being turned on at the same time.

In addition, the distance between the top gate and the source and drain in the double-gate thin film transistor is usually very short, so when the thin film transistor is working, the overlapping parts of the top gate and the source and drain are easy to form The parasitic capacitance, the generation of the parasitic capacitance, also affects the output of the current in the thin film transistor. However, in the thin film transistor provided by the present invention, there is no overlapping portion between the top gate and the source or drain, thus reducing the generation of a part of parasitic capacitance and improving the performance of the thin film transistor.

The invention provides a thin film transistor, which comprises: a substrate, a bottom gate, a bottom gate insulating layer, a channel, a source, a drain, a top gate insulating layer and a top gate, wherein the bottom gate Located on the substrate, the bottom gate insulating layer is located on the bottom gate, the channel is located on the bottom gate insulating layer, the source and drain are located on both sides of the channel, and the top gate insulating layer is located on the source and drain , the top gate is located on the top gate insulating layer, and the bottom gate overlaps the source and the drain, and the top gate overlaps the source or the drain. Compared with the double-gate thin film transistor structure in the prior art, the top gate and bottom gate overlap with the source and drain, but in the double-gate thin film transistor structure provided by the present invention, although the bottom gate There is overlap with the source and drain, but the top gate has no overlap with the source or drain. The beneficial effects obtained by using the thin film transistor provided by the present invention as the AMOIED display backplane are:

1. Because there is no overlap between the top gate and the source or drain, such a thin-film crystal structure conducts the upper channel while conducting the lower channel. Therefore, the thin film transistor structure provided by this solution avoids the upper channel and the lower channel due to the overlap between the top gate and the bottom gate and the source and drain in the double gate thin film transistor in the prior art. The problem that channels are difficult to be turned on at the same time, that is, the thin film transistor structure provided by the present invention can generate relatively stable current/voltage, thereby improving the display performance of the AMOLED display.

2. Because there is no overlap between the top gate and the source or drain, the generation of a part of parasitic capacitance in the thin film transistor is reduced, the performance of the thin film transistor is improved, and the display performance of the AMOLED display is improved.

Correspondingly, the present invention also provides a method for preparing a thin film transistor, which is also used to solve the problem of the upper channel and the The lower channels cannot be turned on at the same time, which leads to the problem that the display performance of the AMOLED display is relatively low. The specific flow of the method is shown in Figure 9, the method includes:

Step 901: Depositing a first metal film on a substrate, and patterning the first metal film to form a bottom gate.

In this step, deposit a layer of metal film on the substrate, where the metal can be copper, aluminum and other metals, and the deposition method can be vapor deposition, specifically thermal evaporation method, or magnetron sputtering method, etc. A metal film is deposited on the substrate.

After the first metal film is deposited on the substrate, the metal film is patterned to obtain a bottom gate structure. The patterning method here can be chemical etching or physical etching, etc. The commonly used chemical etching can use an acidic solution to chemically react with the first metal film, and usually a mask is also used, so that the first The metal film is etched to form the shape of the bottom gate; common physical etching can use plasma to bombard the first metal film, and sometimes a mask is used during the bombardment process to obtain the bottom gate.

Step 902: sequentially depositing a bottom gate insulating film and a channel film on the bottom gate, and patterning the bottom gate insulating film and channel film respectively to form a bottom gate insulating layer and a channel .

On the basis of the bottom gate obtained in step 901, a bottom gate insulating film and a channel film (active layer) are deposited, where the bottom gate insulating film can be a SiNx film, and the channel film can be α-Si, etc. . And after depositing the bottom gate insulating layer on the bottom gate, the gate insulating layer needs to be patterned, and the gate insulating layer is obtained after patterning, and then, a channel film is deposited on the gate insulating layer. Similarly, The channel film is also patterned to obtain a channel.

The graphing method adopted here may be the same as the graphing method described in step 901, or there may be other graphing methods, which are not specifically limited here.

Step 903: Deposit an etch stop layer on the channel, the etch stop layer is used to protect the channel.

In the step, an etch barrier layer is deposited on the channel, and the etch barrier layer is used to protect the channel. Specifically, since step 904 needs to prepare the source and the drain on both sides of the channel, when preparing the source and Etching is usually used in the drain process. At this time, in order to prevent the channel from being corroded by the etching solution, an etch barrier layer is deposited on the channel to prevent the channel from being damaged.

Step 904: Depositing a second metal film on the channel, and patterning the second metal film, forming a source and a drain at both ends of the channel.

In this step, a second metal film is to be deposited on the trench, where the second metal film can also be a conductive metal film such as copper or aluminum, and the patterning method here can also be the same as the patterning method mentioned in step 901 same or similar method.

Step 905: Deposit a top gate insulating layer on the source and drain.

This step is similar to step 902 and will not be repeated here. As shown in FIG. 4 or FIG. 5 , the deposited top gate insulating layer is distributed on the entire surface of the device.

Step 906: Depositing a third metal film on the top gate insulating layer, and patterning the third metal film to form a top gate, and the bottom gate and the source and drain Both have overlapping parts, and the top gate and the source or drain have overlapping parts.

This step is the same as or similar to the method of obtaining the bottom gate in step 901, so it will not be repeated here.

The beneficial effects obtained by applying the preparation method of the thin film transistor provided by the present invention are the same or similar to those obtained by applying the thin film transistor provided by the present invention above, and will not be described in detail here to avoid repetition.

Example 2

Embodiment 2 provides the second thin film transistor structure for the present invention, which is also used to solve the problem that the upper channel and the lower channel in the double gate thin film transistor used in the prior art are used as the AMOLED backplane. The channels cannot be turned on at the same time, which leads to the problem that the display performance of the AMOLED display is relatively low. The structure of the thin film transistor provided by the present invention is shown in Figure 10 and Figure 11, and the thin film transistor specifically includes:

A substrate, a bottom gate, a bottom gate insulating layer, a channel, an etch stop layer, a source, a drain, a top gate insulating layer, and a top gate, wherein the bottom gate is located on the substrate, and the The bottom gate insulating layer is located on the bottom gate, the channel is located on the bottom gate insulating layer, the etch stop layer is located on the channel, and the source and drain are respectively located on the bottom gate On both sides of the channel, the top gate insulating layer is located on the source and the drain, the top gate is located on the top gate insulating layer, and the top gate is connected to the source and the drain have overlapped parts, and the bottom gate has overlapped parts with the source or the drain.

Specifically, the thin film transistor as shown in FIG. 10 specifically includes: a substrate 1001, a bottom gate 1002, a bottom gate insulating layer 1003, a channel 1004, an etch stop layer 1005, a source 1006, and a drain 1007 , a top gate insulating layer 1008 and a top gate 1009, wherein the bottom gate 1002 is located on the substrate 1001, the bottom gate insulating layer 1003 is located on the bottom gate 1002, and the channel 1004 is located on the bottom gate insulating layer 1003. The etch stop layer 1005 is located on the channel 1004, the source 1006 and the drain 1007 are respectively located on both sides 1004 of the channel, the top gate insulating layer 1008 is located on the source 1006 and the drain 1007, and the top gate 1009 is located on the top gate on the insulating layer 1008 , and the top gate 1009 overlaps with the source 1006 and the drain 1007 , and the bottom gate 1002 has no overlap with the source 1006 .

Specifically, the thin film transistor shown in FIG. 11 specifically includes: a substrate 1101, a bottom gate 1102, a bottom gate insulating layer 1103, a channel 1104, an etch stop layer 1105, a source 1106, and a drain 1107 , a top gate insulating layer 1108 and a top gate 1109, wherein the bottom gate 1102 is located on the substrate 1101, the bottom gate insulating layer 1103 is located on the bottom gate 1102, and the channel 1104 is located on the bottom gate insulating layer 1103. The etch stop layer 1105 is located on the channel 1104, the source 1106 and the drain 1107 are respectively located on both sides 1104 of the channel, the top gate insulating layer 1108 is located on the source 1106 and the drain 1107, and the top gate 1109 is located on the top gate On the insulating layer 1108 , and the top gate 1109 overlaps the source 1106 and the drain 1107 , and the bottom gate 1102 overlaps the source 1106 but does not overlap the drain 1107 .

Compared with the double-gate thin film transistor in the prior art, the top gate and the bottom gate overlap with the source and the drain, and in the double-gate thin film transistor in FIG. 10 , the bottom gate 1002 overlaps with the source The electrode 1006 has no overlapping portion, and compared with the double-gate thin film transistor in the prior art, in the double-gate thin film transistor in FIG. 11 , the bottom gate 1102 and the drain 1107 have no overlapping portion.

The beneficial effect obtained by using the thin film transistor with the structure of Figure 10 and Figure 11 is similar to the beneficial effect obtained by using the thin film transistor with the structure of Figure 4 and Figure 5 in the embodiment, and the thin film transistor in Figure 4 and Figure 5 only conducts in the lower channel Only when the upper channel is turned on, can the upper channel be turned on, while the thin film transistors in FIG. 10 and FIG. 11 can turn on the lower channel only when the upper channel is turned on.

For the sake of clarity, the current direction in the thin film transistor in Figure 10 will be described, specifically as shown in Figure 12, where the current direction along the lower channel is "OA-AB-BC-CD", and the current direction along the upper channel is "OA-AB-BC-CD". The current direction is "OA-AE". According to the principle of the direction of the current in the thin film transistor in FIG. 10 , it is easy to know the direction of the current in the thin film transistor in FIG. 11 , which will not be described in detail here.

The invention provides a thin film transistor, which comprises: a substrate, a bottom gate, a bottom gate insulating layer, a channel, a source, a drain, a top gate insulating layer and a top gate, wherein the bottom gate Located on the substrate, the bottom gate insulating layer is located on the bottom gate, the channel is located on the bottom gate insulating layer, the source and drain are located on both sides of the channel, and the top gate insulating layer is located on the source and drain , the top gate is located on the top gate insulating layer; and the top gate overlaps both the source and the drain, and the bottom gate overlaps the source or the drain. Compared with the double-gate thin film crystal structure in the prior art, the top gate and bottom gate overlap with the source and drain, but in the double-gate thin film transistor structure provided by the present invention, although the top gate There are overlaps between the source and the drain, but there is no overlap between the bottom gate and the source or the drain. In this way, a voltage must be applied to the top gate to make the upper channel in the thin film transistor conduct, so that the lower channel can be turned on. The channel is turned on, that is, the upper channel and the lower channel in the thin film transistor are turned on at the same time. Therefore, the thin film transistor structure provided by this solution avoids the problem that the upper channel and the lower channel are difficult to conduct simultaneously in the double-gate thin film transistor in the prior art because the bottom gate and the bottom gate are all closed. That is, a relatively stable current/voltage is generated in the thin film transistor, thereby improving the display performance of the AMOLED display screen.

Correspondingly, the present invention also provides a method for preparing a thin film transistor, which is also used to solve the problem of the upper channel and the The lower channels cannot be turned on at the same time, which leads to the problem that the display performance of the AMOLED display is relatively low. The specific flow of the method is shown in Figure 13, the method includes:

Step 1301: depositing a first metal film on the substrate, and patterning the first metal film to form a bottom gate.

Step 1302: sequentially depositing a bottom gate insulating film and a channel film on the bottom gate, and patterning the bottom gate insulating film and channel film respectively to form a bottom gate insulating layer and a channel .

Step 1303: Deposit an etch barrier layer on the channel, the etch barrier layer is used to protect the channel.

Step 1304: Deposit a second metal film on the channel, and perform patterning on the second metal film, and form a source and a drain at both ends of the channel.

Step 1305: Deposit a top gate insulating layer on the source and drain.

Step 1306: Depositing a third metal film on the top gate insulating layer, and patterning the third metal film to form a top gate, and the top gate is connected to the source and drain Both have overlapping parts, and the bottom gate and the source or drain have overlapping parts.

The preparation method of the thin film crystal provided in the embodiment of the present invention is the same as the preparation method of the thin film crystal provided in Embodiment 1, and will not be repeated here. Moreover, the beneficial effects obtained by applying the thin film transistor manufacturing method provided by the present invention are the same as or similar to the aforementioned beneficial effects obtained by applying the thin film transistor provided by the present invention, and will not be described in detail here to avoid repetition.

Example 3

Embodiment 3 provides the third thin film transistor structure for the present invention, which is also used to solve the problem that the upper channel and the lower channel in the double gate thin film transistor used in the prior art are used as the AMOLED backplane. The channels cannot be turned on at the same time, which leads to the problem that the display performance of the AMOLED display is relatively low. The structure of the thin film transistor provided by the present invention is shown in Figure 14, and the thin film transistor specifically includes:

A substrate, a bottom gate, a bottom gate insulating layer, a channel, an etch stop layer, a source, a drain, a top gate insulating layer, and a top gate, wherein the bottom gate is located on the substrate, and the The bottom gate insulating layer is located on the bottom gate, the channel is located on the bottom gate insulating layer, the etch stop layer is located on the channel, and the source and drain are respectively located on the bottom gate On both sides of the channel, the top gate insulating layer is located on the source and drain, the top gate is located on the top gate insulating layer; and the bottom gate is connected to the source There is no overlapping portion and an overlapping portion with the drain, and the top gate has an overlapping portion with the source and no overlapping portion with the drain.

Specifically, the thin film transistor shown in FIG. 14 specifically includes: a substrate 1401, a bottom gate 1402, a bottom gate insulating layer 1403, a channel 1404, an etch stop layer 1405, a source 1406, and a drain 1407 , a top gate insulating layer 1408 and a top gate 1409, wherein the bottom gate 1402 is located on the substrate 1401, the bottom gate insulating layer 1403 is located on the bottom gate 1402, and the channel 1404 is located on the bottom gate insulating layer 1403. The etch stop layer 1405 is located on the channel 1404, the source 1406 and the drain 1407 are respectively located on both sides 1404 of the channel, the top gate insulating layer 1408 is located on the source 1406 and the drain 1407, and the top gate 1409 is located on the top gate On the insulating layer 1408 , the bottom gate 1402 has no overlap with the source 1406 and has overlap with the drain 1407 , and the top gate 1409 has overlap with the source 1406 and no overlap with the drain 1407 .

Compared with the double-gate thin film transistor in the prior art, the top gate and the bottom gate overlap with the source and the drain, and in the double-gate thin film transistor in FIG. 14 , the bottom gate 1402 overlaps with the source The electrode 1406 has no overlapping portion and has an overlapping portion with the drain 1407 , and the top gate 1409 has an overlapping portion with the source 1406 and has no overlapping portion with the drain 1407 .

The thin film transistor provided by the embodiment of the present invention is similar to the inventive concepts of Embodiment 1 and Embodiment 2. Specifically, FIG. 15 is used to illustrate the current direction of the thin film transistor provided by the present invention. The current direction of the channel is "OA-AB-BD-DF", and the current direction along the upper channel is "OA-AC-CE-ED-DF".

It can be seen from this that in the thin film transistor provided by the present invention, when only the upper channel is turned on, the source 1406 is supplied with current, and the drain 1407 will not have current output, because there is no current loop formed in the channel at this time; the same reason , when only the lower channel is turned on, the source 1406 is supplied with current, and the drain 1407 also has no current output. Only when the upper channel and the lower channel are turned on at the same time, a closed channel can be formed At this time, when the source 1406 is supplied with current, the drain 1407 will output current, that is, the upper channel and the lower channel are turned on at the same time by using the thin film transistor provided by the embodiment of the present invention. The invention provides a thin film transistor, which comprises: a substrate, a bottom gate, a bottom gate insulating layer, a channel, an etch stop layer, a source, a drain, a top gate insulating layer and a top gate, Wherein, the bottom gate is located on the substrate, the bottom gate insulating layer is located on the bottom gate, the channel is located on the bottom gate insulating layer, the etch stop layer is located on the channel, and the source and drain are respectively located on both sides of the channel. , the top gate insulating layer is located on the source and drain, the top gate is located on the top gate insulating layer, and the top gate overlaps with the source and drain, and the bottom gate does not overlap with the source or drain Overlap. Compared with the double-gate thin-film crystal structure in the prior art, the top gate and bottom gate overlap with the source and drain, and the beneficial effect obtained by using the thin-film transistor provided by the present invention as the backplane of the AMOIED display screen yes:

1. When the upper channel is turned on and the lower channel is not turned on, no current will be generated in the drain when current is applied to the source, and when the lower channel is turned on and the upper channel is turned on, current is applied to the source There will be no current generation in the drain at the same time; only when the upper channel and the lower channel are turned on at the same time, the drain will generate current when the current is applied to the source, that is, the upper and lower channels are turned on at the same time Effect. Therefore, the thin film transistor structure provided by this solution avoids the upper channel and the lower channel due to the overlap between the top gate and the bottom gate and the source and drain in the double gate thin film transistor in the prior art. The problem that channels are difficult to be turned on at the same time, that is, the thin film transistor structure provided by the present invention can generate relatively stable current/voltage, thereby improving the display performance of the AMOLED display.

2. Because there is no overlap between the top gate and the drain, the generation of a part of parasitic capacitance in the thin film transistor is reduced, the performance of the thin film transistor is improved, and the display performance of the AMOLED display is improved.

Correspondingly, the present invention also provides a method for preparing a thin film transistor, which is also used to solve the problem of the upper channel and the The lower channels cannot be turned on at the same time, which leads to the problem that the display performance of the AMOLED display is relatively low. The specific flow of the method is shown in Figure 16, the method includes:

Step 1601: Deposit a first metal film on the substrate, and pattern the first metal film to form a bottom gate.

Step 1602: sequentially depositing a bottom gate insulating film and a channel film on the bottom gate, and patterning the bottom gate insulating film and channel film respectively to form a bottom gate insulating layer and a channel .

Step 1603: Deposit an etch barrier layer on the channel, the etch barrier layer is used to protect the channel.

Step 1604: Deposit a second metal film on the channel, and perform patterning on the second metal film, and form a source and a drain on both ends of the channel.

Step 1605: Deposit a top gate insulating layer on the source and drain.

Step 1606: Depositing a third metal film on the top gate insulating layer, and patterning the third metal film to form a top gate, and the bottom gate has no overlap with the source And there is an overlapping portion with the drain, and the top gate has an overlapping portion with the source and has no overlapping portion with the drain.

The preparation method of the thin film crystal provided in the embodiment of the present invention is the same as the preparation method of the thin film crystal provided in Embodiment 1, and will not be repeated here. Moreover, the beneficial effects obtained by applying the thin film transistor manufacturing method provided by the present invention are the same as or similar to the aforementioned beneficial effects obtained by applying the thin film transistor provided by the present invention, and will not be described in detail here to avoid repetition.

Example 4

Embodiment 4 provides the fourth thin film transistor structure for the present invention, which is also used to solve the problem that the upper channel and the lower channel in the double gate thin film transistor used in the prior art are used as the AMOLED backplane. The channels cannot be turned on at the same time, which leads to the problem that the display performance of the AMOLED display is relatively low. The structure of the thin film transistor provided by the present invention is shown in Figure 17, and the thin film transistor specifically includes:

A substrate, a bottom gate, a bottom gate insulating layer, a channel, an etch stop layer, a source, a drain, a top gate insulating layer, and a top gate, wherein the bottom gate is located on the substrate, and the The bottom gate insulating layer is located on the bottom gate, the channel is located on the bottom gate insulating layer, the etch stop layer is located on the channel, and the source and drain are respectively located on the bottom gate On both sides of the channel, the top gate insulating layer is located on the source and drain, the top gate is located on the top gate insulating layer, and the bottom gate is connected to the drain There is no overlapping portion and overlaps with the source, and the top gate overlaps with the drain and has no overlap with the source.

Specifically, the thin film transistor as shown in FIG. 17 specifically includes: a substrate 1701, a bottom gate 1702, a bottom gate insulating layer 1703, a channel 1704, an etch stop layer 1705, a source 1706, and a drain 1707 , a top gate insulating layer 1708 and a top gate 1709, wherein the bottom gate 1702 is located on the substrate 1701, the bottom gate insulating layer 1703 is located on the bottom gate 1702, and the channel 1704 is located on the bottom gate insulating layer 1703, so The etch barrier layer 1705 is located on the channel 1704, the source 1706 and the drain 1707 are respectively located on both sides 1704 of the channel, the top gate insulating layer 1708 is located on the source 1706 and the drain 1707, and the top gate 1709 is located on On the top gate insulating layer 1708 , and the bottom gate 1702 has no overlap with the drain 1707 and overlaps with the source 1706 , and the top gate 1709 has an overlap with the drain 1707 and no overlap with the source 1706 .

Compared with the double-gate thin film transistor in the prior art, the top gate and the bottom gate overlap with the source and the drain, and in the double-gate thin film transistor in FIG. 17 , the bottom gate 1702 and the drain The electrode 1707 has no overlapping portion and overlaps the source electrode 1706 , and the top gate 1709 overlaps the drain electrode 1707 and has no overlapping portion with the source electrode 1706 .

The thin film transistor provided by the embodiment of the present invention is similar to the inventive concept of Embodiment 3. Specifically, FIG. 18 is used to illustrate the current direction of the thin film transistor provided by the embodiment of the present invention. The current direction of the channel is "OA-AB-BC-CD", and the current direction along the upper channel is "OA-AB-BE-EF".

The invention provides a thin film transistor, which comprises: a substrate, a bottom gate, a bottom gate insulating layer, a channel, a source, a drain, a top gate insulating layer and a top gate, wherein the bottom gate Located on the substrate, the bottom gate insulating layer is located on the bottom gate, the channel is located on the bottom gate insulating layer, the etch stop layer is located on the channel, the source and drain are located on both sides of the channel, and the top gate is insulated The layer is located on the source and drain, the top gate is located on the top gate insulating layer, and the bottom gate has no overlap with the drain and overlaps with the source, and the top gate has overlap with the drain and overlaps with the source There is very little overlap. The beneficial effects obtained by adopting the thin film transistor provided by the present invention as the AMOIED display screen backplane are:

1. When the upper channel is turned on and the lower channel is not turned on, no current will be generated in the drain when current is applied to the source, and when the lower channel is turned on and the upper channel is turned on, current is applied to the source There will be no current generation in the drain at the same time; only when the upper channel and the lower channel are turned on at the same time, the drain will generate current when the current is applied to the source, that is, the upper and lower channels are turned on at the same time Effect. Therefore, the thin film transistor structure provided by this solution avoids the upper channel and the lower channel due to the overlap between the top gate and the bottom gate and the source and drain in the double gate thin film transistor in the prior art. The problem that channels are difficult to be turned on at the same time, that is, the thin film transistor structure provided by the present invention can generate relatively stable current/voltage, thereby improving the display performance of the AMOLED display.

2. Because there is no overlap between the top gate and the source, the generation of a part of parasitic capacitance in the thin film transistor is reduced, the performance of the thin film transistor is improved, and the display performance of the AMOLED display is improved.

Correspondingly, the present invention also provides a method for preparing a thin film transistor, which is also used to solve the problem of the upper channel and the The lower channels cannot be turned on at the same time, which leads to the problem that the display performance of the AMOLED display is relatively low. The specific flow of the method is shown in Figure 19, the method includes:

Step 1901: Deposit a first metal film on the substrate, and pattern the first metal film to form a bottom gate.

Step 1902: sequentially depositing a bottom gate insulating film and a channel film on the bottom gate, and patterning the bottom gate insulating film and channel film respectively to form a bottom gate insulating layer and a channel .

Step 1903: Deposit an etch barrier layer on the channel, the etch barrier layer is used to protect the channel.

Step 1904: Deposit a second metal film on the channel, and pattern the second metal film, and form a source and a drain on both ends of the channel.

Step 1905: Deposit a top gate insulating layer on the source and drain.

Step 1906: Depositing a third metal film on the top gate insulating layer, and patterning the third metal film to form a top gate, and the bottom gate has no overlap with the drain And there is an overlapping portion with the source, and the top gate has an overlapping portion with the drain and has no overlapping portion with the source.

The preparation method of the thin film crystal provided in the embodiment of the present invention is the same as the preparation method of the thin film crystal provided in Embodiment 1, and will not be repeated here. Moreover, the beneficial effects obtained by applying the thin film transistor manufacturing method provided by the present invention are the same as or similar to the aforementioned beneficial effects obtained by applying the thin film transistor provided by the present invention, and will not be described in detail here to avoid repetition.

FIG. 20 is a comparison diagram of the voltage-current curve of the thin film transistor provided by the present invention and the voltage-current curve of the thin film transistor with a common structure. The abscissa in the coordinate axis corresponds to the gate voltage, and the ordinate is the current generated by the drain. And the thin film transistor of the present invention in FIG. 20 adopts any thin film transistor structure in Embodiment 1, Embodiment 2, Embodiment 3, and Embodiment 4. Specifically, Embodiment 1, Embodiment 2, and Embodiment 3 obtained through a large number of experiments The voltage-current curve of the thin film transistor in Example 4 is substantially the same as the voltage-current curve of the thin film transistor of the present invention in FIG. 20 .

The thin film transistor with a common structure here is shown in FIG. 21 , specifically comprising: a substrate 2101, a bottom gate 2102, a bottom gate insulating layer 2103, a channel 2104, an etching stopper layer 2105, a source 2106 and a drain 2107, and FIG. 21 is a structure of a thin-film transistor with a bottom gate commonly used in the prior art.

It can be seen from Figure 21 that when the gate voltage is greater than 2V, the current generated by the corresponding drain of the thin film transistor of the present invention is about 5 times the current generated by the drain of a thin film transistor with a common structure, and it can be obtained according to calculation: The electron mobility of a thin film transistor is about 46.0 cm ² /VS, and the electron mobility of a thin film transistor with a common structure is greater than 19.3 cm ² /VS, that is, the electron mobility of the thin film transistor of the present invention is about 46.0 cm 2 /VS. 2.38 times the rate.

Therefore, compared with the structure of the bottom gate thin film transistor in the prior art, the application of the thin film transistor structure provided by the present invention can improve the electron migration capability in the transistor. And it can be seen from FIG. 20 that the shape of the voltage-current curve of the thin film transistor of the present invention is roughly the same as that of the voltage-current curve of the bottom gate thin film transistor structure, which shows that the thin film transistor structure provided by the present invention does not give the thin film transistor bring about other adverse effects.

The above descriptions are only examples of the present invention, and are not intended to limit the present invention. Various modifications and variations of the present invention will occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the scope of the claims of the present invention.

Claims (10)

1. a thin film transistor (TFT), it is characterised in that including: substrate, bottom-gate, bottom-gate insulating barrier, raceway groove, etch stopper Layer, source electrode, draining, push up gate insulator and top-gated pole, wherein, described bottom-gate is positioned on described substrate, and described bottom-gate is exhausted Edge layer is positioned in described bottom-gate, and described raceway groove is positioned on described bottom-gate insulating barrier, and described etching barrier layer is positioned at described ditch On road, described source electrode and drain electrode lay respectively at the both sides of described raceway groove, and described top gate insulator is positioned at described source electrode and drain electrode On, described top-gated pole is positioned on the gate insulator of described top, and described source electrode and drain electrode with one of described top-gated pole or bottom-gate There is lap.

Method the most according to claim 1, it is characterised in that described source electrode and drain electrode have with described top-gated pole and bottom-gate Lap includes:

Described top-gated pole and described source electrode or drain electrode have lap, described bottom-gate all to have overlapping portion with described source electrode and drain electrode Point.

Method the most according to claim 1, it is characterised in that described source electrode and drain electrode have with described top-gated pole and bottom-gate Lap includes:

Described top-gated pole and described source electrode and drain electrode all have lap, described bottom-gate to have overlapping portion with described source electrode or drain electrode Point.

Method the most according to claim 1, it is characterised in that described source electrode and drain electrode have with described top-gated pole and bottom-gate Lap includes:

Described top-gated pole and described source electrode have lap and do not have lap, described bottom-gate and described source with described drain electrode Pole does not has lap and has lap with described drain electrode.

Method the most according to claim 1, it is characterised in that described source electrode and drain electrode have with described top-gated pole and bottom-gate Lap includes:

Described top-gated pole and described drain electrode have lap and do not have lap, described bottom-gate and described leakage with described source electrode Pole does not has lap and has lap with described source electrode.

6. the preparation method of a thin film transistor (TFT), it is characterised in that the method includes:

Deposit first metal film on substrate, and described first metal film is patterned process, form bottom-gate；

Described bottom-gate is sequentially depositing bottom-gate dielectric film and raceway groove film, and respectively to described bottom-gate dielectric film and raceway groove Film is patterned process, forms bottom-gate insulating barrier and raceway groove；

Deposition-etch barrier layer on described raceway groove, described etching barrier layer is used for protecting described raceway groove；

Described raceway groove deposits the second metal film, and described second metal film is patterned process, at described raceway groove Source electrode and drain electrode is formed respectively on two ends；

Deposition top gate insulator on described source electrode and drain electrode；

Described top gate insulator deposits the 3rd metal film, and described 3rd metal film is patterned process, formed Top-gated pole so that described source electrode and drain electrode have lap with one of described top-gated pole or bottom-gate.

Method the most according to claim 6, it is characterised in that described described 3rd metal film is patterned process, Form top-gated pole so that described source electrode and drain electrode have lap with one of described top-gated pole or bottom-gate, including:

Described 3rd metal film is carried out image conversion process, forms top-gated pole so that described top-gated pole and described source electrode or drain electrode There is lap, then described first metal film be patterned process, form bottom-gate and include:

Described first metal film is patterned process, forms bottom-gate so that described bottom-gate and described source electrode and drain electrode All there is lap.

Method the most according to claim 6, it is characterised in that described described 3rd metal film is patterned process, Form top-gated pole so that described source electrode and drain electrode have lap with one of described top-gated pole or bottom-gate, including:

Described 3rd metal film is carried out image conversion process, forms top-gated pole so that described top-gated pole and described source electrode and drain electrode All there is lap, then described first metal film be patterned process, form bottom-gate and include:

Described first metal film is patterned process, forms bottom-gate so that described bottom-gate and described source electrode or drain electrode There is lap.

Method the most according to claim 6, it is characterised in that described described 3rd metal film is patterned process, Form top-gated pole so that described source electrode and drain electrode have lap with one of described top-gated pole or bottom-gate, including:

Described 3rd metal film is carried out image conversion process, forms top-gated pole so that described top-gated pole has overlapping with described source electrode Partly and there is no lap with described drain electrode, then described first metal film be patterned process, form bottom-gate and include:

Described first metal film is patterned process, forms bottom-gate so that described bottom-gate does not weigh with described source electrode Folded partly and have lap with described drain electrode.

Method the most according to claim 6, it is characterised in that described described 3rd metal film is patterned process, Form top-gated pole so that described source electrode and drain electrode have lap with one of described top-gated pole or bottom-gate, including:

Described 3rd metal film is patterned process, forms top-gated pole so that described top-gated pole has overlapping with described drain electrode Partly and there is no lap with described source electrode, then described first metal film be patterned process, form bottom-gate and include:

Described first metal film is patterned process, forms bottom-gate so that described bottom-gate does not weigh with described drain electrode Folded partly and have lap with described source electrode.