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CN106206409B - 堆叠电子装置及其制造方法 - Google Patents

堆叠电子装置及其制造方法 Download PDF

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CN106206409B
CN106206409B CN201510230562.XA CN201510230562A CN106206409B CN 106206409 B CN106206409 B CN 106206409B CN 201510230562 A CN201510230562 A CN 201510230562A CN 106206409 B CN106206409 B CN 106206409B
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substrate
electronic device
layer
stacking
insulating layer
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CN106206409A (zh
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焦佑钧
詹东义
林晨曦
何家骅
詹孟璋
周信宏
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Winbond Electronics Corp
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Winbond Electronics Corp
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Priority to CN201510230562.XA priority Critical patent/CN106206409B/zh
Priority to US15/057,973 priority patent/US10483235B2/en
Priority to JP2016093767A priority patent/JP6263573B2/ja
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Abstract

本发明提供了一种堆叠电子装置及其制造方法，其中，堆叠电子装置的制造方法包括：进行一第一三维打印，以在一第一基底上形成一第一绝缘层以及多个第一重布线层；进行一第二三维打印，以于第一绝缘层上形成一第二基底以及电连接至第一重布线层的多个基底通孔电极；进行一第三三维打印，以于第二基底上形成一第二绝缘层以及电连接至基底通孔电极的多个第二重布线层；将一第三基底的多个接点接合至第二重布线层，使第三基底装设于第二绝缘层上。本发明也提供以上述方法制造的堆叠电子装置。本发明可以缩短基底通孔电极的制造时间，还可有效简化制造堆叠电子装置的工艺步骤及降低制造成本。

Description

堆叠电子装置及其制造方法
技术领域
本发明关于一种半导体技术，且特别是关于一种利用三维打印(three-dimensional printing)技术制造堆叠电子装置的方法。
背景技术
由于半导体技术的向上发展，因此集成电路的集成度(integration)或是电子元件(例如，电晶体、二极管、电阻、电容等等)的密度得以不断提升。为了提升集成电路的集成度，目前已开始发展出三维集成电路(3DIC)。一般来说，三维集成电路可通过基底通孔电极(through substrate via,TSV)作为电连接路径，以实现晶圆或芯片堆叠结构，进而达到提升集成度的目的。
在三维集成电路工艺中，芯片与基底(例如，芯片、晶圆或印刷电路板)或晶圆与基底彼此接合，且在每一芯片/晶圆与基底上的接点之间形成电连接。再者，一般的基底通孔电极的制造是以干蚀刻或激光方式在基底(例如，晶圆或芯片)内形成钻孔(via hole)并以导电材料填入钻孔内。接着，将基底与其他晶圆/芯片以及承载基底进行堆叠并以化学机械研磨(CMP)进行基底薄化工艺，使上述钻孔变成通孔(through hole)并露出填入的导电材料而形成基底通孔电极。最后将承载基底移除而构成三维堆叠电子装置。相较于传统利用打线接合的电子装置而言，具有基底通孔电极的三维堆叠电子装置可缩短内部电连接路径，进而增加装置的传输速度、降低干扰及提升装置效能。
然而，如上所述，基底通孔电极的制造包括钻孔制作、钻孔充填导电材料、基底薄化以及移除承载基底等步骤，因而无法有效缩短制造时间、简化工艺步骤及降低制造成本。因此，有必要寻求一种堆叠电子装置的制造方法，其可改善上述的问题。
发明内容
本发明提供一种堆叠电子装置及其制造方法，解决了现有技术中基底通孔电极制造时间长、工艺复杂、成本高的问题。
本发明一实施例提供一种堆叠电子装置的制造方法，包括：提供一第一基底；进行一第一三维打印，以于第一基底上形成一第一绝缘层以及多个第一重布线层，其中第一重布线层嵌入于第一绝缘层内；进行一第二三维打印，以于第一绝缘层上形成一第二基底以及多个基底通孔电极，其中基底通孔电极贯穿第二基底且电连接至第一重布线层；进行一第三三维打印，以于第二基底上形成一第二绝缘层以及多个第二重布线层，其中第二重布线层嵌入于第二绝缘层内且电连接至基底通孔电极；以及将一第三基底的多个接点接合至第二重布线层，使第三基底装设于第二绝缘层上。
本发明另一实施例提供一种堆叠电子装置，包括：一第一基底；一第一绝缘层以及多个第一重布线层，设置于第一基底上，其中第一重布线层嵌入于第一绝缘层内；一第二基底以及多个基底通孔电极，设置于第一绝缘层上，其中基底通孔电极贯穿第二基底且电连接至第一重布线层；一第二绝缘层以及多个第二重布线层，设置于第二基底上，其中第二重布线层嵌入于第二绝缘层内且电连接至基底通孔电极；以及一第三基底，装设于第二绝缘层上，其中第三基底具有多个接点接合至第二重布线层。第一绝缘层、第一重布线层、第二基底、基底通孔电极、第二绝缘层及第二重布线层通过三维打印所使用的材料所构成。
本发明提供一种堆叠电子装置及其制造方法，可以缩短基底通孔电极的制造时间，还可有效简化工艺步骤及降低制造成本，同时排除上述额外步骤所引起的技术问题。
附图说明
图1A至图1D绘示出根据本发明一实施例的堆叠电子装置的制造方法剖面示意图。
图2绘示出根据本发明一实施例的堆叠电子装置的制造方法流程图。
符号说明：
10 三维打印机
10a 第一打印喷头
10b 第二打印喷头
20 第一三维打印
20’ 第二三维打印
20” 第三三维打印
100 第一基底
102 第一绝缘层
104 第一重布线层
106 第二基底
108 基底通孔电极
110 第二绝缘层
112 第二重布线层
200 堆叠电子装置
300 方法
301、303、305、307、309 步骤
具体实施方式
以下说明本发明实施例的堆叠电子装置的制造方法。然而，可轻易了解本发明所提供的实施例仅用于说明以特定方法制作及使用本发明，并非用以局限本发明的范围。
请参照图1D，其绘示出根据本发明一实施例的堆叠电子装置剖面示意图。堆叠电子装置200包括：一第一基底100、一第一绝缘层102、多个第一重布线层(redistributionlayer,RDL)104、一第二基底106、多个基底通孔电极108、一第二绝缘层110、多个第二重布线层112以及一第三基底130。在一实施例中，第一基底100可为一印刷电路板、一晶圆、一芯片或其组合。
第一绝缘层102以及第一重布线层104设置于第一基底100上，其中第一重布线层104嵌入于第一绝缘层102内且电连接至第一基底100的接点(未绘示)。第一基底100的接点可包括接垫、焊料凸块、导电柱或其组合。此处为简化附图，仅以二个单层导电结构表示第一重布线层104。然而，需注意的是第一重布线层104可为单层或多层导电结构，且第一重布线层104的数量可取决于设计需求而不局限于图1D所示。
在本实施例中，第一绝缘层102以及第一重布线层104通过三维打印所使用的材料所构成。举例来说，第一绝缘层102包括适用于三维打印技术的陶瓷材料、高分子材料、树脂材料或介电材料。再者，第一重布线层104包括适用于三维打印技术的导电金属，例如铝、铜、金或其合金或其他金属合金。
第二基底106以及基底通孔电极108设置于第一绝缘层102上，其中基底通孔电极108贯穿第二基底106且电连接至第一重布线层104。此处为简化附图，仅绘示出二个基底通孔电极108。然而，需注意的是基底通孔电极108的数量可取决于设计需求而不局限于图1D所示。
在本实施例中，第二基底106内不具有任何主动或被动元件。再者，第二基底106以及基底通孔电极108通过三维打印所使用的材料所构成。举例来说，第二基底106包括适用于三维打印技术的模塑成型(molding compound)材料、陶瓷材料、高分子材料、树脂材料或介电材料。再者，基底通孔电极108包括适用于三维打印技术的导电金属，例如钨、铝、铜、金或其合金或其他金属合金。在其他实施例中，第二基底106可包括半导体材料，例如硅或硅锗。在此情形中，堆叠电子装置200更包括一绝缘间隔层(spacer)，以电隔离第二基底106与基底通孔电极108。绝缘间隔层包括适用于三维打印技术的陶瓷材料、高分子材料、树脂材料或介电材料。
第二绝缘层110以及第二重布线层112设置于第二基底106上，其中第二重布线层112嵌入于第二绝缘层110内且电连接至基底通孔电极108。此处为简化附图，仅以二个单层导电结构表示第二重布线层112。然而，需注意的是第二重布线层112可为单层或多层导电结构，且第二重布线层112的数量可取决于设计需求而不局限于图1D所示。
在本实施例中，第二绝缘层110以及第二重布线层112通过三维打印所使用的材料所构成。举例来说，第二绝缘层110包括适用于三维打印技术的陶瓷材料、高分子材料、树脂材料或介电材料。再者，第二重布线层112包括适用于三维打印技术的导电金属，例如铝、铜、金或其合金或其他金属合金。
第三基底130装设于第二绝缘层110上。在本实施例中，第三基底130可为一晶圆、一芯片或其组合。再者，第三基底130具有多个接点120接合至第二重布线层112。接点120可包括接垫、焊料凸块、导电柱或其组合，且此处以焊料凸块作为范例。
接下来，请参照图1A至图1D及图2，其中图1A至图1D绘示出根据本发明一实施例的堆叠电子装置的制造方法剖面示意图，且图2绘示出根据本发明一实施例的堆叠电子装置的制造方法300流程图。在本实施例中，方法300开始于步骤301，提供一第一基底100，如图1A所示。在一实施例中，第一基底100可为一印刷电路板、一晶圆、一芯片或其组合。第一基底100可具有多个接点(未绘示)，例如接垫、焊料凸块、导电柱或其组合。
接着，仍请参照图1A及图2，进行步骤303，通过一三维打印机10进行一第一三维打印20，以于第一基底100上形成一第一绝缘层102以及多个第一重布线层104，其中第一重布线层104嵌入于第一绝缘层102内，且电连接至第一基底100的接点(未绘示)。在本实施例中，三维打印机10可具有多重打印喷头，以在进行第一三维打印20之后，同时形成第一绝缘层102以及第一重布线层104。举例来说，在进行第一三维打印20期间，三维打印机10沿着平行于第一基底100的方向来回移动，利用第一打印喷头10a来形成第一绝缘层102，而利用第二打印喷头10b来形成第一重布线层104。在本实施例中，第一绝缘层102包括陶瓷材料、高分子材料、树脂材料或介电材料。再者，第一重布线层104包括导电金属，例如铝、铜、金或其合金或其他金属合金。
接着，请参照图1B及图2，进行步骤305，通过三维打印机10进行相似于第一三维打印20的一第二三维打印20’，以于第一绝缘层102上形成一第二基底106以及多个基底通孔电极108，其中基底通孔电极108贯穿第二基底106且电连接至第一重布线层104。在本实施例中，在进行第二三维打印20’之后，可同时形成第二基底106以及基底通孔电极108。举例来说，在进行第二三维打印20’期间，三维打印机10利用第一打印喷头10a来形成第二基底106，而利用第二打印喷头10b来形成基底通孔电极108。在本实施例中，第二基底106包括模塑成型材料、陶瓷材料、高分子材料、树脂材料或介电材料。再者，基底通孔电极108包括导电金属，例如钨、铝、铜、金、无铅焊锡或其合金或其他金属合金。在本实施例中，可通过调整第二三维打印20’的时间，使形成的第二基底106具有所需的厚度。再者，形成的基底通孔电极108因贯穿第二基底106而露出于其表面。因此，无须再借由任何研磨工艺(例如，CMP)来调整第二基底106的厚度来形成基底通孔电极108。
在其他实施例中，第二基底106可包括适用于三维打印技术的半导体材料，例如硅或硅锗。在此情形中，三维打印机10可包括至少三个打印喷头，且第二三维打印20’还包括形成一绝缘间隔层，以电隔离第二基底106与基底通孔电极108。绝缘间隔层包括陶瓷材料、高分子材料、树脂材料或介电材料。
接着，请参照图1C及图2，进行步骤307，通过三维打印机10进行相似于第一三维打印20的一第三三维打印20”，以于第二基底106上形成一第二绝缘层110以及多个第二重布线层112，其中第二重布线层112嵌入于第二绝缘层110内且电连接至基底通孔电极108。在本实施例中，在进行第三三维打印20”之后，可同时形成第二绝缘层110以及第二重布线层112。举例来说，在进行第三三维打印20”期间，三维打印机10利用第一打印喷头10a来形成第二绝缘层110，而利用第二打印喷头10b来形成第二重布线层112。在本实施例中，第二绝缘层110可包括相同或不同于第一绝缘材料102的材料。再者，第二重布线层112可包括相同或不同于第一重布线层104的材料。
接着，请参照图1D及图2，进行步骤309，将一第三基底130的多个接点120接合至第二重布线层112，使第三基底130装设于第二绝缘层110上。在本实施例中，第三基底130可为一晶圆、一芯片或其组合。再者，接点120可包括接垫、焊料凸块、导电柱或其组合。举例来说，第三基底130为一芯片且接点120为焊料凸块。再者，通过覆晶(flip chip)技术，将接点120接合至第二重布线层112。
根据上述实施例，由于第一绝缘层102及第一重布线层104、第二基底106及基底通孔电极108以及第二绝缘层110及第二重布线层112依序通过三维打印制作而成，因此可有效缩短堆叠电子装置的制造时间。另外，利用三维打印制作基底通孔电极可排除因深宽比所引起的填洞困难度(gap-filling difficulty)，因而获得高可靠度的基底通孔电极。再者，相较于传统的基底通孔电极的制造，利用三维打印制作基底通孔电极无须额外进行钻孔制作、钻孔充填导电材料、基底薄化以及移除承载基底等步骤，因此可有效简化工艺步骤及降低制造成本，同时排除上述额外步骤所引起的技术问题。
虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何所属技术领域技术人员，在不脱离本发明的精神和范围内，当可作更动与润饰，因此本发明的保护范围当以申请专利范围所界定者为准。

Claims (24)

1.一种堆叠电子装置的制造方法，其特征在于，所述堆叠电子装置的制造方法包括：
提供一第一基底；
进行一第一三维打印，以于该第一基底上形成一第一绝缘层以及多个第一重布线层，其中所述第一重布线层嵌入于该第一绝缘层内；
进行一第二三维打印，以于该第一绝缘层上形成一第二基底以及多个基底通孔电极，其中所述基底通孔电极贯穿该第二基底且电连接至所述第一重布线层；
进行一第三三维打印，以于该第二基底上形成一第二绝缘层以及多个第二重布线层，其中所述第二重布线层嵌入于该第二绝缘层内且电连接至所述基底通孔电极；以及
将一第三基底的多个接点接合至所述第二重布线层，使该第三基底装设于该第二绝缘层上。
2.如权利要求1所述的堆叠电子装置的制造方法，其特征在于，该第一基底包括：一印刷电路板、一晶圆、一芯片或其组合。
3.如权利要求1所述的堆叠电子装置的制造方法，其特征在于，该第一绝缘层及该第二绝缘层包括介电材料。
4.如权利要求3所述的堆叠电子装置的制造方法，其特征在于，其特征在于，所述介电材料包括陶瓷材料或高分子材料。
5.如权利要求4所述的堆叠电子装置的制造方法，其特征在于，所述高分子材料包括树脂材料。
6.如权利要求1所述的堆叠电子装置的制造方法，其特征在于，所述第一重布线层及所述第二重布线层包括铝、铜、金或其合金。
7.如权利要求1所述的堆叠电子装置的制造方法，其特征在于，该第二基底包括模塑成型材料。
8.如权利要求1所述的堆叠电子装置的制造方法，其特征在于，该第二基底包括介电材料。
9.如权利要求8所述的堆叠电子装置的制造方法，其特征在于，所述介电材料包括陶瓷材料或高分子材料。
10.如权利要求9所述的堆叠电子装置的制造方法，其特征在于，所述高分子材料包括树脂材料。
11.如权利要求1所述的堆叠电子装置的制造方法，其特征在于，该第二基底包括半导体材料，且该制造方法还包括形成一绝缘间隔层，以电隔离该第二基底与所述基底通孔电极。
12.如权利要求1所述的堆叠电子装置的制造方法，其特征在于，所述基底通孔电极包括钨、铝、铜、金、无铅焊锡或其合金。
13.如权利要求1所述的堆叠电子装置的制造方法，其特征在于，用以进行该第一三维打印、该第二三维打印及该第三三维打印的一三维打印机具有至少二个打印喷头，使每一三维打印进行期间同时形成至少二种不同的材料。
14.一种堆叠电子装置，其特征在于，所述堆叠电子装置包括：
一第一基底；
一第一绝缘层以及多个第一重布线层，设置于该第一基底上，其中所述第一重布线层嵌入于该第一绝缘层内；
一第二基底以及多个基底通孔电极，设置于该第一绝缘层上，其中所述基底通孔电极贯穿该第二基底且电连接至所述第一重布线层；
一第二绝缘层以及多个第二重布线层，设置于该第二基底上，其中所述第二重布线层嵌入于该第二绝缘层内且电连接至所述基底通孔电极；以及
一第三基底，装设于该第二绝缘层上，其中该第三基底具有多个接点接合至所述第二重布线层；
其中该第一绝缘层、所述第一重布线层、该第二基底、所述基底通孔电极、该第二绝缘层及所述第二重布线层通过三维打印所使用的材料所构成。
15.如权利要求14所述的堆叠电子装置，其特征在于，该第一绝缘层及该第二绝缘层包括介电材料。
16.如权利要求15所述的堆叠电子装置，其特征在于，所述介电材料包括陶瓷材料或高分子材料。
17.如权利要求16所述的堆叠电子装置，其特征在于，所述高分子材料包括树脂材料。
18.如权利要求14所述的堆叠电子装置，其特征在于，所述第一重布线层及所述第二重布线层包括铝、铜、金、无铅焊锡或其合金。
19.如权利要求14所述的堆叠电子装置，其特征在于，该第二基底包括模塑成型材料。
20.如权利要求14所述的堆叠电子装置，其特征在于，该第二基底包括介电材料。
21.如权利要求20所述的堆叠电子装置，其特征在于，所述介电材料包括陶瓷材料或高分子材料。
22.如权利要求21所述的堆叠电子装置，其特征在于，所述高分子材料包括树脂材料。
23.如权利要求14所述的堆叠电子装置，其特征在于，该第二基底包括半导体材料，且该堆叠电子装置还包括一绝缘间隔层，以电隔离该第二基底与所述基底通孔电极。
24.如权利要求14所述的堆叠电子装置，其特征在于，所述基底通孔电极包括钨、铝、铜、金、无铅焊锡或其合金。
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