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CN106206329A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN106206329A
CN106206329A CN201510850009.6A CN201510850009A CN106206329A CN 106206329 A CN106206329 A CN 106206329A CN 201510850009 A CN201510850009 A CN 201510850009A CN 106206329 A CN106206329 A CN 106206329A
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CN
China
Prior art keywords
bonding
semiconductor chip
bonding portion
center
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510850009.6A
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English (en)
Other versions
CN106206329B (zh
Inventor
深山真哉
尾山幸史
谷口庆辅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN106206329A publication Critical patent/CN106206329A/zh
Application granted granted Critical
Publication of CN106206329B publication Critical patent/CN106206329B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
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Abstract

本发明的实施方式提供一种半导体装置，能够抑制积层的多个半导体芯片间的间隔不均。本实施方式的半导体装置包含在第1面上设有第1凸块的半导体芯片。多个第1粘接部设置在半导体芯片的第1面上。第2粘接部设置在半导体芯片的第1面上，刚性比第1粘接部低。第2粘接部被设置为，与多个第1粘接部中离半导体芯片的第1面的中心或重心最远的第1粘接部相比，离该中心或该重心更远。

Description

半导体装置
[相关申请]
本申请享有以日本专利申请2015-110524号(申请日：2015年5月29日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置。
背景技术
为了使NAND(Not AND，与非)型EEPROM(Electrically Erasable ProgrammableRead-Only Memory，电可擦可编程只读存储器)等半导体装置小型化或高功能化，当在一个封装内积层多个半导体芯片时，有时会使用TSV(Through Silicon Via，硅通孔)以高速地收发多个半导体芯片间的电信号。TSV经由贯通半导体芯片的基板的导电性通孔，将设置在半导体芯片的正面及背面的电极间电连接。
在积层这种半导体芯片且在半导体芯片间将电极彼此连接时，利用粘接剂将半导体芯片间粘接。但是，半导体芯片为了使半导体装置小型化而被薄化，因此存在产生翘曲的情况。这种半导芯片的翘曲例如在半导体芯片的角隅部分产生试图使半导体芯片间的间隔扩大的应力。在这种半导体芯片的应力大于粘接剂的粘接力的情况下，在半导体芯片的角隅部，半导体芯片会从粘接剂剥离。
发明内容
本发明的实施方式提供一种半导体装置，能够在积层的多个半导体芯片间抑制粘接剂的剥离。
本实施方式的半导体装置包含在第1面上设有第1凸块的半导体芯片。多个第1粘接部设置在半导体芯片的第1面上。第2粘接部设置在半导体芯片的第1面上，刚性比第1粘接部低。第2粘接部被设置为，与多个第1粘接部中离半导体芯片的第1面的中心或重心最远的第1粘接部相比，离该中心或该重心更远。
附图说明
图1是表示第1实施方式的半导体装置1的构成的一例的剖视图。
图2是表示一个半导体芯片30的构成的一例的俯视图。
图3是表示积层的两个半导体芯片30的粘接状态的剖视图。
图4是表示第1实施方式的半导体装置1的制造方法的一例的剖视图。
图5是继图4之后，表示半导体装置1的制造方法的剖视图。
图6是继图5之后，表示半导体装置1的制造方法的剖视图。
图7是表示第2实施方式的半导体芯片30的构成的一例的俯视图。
图8(A)及(B)是表示积层步骤中的半导体芯片30的情况的概略剖视图。
具体实施方式
下面，参照附图对本发明的实施方式进行说明。本实施方式并非限定本发明。在下面的实施方式中，第1基板及第2基板的上下方向表示使供设置半导体芯片的面朝上时的相对方向，有时与依循重力加速度的上下方向不同。
(第1实施方式)
图1是表示第1实施方式的半导体装置1的构成的一例的剖视图。半导体装置1例如为具有积层了多层的NAND型EEPROM等半导体存储芯片的半导体装置。
半导体装置1包含第1基板10、第2基板20、半导体芯片30、密封树脂40、电极垫50、焊锡球60、IF(Interface，接口)芯片70、内部连接端子80、外部连接端子90、配线层95、第1粘接部101及第2粘接部102。
多个半导体芯片30积层在第1基板10与第2基板20之间。第1基板10使用例如金属等高导热材料。第2基板20使用例如树脂等绝缘性材料。半导体芯片30例如为搭载NAND型EEPROM的存储芯片。
半导体芯片30包含半导体基板SUB、贯通孔31、第1凸块(微凸块)32及电极33。半导体基板SUB例如为硅基板等。贯通孔(TSV)31被设置为将半导体基板SUB从其第1面F1贯通至第2面F2，而将电极33与第1凸块32之间电连接。半导体基板SUB的第2面F2是与半导体基板SUB的第1面F1为相反侧的面。第1凸块32是以与贯通孔31电连接的方式设置在半导体基板SUB的第1面F1侧。电极33是以与贯通孔31电连接的方式设置在半导体基板SUB的第2面F2侧。在贯通孔31与第1凸块32之间，设置阻挡金属等金属层。在贯通孔31与电极33之间，设置具有金属层及绝缘层的多层配线。根据需要，设置与贯通孔31及电极33电连接的半导体元件。贯通孔31、第1凸块32及电极33使用例如金属等导电性材料。
第1粘接部101及第2粘接部102设置在积层的多个半导体芯片30间，将相邻的半导体芯片30粘接。第1及第2粘接部101、102使用例如像聚酰亚胺等那样具有粘附性的绝缘性材料。第1及第2粘接部101、102的详细情况将在下文叙述。
IF芯片(接口芯片)70设置在离第2基板20最近的半导体芯片30与第2基板20之间。IF芯片70为了在积层的多个半导体芯片30与外部设备(未图示)之间进行数据通信，而与该多个半导体芯片30进行倒装芯片连接(FC(Flip Chip，倒装芯片)连接)。
配线层95是在绝缘膜上具有配线(再配线)的层，经由电极垫50及焊锡球60将半导体芯片30或IF芯片70的电极电连接于内部连接端子80。
内部连接端子80经由设置在第2基板20上的配线(未图示)电连接于外部连接端子90。在半导体装置1是LGA(Land Grid Array，焊盘网格阵列)封装的情况下，外部连接端子90作为金属焊盘而设置。在半导体装置1是BGA(Ball Grid Array，球状网格阵列)封装的情况下，外部连接端子90作为具有焊锡球、锡镀层、铜镀层等的突起端子而设置。外部连接端子90能够与外部设备电连接。电极垫50、内部连接端子80及外部连接端子90使用例如导电性金属。
密封树脂(底部填充材)40填充在积层的半导体芯片10间、半导体芯片30与第1基板10之间以及半导体芯片30与第2基板20之间。由此，密封树脂40保护半导体封装内的半导体芯片30。
图2是表示一个半导体芯片30的构成的一例的俯视图。在图2中，表示出半导体芯片30的第1面F1。在本实施方式中，半导体芯片30的第1面F1具有大致四边形(长方形)的几何形状，具有长边S1及短边S2。如上所述，第1凸块32、第1粘接部101及第2粘接部102设置在第1面F1上。另外，第1面F1的几何形状并不限定于大致四边形，也可以是大致多边形。
第1凸块32设置在虚线所示的凸块区域Rb。第1凸块32例如在半导体芯片30的长边S1的中心部，与短边S2大致平行地排列。在凸块区域Rb的两侧，例如设有存储单元阵列(未图示)，凸块区域Rb内的第1凸块32能够作为存储单元阵列的数据通信中的I/O(Input/Output，输入/输出)端子、电源端子或者接地端子来发挥功能。
多个第1粘接部101设置在凸块区域Rb的周边。在本实施方式中，第1粘接部101分别以在第1面F1上具有大致圆形的平面形状的方式配置在第1面F1上。第1粘接部101在第1面F1上的平面形状的面积(第1面积)设为S101。如上所述，第1粘接部101使用例如聚酰亚胺等具有粘附性的绝缘性材料。
多个第2粘接部102设置在半导体芯片30的第1面F1的四个角隅区域Rc。角隅区域Rc处于第1面F1的几何形状的角部。例如，在第1面F1的几何形状为大致四边形的情况下，角隅区域Rc是该四边形的四个角部的区域。在本实施方式中，第2粘接部102分别以在第1面F1上具有大致圆形的平面形状的方式配置在第1面F1上。第2粘接部102在第1面F1上的平面形状的面积(第2面积)设为S102。如上所述，第2粘接部102使用例如聚酰亚胺等粘附性的绝缘性材料。下面，S101、S102也可以分别称为第1粘接部101及第2粘接部102的粘接面积。另外，在图2中，设置在各角隅区域Rc的第2粘接部102的个数为九个，但并不限定于此。但是，如果考虑第2粘接部102的强度，那么第2粘接部102的个数优选三个以上。
这里，第2粘接部102的粘接面积S102小于第1粘接部101的粘接面积S101。而且，第2粘接部102配置在半导体芯片30的角隅区域Rc，比第1粘接部101更远离凸块区域Rb。也就是说，第2粘接部102被设置为，与第1粘接部101相比，离第1面F1的几何中心(在假设半导体芯片30的密度一定的情况下的重心)更远。相反地，第1粘接部101被设置为，比第2粘接部102更靠近第1面F1的几何中心。
例如，如图2所示，将与长边S1平行且通过半导体芯片30的几何中心的轴设为X轴，将与短边S2平行且通过半导体芯片30的几何中心的轴设为Y轴。将由X轴及Y轴划分形成的第1面F1的四个象限分别设为第1象限Q1～Q4。在该情况下，在第1象限Q1，第2粘接部102a_1比第1象限Q1中的任一个第1粘接部101均更远离第1面F1的几何中心。换句话说，第2粘接部102a_1设置在与第1粘接部101中离第1面F1的几何中心最远的第1粘接部101a_1或101b_1相比进一步远离该几何中心的位置。在第2至第4象限Q2～Q4中，可以说情况也与所述第1象限Q1相同。也就是说，第2粘接部102a_2～102a_4分别设置在与第1粘接部101中离第1面F1的几何中心最远的第1粘接部101a_2～101a_4或101b_2～101b_4相比进一步远离该几何中心的位置。
进而，在第1象限Q1，将如下直线设为直线(第1直线)L1，该直线连结位于第1面F1的短边S2侧且离第1面F1的几何中心最远的第1粘接部101a_1与位于第1面F1的长边S1侧且离第1面F1的几何中心最远的第1粘接部101b_1。在第2象限Q2，将如下直线设为直线L2，该直线连结位于第1面F1的短边S2侧且离第1面F1的几何中心最远的第1粘接部101a_2与位于第1面F1的长边S1侧且离第1面F1的几何中心最远的第1粘接部101b_2。在第3象限Q3，将如下直线设为直线L3，该直线连结位于第1面F1的短边S2侧且离第1面F1的几何中心最远的第1粘接部101a_3与位于第1面F1的长边S1侧且离第1面F1的几何中心最远的第1粘接部101b_3。在第4象限Q4，将如下直线设为直线L4，该直线连结位于第1面F1的短边S2侧且离第1面F1的几何中心最远的第1粘接部101a_4与位于第1面F1的长边S1侧且离第1面F1的几何中心最远的第1粘接部101b_4。在该情况下，第2粘接部102设置在由直线L1～L4、短边S2及长边S1包围的第1面F1的四个区域(第1区域)。这四个第1区域也可以说是所述角隅区域Rc。
如此，在本实施方式中，粘接面积比第1粘接部101小的第2粘接部102a_1设置在角隅区域Rc，且被设置为，与多个第1粘接部101相比，离第1面F1的几何中心更远。如此设置第2粘接部102的理由将在下文进行说明。
如上所述，半导体芯片30为了使半导体装置1小型化而被薄化，存在发生翘曲的情况。这种半导芯片30的翘曲例如在半导体芯片30的角隅区域Rc产生试图使半导体芯片30间的间隔扩大的应力。如果因为这种应力使半导体芯片30从粘接部剥离，那么在角隅区域Rc，半导体芯片30间的间隔变宽。在积层的多个半导体芯片30同样地翘曲的情况下，半导体芯片30间的间隔的不均会累加。从而，在该情况下，积层后的半导体芯片30在角隅区域Rc，比起其中心部而言极端地变厚。而且，有半导体芯片30间的间隔不均成为凸块间的连接不良等的原因之虞，从而使半导体装置1的制造良率降低。
第1粘接部101及第2粘接部102使用例如像聚酰亚胺等那样具有某种程度的弹性的材料。但是，由于第1粘接部101的粘接面积比第2粘接部102的粘接面积大，所以第1粘接部101具有比第2粘接部102高的刚性。因此，第1粘接部101比第2粘接部102缺少弹性，难以伸展或者难以收缩。另一方面，由于第2粘接部102的粘接面积相对较小，所以尽管刚性比第1粘接部101低，但比第1粘接部101富有弹性，易于伸展或易于收缩。而且，由于第1粘接部101是使用与第2粘接部102同一种材料构成，所以第1粘接部101的每单位面积的粘接力与第2粘接部102的每单位面积的粘接力大体相等。因此，如果是在半导体芯片1的整个第1面F1都设置第1粘接部101，而不设置第2粘接部102的情况下，那么由于刚性高的第1粘接部101不太伸缩，所以角隅区域Rc的第1粘接部101的端部被施加相对较大的应力，易于从半导体芯片30剥离。如果半导体芯片30在角隅区域Rc从粘接部剥离，那么便无法控制半导体芯片30的角隅区域Rc的翘曲，因此积层的半导体芯片30间的间隔依然不均。
另一方面，在角隅区域Rc设有第2粘接部102的情况下，如图3所示，弹性高的第2粘接部102能够相对大幅地伸缩。因此，第2粘接部102不会从半导体芯片30剥离，而能够在半导体芯片30间伸展。图3是表示积层的两个半导体芯片30的粘接状态的剖视图。第2粘接部102试图收缩而对半导体芯片30施加应力，该应力是在与因半导体芯片30的翘曲所产生的应力相反的方向上作用。由此，第2粘接部102不会在角隅区域Rc从半导体芯片30剥离，而能够抑制在半导体芯片30的中心部及角隅区域Rc的半导体芯片30间的间隔不均。
而且，如果是在半导体芯片1的整个第1面F1都设置第2粘接部102，而不设置第1粘接部101的情况下，那么由于刚性低的第2粘接部102在半导体芯片30间易于伸缩，所以半导体芯片30间的间隔(图3的IN30)变得不稳定。例如，在下述积层步骤中，当对第1基板10及第2基板20一边加压、一边加热时，半导体芯片30间的间隔IN30变得不稳定。因此，在半导体芯片30的第1面F1的中心附近(凸块区域Rb附近)，优选设置刚性相对较高的第1粘接部101。由此，在积层步骤中，也能够使半导体芯片30间的间隔IN30稳定为特定的间隔。
如此，在第1面F1的几何中心附近配置粘接面积大的第1粘接部101，在第1面F1的角隅区域Rc配置粘接面积小的第2粘接部102，由此，既能使半导体芯片30间的间隔IN30稳定，又能抑制半导体芯片30在角隅区域Rc的剥离。结果，能够抑制积层的多个半导体芯片30间的间隔不均。
图2所示的第1面F1上的第1粘接部101与第2粘接部102之间的最小间隔G是根据粘接面积相对较大的第1粘接部101的平面形状的大小而决定。例如，第1粘接部101在第1面F1具有直径为φ1的圆形的平面形状，第2粘接部10在第1面F1具有直径为φ2(φ2<φ1)的圆形的平面形状。在该情况下，最小间隔G是根据直径φ1而决定。例如，最小间隔G设定为直径φ1以上。由此，能够抑制第1粘接部101与第2粘接部102接触。其原因在于存在如下情况：如果将最小间隔G设定为小于直径φ1，或者根据粘接面积相对较小的第2粘接部102的直径φ2来决定最小间隔G，那么第2粘接部102会过分接近第1粘接部101，而与第1粘接部101接触。
另外，在本实施方式中，第1凸块32、第1及第2粘接部101、102相对于X轴及Y轴对称地配置。但是，第1凸块32、第1及第2粘接部101、102的配置也可不必相对于X轴及Y轴对称。
而且，在本实施方式中，第1面F1的几何形状是大致四边形，但也可以是四边形以外的多边形。而且，第1面F1的几何形状的一部分也可以带有弧度。即便是在该情况下，也只要将第1粘接部101配置在第1面F1的中心附近，将第2粘接部102配置在第1面F1的角隅区域Rc(或者周边区域)即可。
而且，在本实施方式中，第1粘接部101及第2粘接部102的平面形状是圆形。但是，第1粘接部101及第2粘接部102的平面形状并不限定于此，也可以是多边形。
图4～图6是表示第1实施方式的半导体装置1的制造方法的一例的剖视图。首先，利用粘接剂(未图示)将最初的半导体芯片30粘接在第1基板10上。第1基板10例如可以是金属板。然后，将其他多个半导体芯片30依次积层在最初的半导体芯片30上。由此，如图4所示，多个半导体芯片30积层在第1基板10上。这时，某个半导体芯片30的第1凸块32与位于其下方的半导体芯片30的电极33及贯通孔31电连接。
参照图2，如上所述，在半导体芯片30的第1面F1的凸块区域Rb，预先设有第1凸块32，在凸块区域Rb以外的第1面F1的区域，预先设有第1及第2粘接部101、102。从而，通过将多个半导体芯片30积层，第1及第2粘接部101、102配置在半导体芯片30间的特定位置，而将半导体芯片30间粘接(积层步骤)。另外，第1及第2粘接部101、102只要使用例如感光性聚酰亚胺等，利用光刻技术及蚀刻技术形成在第1面F1上即可。
另外，在最上段的半导体芯片30上，在积层之前，预先形成配线层95。由此，能够获得图4所示的构造。配线层95在绝缘膜上具有配线(再配线)96，在绝缘膜上具有电极垫50。
其次，如图5所示，在配线96上搭载着IF芯片70。IF芯片70经由焊锡凸块电连接于配线96。
其次，在甲酸气体环境等还原气体环境下，使将第1凸块32及IF芯片70与配线96之间电连接的凸块熔融，然后再使其凝固(回焊步骤)。其目的在于：为了将多个半导体芯片30间、及IF芯片70与配线96之间确实地电连接，而将形成在金属表面的氧化膜等还原，而将氧化膜等去除。
其次，使用切割刀片等，在半导体芯片30周围将第1基板10切断，将包含积层的多个半导体芯片30、IF芯片70及第1基板10的积层体ST个别化。
其次，将已个别化的积层体ST搭载在第2基板20上。这时，如图6所示，积层体ST使IF芯片70及电极垫50朝向第2基板20的表面而搭载在第2基板20上。也就是说，积层体ST相对于图5所示的状态使上下方向相反(使第1基板10在半导体芯片30的上方)而搭载在第2基板20上。
第2基板20是在其表面，在内部连接端子80上具备焊锡球60，在其背面具备外部连接端子90。积层体ST的电极垫50与焊锡球60接触。
其次，对第1基板10与第2基板20，一边朝相互对向的方向加压(按压)，一边加热(回焊步骤)。由此，积层体ST的电极垫50电连接于焊锡球60，并与内部连接端子80或外部连接端子90电连接。而且，半导体芯片30的第1凸块32连接于相邻的另一个半导体芯片30的电极33。进而，在该回焊步骤中，对第1粘接部101及第2粘接部102进行回焊，将相邻的半导体芯片30间粘接。
积层体ST内的多个半导体芯片30相互间的电连接、及积层体ST与第2基板20之间的电连接也可以在同一个回焊步骤中执行。可替换地，积层体ST内的多个半导体芯片30相互间的电连接、及积层体ST与第2基板20之间的电连接也可以在不同的回焊步骤中执行。在该情况下，只要在将积层体ST搭载在第2基板20上之前，为了将积层体ST内的多个半导体芯片30相互间电连接，执行第1次回焊步骤，然后，在将积层体ST搭载在第2基板20上之后，为了将积层体ST与第2基板20之间电连接，执行第2次回焊步骤即可。
其次，向第1基板10与第2基板之间，流入液状的密封树脂40(底部填充步骤)。由此，密封树脂40填充在积层的多个半导体芯片30间、及积层体ST与第2基板20之间。
然后，使用切割刀片等，将第2基板20切断，使积层体ST个别化。由此，完成图1所示的半导体装置1。
如上所述，在本实施方式中，粘接面积比第1粘接部101小的第2粘接部102a_1设置在角隅区域Rc，且被设置为，与多个第1粘接部101相比，离第1面F1的中心或重心更远。由此，弹性高的第2粘接部102在角隅区域Rc将半导体芯片30间拉伸，从而能够抑制在半导体芯片30的中心部及角隅区域Rc的半导体芯片30间的间隔不均。
而且，在半导体芯片30的第1面F1的中心附近(凸块区域Rb附近)，设有刚性相对较高的第1粘接部101。由此，在回焊步骤中，也能够使半导体芯片30间的间隔稳定为特定的间隔。
(第2实施方式)
图7是表示第2实施方式的半导体芯片30的构成的一例的俯视图。第2实施方式的半导体芯片30在角隅区域Rc还包含第2凸块(微凸块)35。第2实施方式的其他构成可以与第1实施方式的对应构成相同。
第2凸块35与第1凸块32同样地，和贯通半导体芯片30的第1面F1与第2面F2之间的贯通孔(未图示)电连接。由此，积层的多个半导体芯片30中的第2凸块35共通地电连接。
第2凸块35配置在第1～第4象限Q1～Q4的各角隅区域Rc。第2凸块35在各角隅区域Rc内，设置在相邻的第2粘接部间。进而，第2凸块35配置在与离第1面F1的几何中心最远的第2粘接部102a_1～102a_4相比更靠近第1面F1的几何中心的位置。由此，尽管第2凸块35设置在角隅区域Rc，但是由于第2粘接部102抑制在角隅区域Rc的半导体芯片30间的剥离，所以能够在积层的半导体芯片30间维持与其他第2凸块35的电连接。
第2凸块35例如为能够与电源或地线电连接的电源端子或接地端子，向半导体芯片30内的半导体元件供给电源电位或接地电位等电位。
如果是在将电源端子及接地端子仅设置在凸块区域Rb内的情况下，那么尽管能够在相对较短的时间内对处于靠近凸块区域Rb的位置的半导体元件(例如，存储单元)施加电源电位或接地电位，但需要花费相对较长的时间才能对处于离凸块区域Rb较远的位置的半导体元件施加所述电位。
相对于此，在第2实施方式中，将电源端子及接地端子不仅设置在凸块区域Rb内，也设置在角隅区域Rc。如此，只要像第2实施方式那样，将作为电源端子或接地端子的第2凸块35设置在角隅区域Rc，电源电位或设置电位便会在较短时间内施加给处于离凸块区域Rb较远的位置的半导体元件。这关系到半导体装置1的高速动作。
而且，通过将第2凸块35设置在角隅区域Rc，在回焊步骤中，第2凸块35能够支撑半导体芯片30的角隅区域Rc。例如，图8(A)及图8(B)是表示积层步骤中的半导体芯片30的情况的概略剖视图。在图8(A)及图8(B)中，对于积层的两个半导体芯片30，一边利用加压装置200沿箭头A方向加压，一边进行积层。加压装置200包含加压部210及平台220。加压部210包含弹性体(例如，橡胶)201及保持该弹性体201的固持器202。加压部210将搭载在平台220上的多个半导体芯片30向平台220按压。这时，半导体芯片30被加热。
加压装置200的弹性体201弹性按压半导体芯片30，不仅对半导体芯片30的中心部(凸块区域Rb)加压，还对角隅区域Rc加压。从而，如图8(A)所示，如果是在未设置第2凸块35的情况下，那么在积层步骤中，角隅区域Rc相对于半导体芯片30的中心部下沉，角隅区域Rc的半导体芯片30间的间隔IN30与中心部的半导体芯片30间的间隔IN30相比变窄。
另一方面，在第2实施方式中，如图8(B)所示，在角隅区域Rc设有第2凸块35，因此在回焊步骤中，第2凸块35支撑角隅区域Rc的半导体芯片30。由此，角隅区域Rc不相对于半导体芯片30的中心部下沉，而能够使角隅区域Rc的半导体芯片30间的间隔IN30与中心部的半导体芯片30间的间隔IN30大体相等。由此，能够抑制半导体芯片30的中心部与角隅区域Rc的半导体芯片30间的间隔不均。
而且，第2实施方式与第1实施方式同样地包含第1粘接部101及第2粘接部102。因此，第2实施方式能够进一步获得与第1实施方式相同的效果。
对本发明的几个实施方式进行了说明，但这些实施方式是作为例子而提出的，并非试图限定发明的范围。这些实施方式能以其他各种方式实施，能够在不脱离发明的主旨的范围内，进行各种省略、置换、变更。这些实施方式及其变化包含在发明的范围及主旨中，同样地，也包含在权利要求书所记载的发明及其均等的范围内。
附记
一种半导体装置，包括：半导体芯片，在第1面上设有第1凸块；
多个第1粘接部，设置在所述半导体芯片的所述第1面上；及
第2粘接部，设置在所述半导体芯片的第1面上且在所述第1面上的粘接面积比所述多个第1粘接部在所述第1面上的粘接面积小，且被设置为，与所述多个第1粘接部中离所述半导体芯片的所述第1面的中心或重心最远的第1粘接部相比，离该中心或该重心更远。
附记A
根据附记所述的半导体装置，其中所述半导体芯片的所述第1面具有大致多边形的形状，且
所述第2粘接部设置在所述第1面的所述大致多边形的角隅区域。
附记B
根据附记A所述的半导体装置，其还包含设置在所述角隅区域内的第2凸块。
附记C
根据附记B所述的半导体装置，其中所述第1凸块配置在比所述角隅区域更靠近所述第1面的中心或重心的位置，且
所述第2凸块在所述角隅区域内，配置在比所述第2粘接部更靠近所述第1面的中心或重心的位置。
附记D
根据附记B所述的半导体装置，其中所述第2凸块是能够与电源或地线连接的电源端子或接地端子。
附记E
根据附记C所述的半导体装置，其中所述第2凸块是能够与电源或地线连接的电源端子或接地端子。
附记F
根据附记A所述的半导体装置，其中所述第1面上的所述第1粘接部与所述第2粘接部之间的最小间隔是根据所述第1面上的所述第1粘接部的平面形状的大小而决定。
附记G
根据附记F所述的半导体装置，其中所述最小间隔是所述第1面上的所述第1粘接部的直径以上。
[符号的说明]
1 半导体装置
10 第1基板
20 第2基板
30 半导体芯片
40 密封树脂
50 电极垫
60 焊锡球
70 IF芯片
80 内部连接端子
90 外部连接端子
95 配线层
101 第1粘接部
102 第2粘接部
31 贯通孔
32 第1凸块
33 电极

Claims (9)

1.一种半导体装置，其特征在于包括：半导体芯片，在第1面上设有第1凸块；
多个第1粘接部，设置在所述半导体芯片的所述第1面上；以及
第2粘接部，设置在所述半导体芯片的所述第1面上且刚性比所述第1粘接部低，且被设置为，与所述多个第1粘接部中离所述半导体芯片的所述第1面的中心或重心最远的第1粘接部相比，离该中心或该重心更远。
2.根据权利要求1所述的半导体装置，其特征在于：所述第2粘接部在所述第1面上的粘接面积比所述第1粘接部在所述第1面上的粘接面积小。
3.根据权利要求1或2所述的半导体装置，其特征在于：所述半导体芯片的所述第1面具有包含短边及长边的大致多边形的形状，
所述第2粘接部设置在由第1直线、所述短边及所述长边包围的所述第1面上的第1区域，
所述第1直线是如下直线：连结所述多个第1粘接部中位于所述第1面的所述短边侧且离所述第1面的几何中心最远的第1粘接部与所述多个第1粘接部中位于所述第1面的所述长边侧且离所述第1面的几何中心最远的第1粘接部。
4.根据权利要求3所述的半导体装置，其特征在于：在所述第1区域设有三个以上所述第2粘接部。
5.根据权利要求3所述的半导体装置，其特征在于还包含设置在所述第1区域内的第2凸块。
6.根据权利要求5所述的半导体装置，其特征在于：所述第1凸块配置在比所述第1区域更靠近所述第1面的几何中心的位置，且
所述第2凸块在所述第1区域内，配置在比所述第2粘接部更靠近所述第1面的几何中心的位置。
7.根据权利要求5所述的半导体装置，其特征在于：所述第2凸块是能够与电源或地线电连接的电源端子或接地端子。
8.根据权利要求1或2所述的半导体装置，其特征在于：所述第1面上的所述第1粘接部与所述第2粘接部之间的最小间隔是根据所述第1面上的所述第1粘接部的平面形状的大小而决定。
9.根据权利要求8所述的半导体装置，其特征在于：所述最小间隔是所述第1面上的所述第1粘接部的直径以上。
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