CN106158040B - Read voltage level estimation method, memory storage device and control circuit unit - Google Patents

Abstract

The present invention provides a read voltage level estimation method, a memory storage device, and a control circuit unit. The method includes: reading a first area in a rewritable non-volatile memory module according to a first read voltage level to obtain a first coding unit, wherein the first coding unit belongs to a block code; performing a first decoding procedure on the first coding unit and recording first decoding information; reading the first area according to a second read voltage level to obtain a second coding unit, wherein the second coding unit belongs to the block code; performing a second decoding procedure on the second coding unit and recording second decoding information; and estimating and obtaining a third read voltage level according to the first decoding information and the second decoding information. In this way, the management capability of the rewritable non-volatile memory module using the block code can be improved.

Description

Read voltage level estimation method, memory storage device and control circuit unit

technical field

The present invention relates to a memory management method, and in particular to a read voltage level estimation method, a memory storage device and a control circuit unit.

Background technique

Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, it is very suitable for being built in the various memory modules listed above. in portable multimedia devices.

Generally speaking, in order to ensure the correctness of the data, before writing a piece of data into the rewritable non-volatile memory module, the data will be encoded. The encoded data will be written into the rewritable non-volatile memory module. When the data is to be read, the encoded data will be read and decoded. If the data can be successfully decoded, it means that the number of erroneous bits in it is small and these erroneous bits can be corrected. However, if the data cannot be successfully decoded (ie, the decoding fails), a different read voltage may be used to re-read the data. However, in some cases, even if multiple available read voltages have been used, the read data cannot be successfully decoded, resulting in data read failure. In particular, this situation is more severe for data encoded using block codes.

Contents of the invention

The invention provides a reading voltage level estimation method, a memory storage device and a control circuit unit, which can improve the management ability of a rewritable non-volatile memory module using a block code.

An exemplary embodiment of the present invention provides a method for estimating a read voltage level, which is used in a rewritable non-volatile memory module. The method for estimating the read voltage level includes: according to the first read voltage read the first area in the rewritable non-volatile memory module to obtain a first encoding unit, wherein the first encoding unit belongs to a block code; perform the second encoding unit on the first encoding unit A decoding program and recording the first decoding information; reading the first area according to the second reading voltage level to obtain a second coding unit, wherein the second coding unit belongs to the block code; The second encoding unit executes a second decoding procedure and records second decoding information; and estimates and obtains a third read voltage level according to the first decoding information and the second decoding information.

In an exemplary embodiment of the present invention, the block code is composed of a plurality of sub-coding units, and the first bit in the sub-coding units is determined by a plurality of encoding procedures.

In an exemplary embodiment of the present invention, the encoding procedures have different encoding directions.

In an exemplary embodiment of the present invention, the first decoded information includes a first value, and the second decoded information includes a second value, wherein it is estimated according to the first decoded information and the second decoded information And the step of obtaining the third read voltage level includes: comparing the first value with the second value and determining the third read voltage level according to the comparison result.

In an exemplary embodiment of the present invention, the first value is related to a first decoding result of the first decoding procedure, and the second value is related to a second decoding result of the second decoding procedure.

In an exemplary embodiment of the present invention, the first value is positively related to the number of first decoded successful units of the first decoding program, and the second value is directly related to the second decoded unit number of the second decoding program. Number of successful units.

In an exemplary embodiment of the present invention, the method for estimating the read voltage level further includes: obtaining the number of successfully decoded units in the first row and the number of successfully decoded units in the first column according to the first decoding result; The number of successfully decoded units in the first row and the number of successfully decoded units in the first column determine the first value; obtain the number of successfully decoded units in the second row and the number of successfully decoded units in the second column according to the second decoding result; and The second value is determined according to the number of successfully decoded units in the second row and the number of successfully decoded units in the second column.

In an exemplary embodiment of the present invention, the step of estimating and obtaining the third read voltage level according to the first decoded information and the second decoded information includes: converting the first read voltage One of the level and the second read voltage level is determined as the third read voltage level.

In an exemplary embodiment of the present invention, the method for estimating the read voltage level further includes: judging whether the first decoding process fails, wherein the first decoding process is read according to the second read voltage level. A region of steps is performed after determining that the first decoding procedure has failed.

In an exemplary embodiment of the present invention, the read voltage level estimating method further includes: performing prediction related to the rewritable non-volatile memory module according to the third read voltage level. Set operation, wherein the preset operation includes at least one of the following operations: read the first area to obtain a plurality of soft bits corresponding to the third decoding unit and perform the operation of the third decoding unit according to the soft bits The decoding unit performs iterative decoding; determines wear levels of a plurality of memory cells in the first area or voltage distribution states of the memory cells; and determines a preset programming voltage corresponding to the first area.

In an exemplary embodiment of the present invention, the read voltage level estimating method further includes: reading the first region according to the third read voltage level to obtain a third coding unit; and Execute a third decoding procedure on the third encoding unit.

In an exemplary embodiment of the present invention, both the first decoding process and the second decoding process are hard bit mode decoding.

Another exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to electrically connect to the host system. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module. Wherein the memory control circuit unit is used to send a first read instruction sequence, wherein the first read instruction sequence is used to instruct to read the rewritable non-volatile memory according to a first read voltage level The first area in the module to obtain the first encoding unit, wherein the first encoding unit belongs to the block code, wherein the memory control circuit unit is also used to execute the first decoding program on the first encoding unit and record The first decoding information, wherein the memory control circuit unit is also used to send a second read command sequence, wherein the second read command sequence is used to indicate to read the first region, to obtain a second coding unit, wherein the second coding unit belongs to the block code, wherein the memory control circuit unit is also used to execute a second decoding procedure on the second coding unit and record a second decoding information, wherein the memory control circuit unit is further configured to estimate and obtain a third read voltage level according to the first decoded information and the second decoded information.

In an exemplary embodiment of the present invention, the block code is composed of a plurality of sub-coding units, and the first bit in the sub-coding units is determined by a plurality of encoding procedures.

In an exemplary embodiment of the present invention, the encoding procedures have different encoding directions.

In an exemplary embodiment of the present invention, the first decoded information includes a first value, and the second decoded information includes a second value, wherein the memory control circuit unit The operation of decoding information to estimate and obtain the third read voltage level includes: comparing the first value with the second value and determining the third read voltage level according to the comparison result.

In an exemplary embodiment of the present invention, the first value is related to a first decoding result of the first decoding procedure, and the second value is related to a second decoding result of the second decoding procedure.

In an exemplary embodiment of the present invention, the first value is positively related to the number of first decoded successful units of the first decoding program, and the second value is directly related to the second decoded unit number of the second decoding program. Number of successful units.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to obtain the number of successfully decoded cells in the first row and the number of successfully decoded cells in the first column according to the first decoding result, wherein the memory control circuit unit It is also used to determine the first value according to the number of successfully decoded units in the first row and the number of successfully decoded units in the first column, wherein the memory control circuit unit is also used to obtain the first value according to the second decoding result The number of successfully decoded units in the second row and the number of successfully decoded units in the second column, wherein the memory control circuit unit is also used to determine the second row according to the number of successfully decoded units in the second row and the number of successfully decoded units in the second column. binary value.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit estimating and obtaining the third read voltage level according to the first decoded information and the second decoded information includes: One of the first read voltage level and the second read voltage level is determined as the third read voltage level.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to determine whether the first decoding procedure fails, wherein the operation of the memory control circuit unit sending the second read command sequence is to determine Executed after the first decoding procedure fails.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to perform a preset operation related to the rewritable non-volatile memory module according to the third read voltage level, wherein The preset operation includes at least one of the following operations: instructing to read the first area to obtain a plurality of soft bits corresponding to the third decoding unit and perform the operation on the third decoding unit according to the soft bits Iterative decoding; determining the degree of wear of a plurality of memory cells in the first area or the voltage distribution state of the memory cells; and determining a preset programming voltage corresponding to the first area.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to instruct to read the first area according to the third read voltage level to obtain a third encoding unit, wherein the memory The control circuit unit is also used for executing a third decoding program on the third encoding unit.

In an exemplary embodiment of the present invention, both the first decoding process and the second decoding process are hard bit mode decoding.

Another exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module, the memory control circuit unit includes a host interface, a memory interface, an error checking and correction circuit, and a memory management circuit. The host interface is used to electrically connect to the host system. The memory interface is used to electrically connect to the rewritable non-volatile memory module. The memory management circuit is electrically connected to the host interface, the memory interface, and the error checking and correction circuit, wherein the memory management circuit is used to send a first read instruction sequence, wherein the first read The instruction sequence is used to instruct to read the first area in the rewritable non-volatile memory module according to the first read voltage level to obtain a first coding unit, wherein the first coding unit belongs to a block code, wherein the error checking and correction circuit is used to execute the first decoding program on the first coding unit, and the memory management circuit is also used to record the first decoding information, wherein the memory management circuit is also used to send A second read command sequence, wherein the second read command sequence is used to instruct to read the first region according to a second read voltage level to obtain a second encoding unit, wherein the second encoding unit Belonging to the block code, wherein the error checking and correction circuit is also used to execute a second decoding procedure on the second encoding unit, and the memory management circuit is also used to record the second decoding information, wherein the memory The management circuit is also used for estimating and obtaining a third reading voltage level according to the first decoding information and the second decoding information.

In an exemplary embodiment of the present invention, the block code is composed of a plurality of sub-coding units, and the first bit in the sub-coding units is determined by a plurality of encoding procedures.

In an exemplary embodiment of the present invention, the encoding procedures have different encoding directions.

In an exemplary embodiment of the present invention, the first decoding information includes a first value, and the second decoding information includes a second value, wherein the memory management circuit according to the first decoding information and the second The operation of decoding information to estimate and obtain the third read voltage level includes: comparing the first value with the second value and determining the third read voltage level according to the comparison result.

In an exemplary embodiment of the present invention, the first value is related to a first decoding result of the first decoding procedure, and the second value is related to a second decoding result of the second decoding procedure.

In an exemplary embodiment of the present invention, the first value is positively related to the number of first decoded successful units of the first decoding program, and the second value is directly related to the second decoded unit number of the second decoding program. Number of successful units.

In an exemplary embodiment of the present invention, the memory management circuit is further used to obtain the number of successfully decoded units in the first row and the number of successfully decoded units in the first column according to the first decoding result, wherein the memory management circuit is also used The first value is determined according to the number of successfully decoded units in the first row and the number of successfully decoded units in the first column, wherein the memory management circuit is also used to obtain the decoded value of the second row according to the second decoding result The number of successful units and the number of successfully decoded units in the second column, wherein the memory management circuit is further configured to determine the second value according to the number of successfully decoded units in the second row and the number of successfully decoded units in the second column.

In an exemplary embodiment of the present invention, the operation of the memory management circuit to estimate and obtain the third read voltage level according to the first decoding information and the second decoding information includes: One of the first read voltage level and the second read voltage level is determined as the third read voltage level.

In an exemplary embodiment of the present invention, the memory management circuit is further used to determine whether the first decoding procedure fails, wherein the operation of the memory management circuit sending the second read instruction sequence is to determine whether the Executed after the first decoding procedure fails.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to perform a preset operation related to the rewritable non-volatile memory module according to the third read voltage level, wherein the The preset operation includes at least one of the following operations: instructing to read the first area to obtain a plurality of soft bits corresponding to the third decoding unit, and the error checking and correction circuit is also used to to perform iterative decoding on the third decoding unit; determine the degree of wear of a plurality of storage units in the first area or the voltage distribution state of the storage units; and determine a preset program corresponding to the first area cation voltage.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to instruct to read the first area according to the third read voltage level to obtain a third encoding unit, wherein the error checking The AND correction circuit is also used for performing a third decoding procedure on the third encoding unit.

In an exemplary embodiment of the present invention, both the first decoding process and the second decoding process are hard bit mode decoding.

Based on the above, the read voltage level estimation method, the memory storage device and the control circuit unit provided by the embodiments of the present invention, after using different read voltage levels to read the memory and trying to decode the obtained data, Decoding information corresponding to different decoding procedures will be recorded. The decoded information can then be used as a basis for estimating an appropriate read voltage level. Thereby, the management capability of the rewritable non-volatile memory module using the block code can be improved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

FIG. 2 is a schematic diagram of a computer, an input/output device and a memory storage device according to an exemplary embodiment of the present invention;

3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

FIG. 4 is a schematic block diagram of the memory storage device shown in FIG. 1;

FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

FIG. 6 is a schematic diagram of a memory cell array according to an exemplary embodiment of the present invention;

FIG. 7 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

FIG. 8 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

FIG. 9 is a schematic diagram showing threshold voltage distributions of a plurality of memory cells according to an exemplary embodiment of the present invention;

Fig. 10 is a schematic diagram of a coding unit shown according to an exemplary embodiment of the present invention;

FIG. 11 is a schematic diagram of reading multiple soft bits according to an exemplary embodiment of the present invention;

FIG. 12 is a flowchart of a method for estimating a read voltage level according to an exemplary embodiment of the present invention.

Explanation of reference signs:

10: memory storage device;

11: host system;

12: computer;

122: microprocessor;

124: random access memory;

126: system bus;

128: data transmission interface;

13: input/output device;

21: mouse;

22: keyboard;

23: Display;

24: printer;

25: Pen drive;

26: memory card;

27: SSD;

31: digital camera;

32: SD card;

33: MMC card;

34: memory stick;

35: CF card;

36: embedded storage device;

402: connect the interface unit;

404: memory control circuit unit;

406: Rewritable non-volatile memory module;

502: memory cell array;

504: word line control circuit;

506: bit line control circuit;

508: row decoder;

510: data input/output buffer;

512: control circuit;

602: storage unit;

604: bit line;

606: character line;

608: shared source line;

612, 614: transistors;

702: memory management circuit;

704: host interface;

706: memory interface;

708: Error checking and correction circuit;

710: buffer memory;

712: power management circuit;

800(0)～800(R): Entity erasing unit;

810(0)～810(D): logic unit;

802: storage area;

806: system area;

901, 902, 911, 912, 1110, 1120: distribution;

913: overlapping area;

V _read-0 ～V _read-3 、 V ₁ ～V ₅ : read the voltage level;

1010: encoding unit;

1011～101n: sub coding unit;

b ₁₁ ~b _nm : bits;

1101～1106: voltage range;

b ₁ ~ b ₅ : soft bits;

S1201-S1206: steps.

Detailed ways

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also called a control circuit). Typically memory storage devices are used with a host system such that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram of a computer, an input/output device and a memory storage device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , the host system 11 generally includes a computer 12 and an input/output (input/output, I/O for short) device 13 . The computer 12 includes a microprocessor 122 , a random access memory (random access memory, RAM for short) 124 , a system bus 126 and a data transmission interface 128 . The input/output device 13 includes a mouse 21 , a keyboard 22 , a monitor 23 and a printer 24 as shown in FIG. 2 . It must be understood that the device shown in FIG. 2 is not limited to the input/output device 13, and the input/output device 13 may also include other devices.

In an exemplary embodiment, the memory storage device 10 is electrically connected to other components of the host system 11 through the data transmission interface 128 . Data can be written into the memory storage device 10 or read from the memory storage device 10 through the operation of the microprocessor 122 , the random access memory 124 and the input/output device 13 . For example, the memory storage device 10 may be a rewritable non-volatile memory storage device such as a flash drive 25, a memory card 26, or a solid state drive (Solid State Drive, SSD for short) 27 as shown in FIG. 2 .

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

In general, host system 11 is any system that can cooperate substantially with memory storage device 10 to store data. Although in this exemplary embodiment, the host system 11 is described as a computer system, however, in another exemplary embodiment, the host system 11 may be a system such as a digital camera, a video camera, a communication device, an audio player, or a video player. . For example, when the host system is a digital camera (video camera) 31, the rewritable non-volatile memory storage device is an SD card 32, an MMC card 33, a memory stick (memory stick) 34, a CF card 35 or An embedded storage device 36 (as shown in FIG. 3 ). The embedded storage device 36 includes an embedded multimedia card (Embedded MMC, eMMC for short). It is worth mentioning that the embedded multimedia card is directly electrically connected to the substrate of the host system.

FIG. 4 is a schematic block diagram of the memory storage device shown in FIG. 1 .

Referring to FIG. 4 , the memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be in accordance with the Parallel Advanced Technology Attachment (Parallel Advanced Technology Attachment, referred to as PATA) standard, Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, referred to as IEEE) 1394 standard, Peripheral Component Interconnect Express (PCI Express for short) standard, Universal Serial Bus (Universal Serial Bus, USB for short) standard, Secure Digital (SD for short) interface standard, Ultra High Speed Generation (Ultra HighSpeed-I (UHS-I for short) interface standard, Ultra High Speed-II (UHS-II for short) interface standard, Memory Stick (Memory Stick, MS for short) interface standard, Multi Media Card (Multi Media Card) , MMC for short) interface standard, Embedded Multimedia Card (eMMC for short) interface standard, Universal Flash Storage (UFS for short) interface standard, Compact Flash (CF for short) interface standard , Integrated Device Electronics (IDE for short) standard or other suitable standards. The connection interface unit 402 can be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 can be arranged outside a chip including the memory control circuit unit 404 .

The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in the form of hardware or firmware, and write and read data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11. Fetch and erase operations.

The rewritable non-volatile memory module 406 is electrically connected to the memory control circuit unit 404 and used for storing data written by the host system 11 . The rewritable non-volatile memory module 406 can be a single-level cell (Single Level Cell, SLC for short) NAND flash memory module (that is, a flash memory module that can store 1 bit of data in a storage unit), multiple Layer unit (Multi Level Cell, referred to as MLC) NAND flash memory module (that is, a flash memory module that can store 2 bits of data in a storage unit), triple level cell (Triple Level Cell, referred to as TLC) NAND flash memory module A memory module (that is, a flash memory module that can store 3 bits of data in one storage unit), other flash memory modules, or other memory modules with the same characteristics.

FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. FIG. 6 is a schematic diagram of a memory cell array according to an exemplary embodiment of the present invention.

Please refer to FIG. 5, the rewritable non-volatile memory module 406 includes a memory cell array 502, a word line control circuit 504, a bit line control circuit 506, a row decoder (column decoder) 508, and a data input/output buffer 510 and control circuit 512 .

In this exemplary embodiment, the memory cell array 502 may include a plurality of memory cells 602 for storing data, a plurality of select gate drain (SGD for short) transistors 612 and a plurality of select gate source (selectgate source) , SGS for short) transistor 614, and a plurality of bit lines 604, a plurality of word lines 606, and a common source line 608 connected to these memory cells (as shown in FIG. 6 ). The memory cells 602 are arranged in an array (or three-dimensionally stacked) at intersections of the bit lines 604 and the word lines 606 . When receiving a write instruction or a read instruction from the memory control circuit unit 404, the control circuit 512 will control the word line control circuit 504, the bit line control circuit 506, the row decoder 508, and the data input/output buffer 510 to write Entering data into the memory cell array 502 or reading data from the memory cell array 502, wherein the word line control circuit 504 is used to control the voltage applied to the word line 606, and the bit line control circuit 506 is used to control the voltage applied to the bit line The voltage of the line 604, the row decoder 508 selects the corresponding bit line according to the column address in the command, and the data input/output buffer 510 is used for temporarily storing data.

Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits by changing a voltage (also referred to as threshold voltage hereinafter). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This process of changing the threshold voltage is also called "writing data into the memory cell" or "programming the memory cell". Each memory cell of the memory cell array 502 has multiple storage states as the threshold voltage changes. And by applying a read voltage, it can be determined which storage state the memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

FIG. 7 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Referring to FIG. 7 , the memory control circuit unit 404 includes a memory management circuit 702 , a host interface 704 , a memory interface 706 and an error checking and correction circuit 708 .

The memory management circuit 702 is used to control the overall operation of the memory control circuit unit 404 . Specifically, the memory management circuit 702 has a plurality of control instructions, and when the memory storage device 10 is operating, these control instructions are executed to perform operations such as writing, reading, and erasing data. When describing the operation of the memory management circuit 702 below, it is equivalent to describing the operation of the memory control circuit unit 404 .

In this exemplary embodiment, the control instructions of the memory management circuit 702 are implemented in the form of firmware. For example, the memory management circuit 702 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 702 can also be stored in a specific area of the rewritable non-volatile memory module 406 in the form of program code (for example, a system area in the memory module dedicated to storing system data) middle. In addition, the memory management circuit 702 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to store in the rewritable non-volatile memory module The control instructions in 406 are loaded into the random access memory of the memory management circuit 702 . Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 702 may also be implemented in a hardware form. For example, the memory management circuit 702 includes a microcontroller, a physical unit management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit and a data processing circuit. The physical unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. Wherein, the physical unit management circuit is used to manage the physical erasing unit of the rewritable non-volatile memory module 406; the memory write circuit is used to issue a write command sequence to the rewritable non-volatile memory module 406 to write data Write in the rewritable non-volatile memory module 406; the memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 406 to read from the rewritable non-volatile memory module 406 Read data; the memory erasing circuit is used to issue an erase command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406; and the data processing circuit is used to Data to be written into the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406 are processed. The write command sequence, the read command sequence and the erase command sequence may respectively include one or more program codes or command codes and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding write, read and erase operations.

The host interface 704 is electrically connected to the memory management circuit 702 and used for receiving and identifying commands and data transmitted by the host system 11 . That is to say, the commands and data sent by the host system 11 are sent to the memory management circuit 702 through the host interface 704 . In this exemplary embodiment, the host interface 704 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 704 may also be compatible with PATA standard, IEEE 1394 standard, PCIExpress standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 706 is electrically connected to the memory management circuit 702 and used for accessing the rewritable non-volatile memory module 406 . That is to say, the data to be written into the rewritable nonvolatile memory module 406 will be converted into a format acceptable to the rewritable nonvolatile memory module 406 via the memory interface 706 . Specifically, if the memory management circuit 702 wants to access the rewritable non-volatile memory module 406, the memory interface 706 will transmit the corresponding instruction sequence. These command sequences may include one or more signals, or data on a bus. For example, in the read instruction sequence, the read identification code, memory address and other information will be included.

The error checking and correcting circuit 708 is electrically connected to the memory management circuit 702 and used for executing error checking and correcting procedures to ensure the correctness of data. Specifically, when the memory management circuit 702 receives a write command from the host system 11, the error checking and correction circuit 708 will generate a corresponding error correcting code (ECC for short) for the data corresponding to the write command. and/or error checking code (error detecting code, referred to as EDC), and the memory management circuit 702 will write the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable non-volatile In the sex memory module 406. Afterwards, when the memory management circuit 702 reads data from the rewritable non-volatile memory module 406, it will simultaneously read the error correction code and/or error check code corresponding to the data, and the error check and correction circuit 708 will be based on The error correction code and/or error check code performs error checking and correction procedures on the read data.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 710 and a power management circuit 712 . The buffer memory 710 is electrically connected to the memory management circuit 702 and used for temporarily storing data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406 . The power management circuit 712 is electrically connected to the memory management circuit 702 and used for controlling the power of the memory storage device 10 .

FIG. 8 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. It must be understood that when describing the operation of the physical erasing unit of the rewritable non-volatile memory module 406, words such as "selection", "grouping", "dividing", and "association" are used to operate physical erasing. A unit is a logical concept. That is to say, the actual position of the physical erasing unit of the rewritable non-volatile memory module is not changed, but the physical erasing unit of the rewritable non-volatile memory module is logically operated.

The storage units of the rewritable non-volatile memory module 406 constitute a plurality of physical programming units, and these physical programming units constitute a plurality of physical erasing units. Specifically, the storage units on the same word line form one or more physical programming units. If each storage unit can store more than 2 bits, the physical programming units on the same word line can be classified into at least lower physical programming units and upper physical programming units. For example, the Least Significant Bit (LSB) of a storage unit belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a storage unit belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit is greater than that of the upper physical programming unit, or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit. unit reliability. In this exemplary embodiment, the entity programming unit is the smallest unit of programming. That is, the entity programming unit is the smallest unit for writing data. For example, the entity programming unit is an entity page or an entity sector. If the physical programming unit is a physical page, each physical programming unit usually includes a data bit area and a redundant bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (eg, error correction code). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B for short). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the present invention does not limit the size and number of physical sectors. On the other hand, the entity erasing unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased. For example, the physical erasing unit is a physical block.

Please refer to FIG. 8, the memory management circuit 702 can logically divide the physical erasing units 800(0)-800(R) of the rewritable non-volatile memory module 406 into multiple areas, for example, the storage area 802 and the system District 806.

The physical erase unit of the storage area 802 is used to store data from the host system 11 . Valid data and invalid data are stored in the storage area 802 . For example, when the host system wants to delete a piece of valid data, the deleted data may still be stored in the storage area 802, but it will be marked as invalid data. A physical erasing unit that does not store valid data is also called a spare physical erasing unit. For example, the erased physical erasing unit becomes an idle physical erasing unit. If a physical erasing unit in the storage area 802 or the system area 806 is damaged, the physical erasing unit in the storage area 802 can also be used to replace the damaged physical erasing unit. If there is no available physical erasing unit in the storage area 802 to replace the damaged physical erasing unit, the memory management circuit 702 may declare the entire memory storage device 10 as a write-protected (write protect) state, and cannot write input data. In addition, the physical erasing unit that stores valid data is also referred to as a non-spare physical erasing unit.

The physical erasing unit of the system area 806 is used to record system data, wherein the system data includes the manufacturer and model of the memory chip, the number of physical erasing units of the memory chip, and the number of physical programming units of each physical erasing unit Wait.

The number of physical erasing units in the storage area 802 and the system area 806 varies according to different memory specifications. In addition, it must be understood that during the operation of the memory storage device 10 , the grouping relationship of the physical erasing unit associated with the storage area 802 and the system area 806 will change dynamically. For example, when the physical erasing unit in the system area 806 is damaged and replaced by the physical erasing unit in the storage area 802 , the original physical erasing unit in the storage area 802 will be associated with the system area 806 .

The memory management circuit 702 configures the logic units 810 ( 0 )˜ 810 (D) to map to the physical erase units 800 ( 0 )˜ 800 (A) in the storage area 802 . For example, in this exemplary embodiment, the host system 11 accesses the data in the storage area 802 through logical addresses, therefore, each logical unit 810(0)˜810(D) refers to a logical address. In addition, in an exemplary embodiment, each logical unit 810(0)-810(D) may also refer to a logical sector, a logical programming unit, a logical erasing unit, or consist of multiple consecutive logical addresses . Each logical unit 810(0)-810(D) is mapped to one or more physical units. In this exemplary embodiment, a physical unit refers to a physical erasing unit. However, in another exemplary embodiment, a physical unit may also be a physical address, a physical sector, a physical programming unit, or consist of multiple consecutive physical addresses, which are not limited by the present invention. The memory management circuit 702 records the mapping relationship between the logical unit and the physical unit in one or more logical-physical mapping tables. When the host system 11 intends to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 702 can perform data storage for the memory storage device 10 according to the one or more logical-physical mapping tables. Pick.

FIG. 9 is a schematic diagram showing threshold voltage distributions of a plurality of memory cells according to an exemplary embodiment of the present invention.

Referring to FIG. 9 , the horizontal axis represents the threshold voltage of the memory cells, and the vertical axis represents the number of memory cells. For example, FIG. 9 shows the threshold voltages of each memory cell in a physical cell. It is assumed here that when the critical voltage of a certain memory cell falls within the distribution 901, the memory cell stores a bit "1"; conversely, if the critical voltage of a certain memory cell falls within the distribution 902, the stored bit The cell stores a bit "0". It is worth mentioning that, in this exemplary embodiment, each memory cell is used to store one bit, so there are two possible distributions of the threshold voltage. However, in other exemplary embodiments, if a memory cell is used to store multiple bits, there may be four, eight or any other possible distributions of the corresponding threshold voltages. In addition, the present invention does not limit the bits represented by each distribution.

When data is to be read from the rewritable nonvolatile memory module 406 , the memory management circuit 702 sends a read command sequence to the rewritable nonvolatile memory module 406 . The read instruction sequence includes one or more instructions or program codes. The read command sequence is used to instruct to read multiple storage units in a certain physical unit to obtain multiple bits. For example, according to the read command sequence, the rewritable non-volatile memory module 406 will use the read voltage V _read-0 to read these memory cells and transmit the corresponding bit data to the memory management circuit 702 . For example, if the threshold voltage of a certain memory cell is less than the read voltage V _read-0 (for example, the memory cell belonging to the distribution 901), the memory management circuit 702 will read bit "1"; if the threshold voltage of a certain memory cell Greater than the read voltage V _read-0 (eg, memory cells belonging to the distribution 902 ), the memory management circuit 702 will read a bit "0".

However, as the usage time of the rewritable non-volatile memory module 406 increases and/or the operating environment changes, performance degradation of the distributions 901 and 902 may occur. After performance degradation occurs, the distributions 901 and 902 may gradually approach each other or even overlap each other. For example, distribution 911 and distribution 912 are used to represent distributions 901 and 902 after performance degradation, respectively. Distribution 911 and distribution 912 contain an overlapping region 913 . The overlapping area 913 indicates that some memory cells should store a bit "1", but their threshold voltage is greater than the read voltage V _read-0 ; or, some memory cells should store a bit "0", but Its threshold voltage is lower than the read voltage V _read-0 . After performance degradation occurs, if the read voltage V _read-0 is continuously used to read the memory cells belonging to the distribution 911 or the distribution 912 , the read bits may contain more errors. For example, a storage unit belonging to distribution 911 is misjudged as belonging to distribution 912 , or a storage unit belonging to distribution 912 is misjudged as belonging to distribution 911 . Therefore, in this exemplary embodiment, the error checking and correcting circuit 708 decodes the read bits to correct errors therein. In the following exemplary embodiments, the read voltage is also referred to as a read voltage level. Each read voltage level has at least one voltage value.

In this exemplary embodiment, the ECC circuit 708 encodes the data to be stored in the rewritable non-volatile memory module 406 and generates an encoding unit. This coding unit is a block code. The memory management circuit 702 sends a write command sequence to the rewritable non-volatile memory module 406 . The write command sequence includes at least one command or program code. The write command sequence is used to instruct to write the encoding unit into an appropriate area (hereinafter referred to as the first area) in the rewritable non-volatile memory module 406 . For example, the first area may be at least one solid unit. According to the write command sequence, the rewritable non-volatile memory module 406 will store the coding unit in the first area. Then, when the memory management circuit 702 instructs to read the data in the first area, the rewritable non-volatile memory module 406 will read the coding unit from the first area, and the error checking and correction circuit 708 will perform a decoding program to decode this code unit.

Fig. 10 is a schematic diagram of a coding unit according to an exemplary embodiment of the present invention.

Please refer to FIG. 10 , the coding unit 1010 includes bits b _{11 ˜b nm} . If bits b ₁₁ -b _nm are grouped into sub-coding units 1011-101n, each sub-coding unit 1011-101n has m bits. Both n and m can be any positive integer greater than 1. In this exemplary embodiment, some bits are determined by multiple encoding procedures. For example, the encoding procedure whose encoding direction is the row direction (for example, from left to right) can be regarded as the first type of encoding procedure, and the encoding procedure whose encoding direction is the column direction (for example, from top to bottom) can be regarded as For the second type of coding procedure. In an exemplary embodiment, the first type of encoding procedure is also referred to as a row encoding procedure, and the second type of encoding procedure is also referred to as a column encoding procedure.

In this exemplary embodiment, the first type of encoding procedure is executed first, and according to the encoding result of the first type of encoding procedure, the second type of encoding procedure is subsequently executed. For example, assuming that the user data to be stored includes bits b ₁₁ ~b _1p , b ₂₁ ~b _2p , ..., b _r1 ~b _rp , then in the first type of encoding procedure, bits b ₁₁ ~b _1p , b ₂₁ ~ b _2p , ..., b _r1 ~b _rp will be coded to obtain bits b ₁₁ ~b _1m (ie, sub-coding unit 1011 ), b ₂₁ ~b _2m (ie, sub-coding unit 1012 ), ..., b _r1 ~ b _rm (ie, the sub-coding unit 101r). Bits b _1q ~ b _1m are error correction codes corresponding to bits b ₁₁ ~ b _1p , bits b _2q ~ b _2m are error correction codes corresponding to bits b ₂₁ ~ b _2p , and so on, where q is equal to p+1 . After the sub-encoding units 1011-101r are obtained, the second type of encoding procedure will be executed. For example, in the second type of encoding procedure, bits b ₁₁ ~ b _r1 (that is, the first bit in each sub-coding unit 1011 ~ 101r), bits b ₁₂ ~ b _r2 (that is, the first bit in each sub-coding unit 1011 the second bit in ~101r), ..., bits b _1m ~b _rm (that is, the mth bit in each sub-coding unit 1011 ~ 101r) will be respectively encoded to obtain bits b ₁₁ ~b _n1 , b _{12 ˜b n2} , . . . , b _{1m ˜b nm} . Bits b _s1 ~b _n1 are error correction codes corresponding to bits b ₁₁ ~b _r1 , bits b _s2 ~b _n2 are error correction codes corresponding to bits b ₁₂ ~b _r2 , and so on, where s is equal to r+1 .

After the encoding unit 1010 is read out, the encoding unit 1010 will be decoded corresponding to the encoding sequence adopted. For example, in this exemplary embodiment, the decoding program whose decoding direction is the column direction (also referred to as the second type of decoding program) will be executed first, and according to the decoding result of the second type of decoding program, the decoding direction is the row direction The program (also referred to as the first type of decoding program) will be executed in succession. For example, in the second type of decoding procedure, bits b _s1 ~ b _n1 , b _s2 ~ b _n2 , ..., b _sm ~ b _nm will be used to decode bits b ₁₁ ~ b _r1 , b ₁₂ ~ b _r2 , ... , b _1m ~b _rm to decode. After obtaining the decoded bits b _{11 ˜b r1} , b _{12 ˜b r2} , . . . , b _{1m ˜b rm} , the first type of decoding procedure will be executed. For example, in the first type of decoding program, the bits b _1q ~ b _1m , b _2q ~ b _2m , ..., b _rq ~ b _rm decoded by the second type of decoding program will be used respectively for the bits decoded by the second type of decoding program The program decoded bits b _{11 ˜b 1p} , b _{21 ˜b 2p} , . . . , b _{r1 ˜b rp} are decoded to obtain decoded user data.

It is worth mentioning that the composition of the coding unit and the encoding/decoding order mentioned in the above exemplary embodiments are just an example and not intended to limit the present invention. For example, in another exemplary embodiment, the generated error correction code may also be arranged before or interspersed in the corresponding user data. Or, in an exemplary embodiment, when encoding user data, it is also possible to execute the second type of encoding program first, and then execute the first type of encoding program according to the encoding result of the second type of encoding program; correspondingly, in When decoding the coding unit, the first type of decoding program may be executed first, and then the second type of decoding program is executed according to the decoding result of the first type of decoding program. In addition, the encoding directions of the first type of encoding program (or the first type of decoding program) and the second type of encoding program (or the second type of decoding program) are different, but the first type of encoding program (or the first type of decoding program) and the second type The second type of encoding procedure (or the second type of decoding procedure) can use the same or different encoding/decoding algorithms. For example, the first type of encoding program and the corresponding first type of decoding program may include low density parity correction code (low density parity code, LDPC for short), BCH code and Reed-Solomon code (Reed-Solomon code, RS for short). code), block turbo code (block turbo code, referred to as BTC) and other encoding/decoding algorithms; and the second type of encoding program and the corresponding second type of decoding program can also include the above encoding/decoding at least one of the algorithms or other types of encoding/decoding algorithms.

In this exemplary embodiment, the memory management circuit 702 sends a read command sequence (hereinafter referred to as the first read command sequence) to the rewritable non-volatile memory module 406 . The first read command sequence is used to instruct to read data from the above-mentioned first area. After receiving the first read command sequence, the rewritable non-volatile memory module 406 will read the first area according to a read voltage level (hereinafter also referred to as the first read voltage level). A plurality of storage units in to obtain a coding unit (hereinafter also referred to as a first coding unit). The first coding unit belongs to a block code. The introduction of the coding unit has been described in detail above, so it will not be repeated here. Then, the ECC circuit 708 executes a decoding procedure (hereinafter also referred to as the first decoding procedure) on the first encoding unit and records corresponding decoding information (hereinafter also referred to as the first decoding information).

In this exemplary embodiment, the first decoding procedure is an iterative decoding procedure. For example, in the first decoding process, the error checking and correction circuit 708 will perform at least one iterative decoding operation, so as to improve the reliability information of the first coding unit by iteratively updating the reliability information (for example, decoding initial value) of the first coding unit. decoding success rate. Each iterative decoding operation may include the same or similar decoding operations as described in the exemplary embodiment of FIG. 10 . In general, depending on the number of errors (also called erroneous bits) in the coding unit, the first decoding procedure may succeed or fail. For example, after at least one iterative decoding operation, if the decoding is successful, for example, the error checking and correction circuit 708 determines that all errors in the first coding unit have been corrected, the error checking and correction circuit 708 will output the decoded (or Corrected) first coding unit. On the contrary, if the number of erroneous bits in the first coding unit is too large and/or the distribution of these erroneous bits is just in a position where it cannot be corrected, etc., the number of iterative decoding operations performed by the error checking and correction circuit 708 has already been exceeded. When a preset number of times is reached, the error checking and correction circuit 708 will determine that the decoding fails.

It is worth mentioning that, from the exemplary embodiment shown in FIG. 10 , either the first type of decoding process corresponding to a certain row or the second type of decoding process corresponding to a certain column may succeed or fail. Each execution of the first type of decoding program is independent, and each execution of the second type of decoding program is also independent. For example, the first type of decoding procedure for the sub-coding unit 1011 may succeed or fail, and the second type of decoding procedure for the sub-coding unit 1012 may also succeed or fail, and the two may be irrelevant. Therefore, even if the decoding of the first coding unit fails, there may still be successfully decoded rows, columns or bits therein.

The memory management circuit 702 will record the successfully decoded information as the first decoded information. For example, the first decoding information may include a value (hereinafter also referred to as the first value). The first value is related to the decoding result of the first coding unit (hereinafter also referred to as the first decoding result). For example, the first value is determined according to the first decoding result. For example, the first value is the number of successfully decoded units that is positively correlated with the first decoding procedure (hereinafter also referred to as the first number of successfully decoded units). In this exemplary embodiment, the first number of successfully decoded units refers to the number of successfully decoded units in the first coding unit. For example, a successfully decoded unit may refer to a successfully decoded row, a successfully decoded column, or a successfully decoded bit. The memory management circuit 702 may directly use the first number of successfully decoded units as the first value. For example, the memory management circuit 702 may directly calculate the number of successfully decoded rows in the first coding unit (hereinafter also referred to as the number of successfully decoded first row units), the number of successfully decoded columns in the first coding unit (hereinafter also referred to as is called the number of successfully decoded units in the first column), or the number of successfully decoded bits in the first coding unit is used as the first value. Alternatively, the memory management circuit 702 may also perform a logical operation according to the number of successfully decoded units in the first row and the number of successfully decoded units in the first column to determine the first value. For example, the memory management circuit 702 may multiply the number of successfully decoded units in the first row by a weight (hereinafter also referred to as the first weight) to obtain a parameter (hereinafter also referred to as the first parameter) and multiply the number of successfully decoded units in the first column by Adding another weight (hereinafter also referred to as the second weight) to obtain another parameter (hereinafter also referred to as the second parameter); the memory management circuit 702 can add the first parameter and the second parameter to determine the first value. Taking the exemplary embodiment of FIG. 10 as an example, the first weight may be n/(n+m), and the second weight may be m/(n+m). However, the first weight and the second weight can also be set according to practical requirements, which is not limited by the present invention. In addition, in another exemplary embodiment, the memory management circuit 702 may also input the first number of successfully decoded units into a lookup table and use the output of the lookup table as the first value.

After determining that the decoding of the first encoding unit fails, the memory management circuit 702 instructs the rewritable non-volatile memory module 406 to adjust the read voltage. For example, the read voltage used to read the first region is adjusted from a first read voltage level to another read voltage level (hereinafter also referred to as a second read voltage level). The memory management circuit 702 sends another read command sequence (hereinafter referred to as the second read command sequence) to the rewritable non-volatile memory module 406 . The second read command sequence is used to instruct to read the above-mentioned first area according to the second read voltage level. After receiving the second read instruction sequence, the rewritable non-volatile memory module 406 will read the storage unit in the first area again according to the second read voltage level to obtain another encoding unit (hereinafter Also known as the second coding unit). The second coding unit also belongs to the block code. Since the reading voltage level for reading data changes, some bits in the second encoding unit may be different from bits at the same position in the first encoding unit. For example, bit b ₁₁ in the second CU may be different from bit b ₁₁ in the first CU.

The ECC circuit 708 executes another decoding procedure (hereinafter also referred to as the second decoding procedure) on the second encoding unit and records corresponding decoding information (hereinafter also referred to as the second decoding information). How to execute the decoding process for the coding unit has been described in detail above, so it will not be repeated here.

It is worth mentioning that even if the decoding of the second coding unit fails, there may still be rows, columns or bits that are successfully decoded. The memory management circuit 702 will record the successfully decoded information as the second decoded information. For example, the second decoding information may include a value (hereinafter also referred to as a second value). The second value is related to the decoding result of the second coding unit (hereinafter also referred to as the second decoding result). For example, the second value is determined according to the second decoding result. For example, the second value is the number of successfully decoded units positively related to the second decoding program (hereinafter also referred to as the second number of successfully decoded units). In this exemplary embodiment, the second number of successfully decoded units refers to the number of successfully decoded units in the second coding unit. For example, the memory management circuit 702 may directly calculate the number of successfully decoded rows in the second coding unit (hereinafter also referred to as the number of successfully decoded second row units), the number of successfully decoded columns in the second coding unit (hereinafter also referred to as is called the number of successfully decoded units in the second column), or the number of successfully decoded bits in the second coding unit is used as the second value. Alternatively, the memory management circuit 702 may also perform a logical operation according to the number of successfully decoded units in the second row and the number of successfully decoded units in the second column to determine the second value. In addition, the memory management circuit 702 may also input the second number of successfully decoded units into a lookup table and use the output of the lookup table as the second value. For how to determine the second value, reference can be made to the above description about the first value, so details will not be repeated here.

After obtaining the first decoded information and the second decoded information, the memory management circuit 702 estimates another read voltage level (hereinafter referred to as the third read voltage) according to the first decoded information and the second decoded information. level). In this exemplary embodiment, the third read voltage level can be regarded as an optimal read voltage level estimated for the first region. For example, the optimal reading voltage level may refer to the reading voltage level estimated based on past historical records and used to read out the coding unit with the highest decoding success rate. For example, the memory management circuit 702 can compare the first value with the second value and determine the third read voltage level according to the comparison result. For example, if the first value is greater than the second value, the memory management circuit 702 can determine the third read voltage level according to the first read voltage level. For example, in this exemplary embodiment, if the first value is greater than the second value, the memory management circuit 702 may directly set the first read voltage level to the third read voltage level. Or, in another exemplary embodiment, if the first value is greater than the second value, the memory management circuit 702 may also perform a logical operation according to the first read voltage level to determine the third read voltage level. Not limited. In addition, if the first value is smaller than the second value, the memory management circuit 702 can determine the third read voltage level according to the second read voltage level. For example, in this exemplary embodiment, if the first value is smaller than the second value, the memory management circuit 702 can directly set the second read voltage level to the third read voltage level. Or, in another exemplary embodiment, if the first value is smaller than the second value, the memory management circuit 702 may also perform a logical operation according to the second read voltage level to determine the third read voltage level. Not limited.

It is worth mentioning that although the above exemplary embodiment is described with two consecutive read operations and decoding operations as an example, in another exemplary embodiment, the two read operations mentioned in the above exemplary embodiment Fetching and decoding operations can also be discontinuous. More read operations and decode operations can be used to process data stored in the same area. For example, in an exemplary embodiment of FIG. 9 , a plurality of available read voltage levels V _{read-0 ˜V read-3} may be recorded in a look-up table. According to the look-up table, the read voltage level V _read-0 can be used to read the data of the above-mentioned first area first. Afterwards, if the decoding of the read coding unit fails, according to the look-up table, the read voltage level V _read-1 can be continuously used to read the data in the first area. Afterwards, if the decoding of the read coding units still fails, the read voltage level V _read-2 can be continuously used to read the data in the first area and the corresponding decoding operation will be performed. Afterwards, if the decoding of the read coding units still fails, the read voltage level V _read-3 can be used to read the data in the first area and the corresponding decoding operation will be performed. The first read voltage level mentioned in the above exemplary embodiments may be any one of the read voltage levels V _{read- 0˜V read-2} shown in FIG. The second read voltage level can be any read voltage level applied after the first read voltage level. For example, if the first read voltage level is the read voltage level V _read-0 , the second read voltage level can be any one of the read voltage levels V read _{- 1˜V read-3} , and so on. In addition, the order in which the read voltage levels V _{read-0 ˜V read-3} are used can also be adjusted, which is not limited by the present invention. For example, in another exemplary embodiment, the read voltage levels V _read-0 ˜ V _read-3 may also be used sequentially according to the voltage values from small to large.

In an exemplary embodiment, for the same area in the rewritable non-volatile memory module 406, if the read voltage levels recorded in the look-up table have been used and the read code units cannot is successfully decoded, the above-mentioned operation of determining the third read voltage level according to the plurality of used read voltage levels will be performed. However, in another exemplary embodiment, it can also be set that after trying to use certain reading voltage levels or changing the reading voltage levels for more than a preset number of times, the above-mentioned functions based on multiple usage The operation of determining the third read voltage level based on the passed read voltage level is not limited in the present invention. In addition, although the above exemplary embodiments are iterative decoding procedures as examples of the first decoding procedure and the second decoding procedure, however, in another exemplary embodiment, the first decoding procedure and/or the second decoding procedure may also belong to The non-iterative decoding procedure is not limited by the present invention.

In an exemplary embodiment, during the process of using a certain read voltage level to read the encoding unit and perform the corresponding decoding process, the bit values at the partially successfully decoded positions can be considered correct and are record it. For example, if a row or column is successfully decoded, the bit values of each position in the row or column can be recorded. In the next decoding procedure, the recorded bit value can be used as additional decoding information. For example, in an exemplary embodiment, assuming that the decoding of a coding unit fails but the decoding result indicates that the bit b ₁₁ in the coding unit is correct, the bit value of the bit b ₁₁ will be recorded. When adjusting the read voltage level to read the same data and perform the next decoding on the read data, the bit b ₁₁ in the read coding unit will be directly corrected to the previously recorded bit value . Or, in the next decoding procedure, the recorded bit values may be skipped, thereby reducing the number of bits to be checked in each coding unit obtained. Thereby, during the process of executing corresponding decoding procedures according to different reading voltage levels, some bits in the coding unit can be gradually corrected, thereby increasing the success rate of decoding. In addition, the present invention does not limit the types of additional decoding information that can be passed on, and any decoding information that can be passed to the next decoding process can be recorded and used in the next decoding process.

After determining the third read voltage level, the memory management circuit 702 can perform at least one preset operation related to the rewritable non-volatile memory module 406 according to the third read voltage level. This preset operation may be used to optimize the rewritable non-volatile memory module 406 for data storage, reading or management of physical units.

In an exemplary embodiment, the error checking and correction circuit 708 may perform hard bit pattern decoding and soft bit pattern decoding. Taking the SLC flash memory as an example, in hard bit mode decoding, a read voltage level is applied to a memory cell. According to whether the memory cell is turned on in response to the read voltage level, the rewritable non-volatile memory module 406 returns a bit (also called a verification bit). Afterwards, the error checking and correcting circuit 708 performs decoding according to the verification bit. In hard bit mode decoding, the obtained verification bits are also called hard bits. Also taking the SLC type flash memory as an example, in soft bit mode decoding, multiple read voltage levels will be applied to a memory cell. According to the conduction state of the memory cell in response to the read voltage levels, the rewritable non-volatile memory module 406 returns a plurality of verification bits. Then, the error checking and correcting circuit 708 performs decoding according to the verifying bits. In soft bit mode decoding, the obtained verification bits are also called soft bits. In the iterative decoding procedure of hard bit mode decoding, the decoding initial value of a storage unit can be divided into two values according to a verification bit corresponding to the storage unit. For example, if the verification bit is "1", the initial decoding value of the corresponding storage unit can be set to "-n"; if the verification bit is "0", the initial decoding value of the corresponding storage unit can be set to "-n ". The iterative decoding process of hard bit mode decoding is performed based on these two values. However, in the iterative decoding procedure of soft bit pattern decoding, the decoding initial value of a storage unit is determined according to a plurality of verification bits corresponding to the storage unit.

In an exemplary embodiment, the decoding performed by the error checking and correcting circuit 708 is hard bit mode decoding until the plurality of read voltage levels in the above-mentioned look-up table are used up. If multiple read voltage levels in the above-mentioned lookup table are used up and the data read from the same area still cannot be successfully decoded, the ECC circuit 708 may switch to use soft bit mode decoding. In soft bit mode decoding, the memory management circuit 702 instructs to read the above-mentioned first area according to the third read voltage level to obtain a decoding unit (hereinafter also referred to as a third decoding unit). In addition, the memory management circuit 702 also instructs to determine a plurality of read voltage levels (hereinafter referred to as fourth read voltage levels) whose voltage values are close to the voltage value of the third read voltage level read voltage levels) and read the first region according to the fourth read voltage levels to obtain a plurality of soft bits. The fourth read voltage levels may or may not include the third read voltage levels. Each soft bit can provide one bit of additional decoding information in the third decoding unit. The ECC circuit 708 can execute a corresponding decoding procedure (also referred to as a third decoding procedure) on the third decoding unit.

FIG. 11 is a schematic diagram of reading a plurality of soft bits according to an exemplary embodiment of the present invention.

Please refer to FIG. 11 , assuming that the determined fourth read voltage level includes read voltage levels V ₁ -V ₅ , then in soft bit mode decoding, the read voltage levels V ₁ -V ₅ will be used to The memory cells belonging to distributions 1110 and 1120 in the above-mentioned first area are read. In response to the read voltage levels V ₁ -V ₅ , a plurality of soft bits b ₁ -b ₅ are obtained. For example, if the critical voltage of a memory cell is in the voltage range 1101, the read soft bits b ₁ -b ₅ will be "11111"; if the critical voltage of a certain memory cell is in the voltage range 1102, the read The fetched soft bits b ₁ to b ₅ will be "01111"; if the critical voltage of a certain memory cell is in the voltage range 1103, the read soft bits b ₁ to b ₅ will be "00111"; The critical voltage of a memory cell is in the voltage range 1104, then the read soft bits b ₁ ~ b ₅ will be "00011"; if the critical voltage of a certain memory cell is in the voltage range 1105, the read soft bits The bits b ₁ -b ₅ will be "00001"; if the threshold voltage of a memory cell is within the voltage range 1106, the read soft bits b ₁ -b ₅ will be "00000". In soft bit mode decoding, the read soft bits b ₁ -b ₅ are used to perform corresponding iterative decoding on the third decoding unit. For example, corresponding to each voltage interval, the probability of the memory cell belonging to the distribution 1110 and the probability of belonging to the distribution 1120 can be calculated in advance. Based on these two probabilities, the Log Likelihood Ratio (LLR) can be calculated. The logarithmic likelihood ratio can be used to determine the absolute value of the decoded initial value. For example, the decoding initial values corresponding to each voltage range may be calculated in advance and stored in a lookup table. The obtained soft bits b ₁ -b ₅ can be input into this lookup table, and corresponding decoding initial values can be obtained. Thereafter, the error checking and correction circuit 708 can perform subsequent decoding according to the obtained decoding initial value.

In other words, soft bit pattern decoding uses more decoding information (eg, verification bits) than hard bit pattern decoding. Based on more decoding information used, the decoding success rate of soft bit mode decoding is usually higher than that of hard bit mode decoding. Therefore, it is possible for soft bit pattern decoding to successfully complete decoding where hard bit pattern decoding fails.

In an exemplary embodiment, the memory management circuit 702 may determine the degree of wear of the memory cells in the first region or the voltage distribution state of the memory cells according to the third read voltage level. For example, in the exemplary embodiment of FIG. 9, for the memory cells belonging to the distributions 911 and 912, using the read voltage level V _read-0 to read these memory cells can read the memory cells with a lower error rate. data; and after the performance degradation occurs, for the memory cells belonging to the distributions 911 and 912, the data with a lower error rate can be read by using the read voltage level V _read-3 to read these memory cells. Therefore, according to the determined third reading voltage level, the memory management circuit 702 can also obtain the current wear level of these memory cells or the current voltage distribution state of these memory cells by means of table lookup. For example, the read voltage levels V _read-0 ˜ V _read-3 in FIG. 9 may respectively correspond to a loss level or a voltage distribution state. It is worth mentioning that, in an exemplary embodiment, the degree of wear is related to the usage status of the storage unit or the current operating environment. For example, if the times of reading, writing and erasing of a storage unit increase, the degree of wear of the storage unit may increase synchronously. For example, if the time interval for storing data in the storage unit increases, the degree of wear of the storage unit may increase synchronously. For example, if the temperature or humidity of the current operating environment of the rewritable non-volatile memory module 406 is too high, the degree of wear of the storage unit may also increase synchronously. In addition, the degree of wear may also be related to the correctness/error rate of the data stored in the storage unit. For example, the higher the degree of wear of the storage unit, the lower the correctness of the data stored in the storage unit or the higher the error rate of the data stored in the storage unit.

In an exemplary embodiment, the memory management circuit 702 can determine a default programming voltage corresponding to the above-mentioned first region according to the third read voltage level. For example, if the rewritable non-volatile memory module 406 uses an incremental step pulse erasing (Incremental Step Pulse Program, ISPP) model to program memory cells, the memory management circuit 702 can read The voltage level is used to instruct the rewritable non-volatile memory module 406 to adjust an initial programming voltage in the incremental step pulse model. The initial programming voltage is the programming voltage first applied to the memory cells in the first region in the incremental step pulse model. In addition, any programming parameters or erasing parameters that are related to adjusting the initial programming voltage and/or can achieve similar effects can also be adjusted.

It should be noted that the present invention does not limit the preset operations that can be performed according to the third read voltage level to the above. For example, in another exemplary embodiment, any parameter or memory setting that can be adjusted correspondingly according to the performance degradation, wear degree, or voltage distribution state of the memory cell can be appropriately adjusted in response to the third read voltage level adjustment, so as to improve the management capability of the rewritable non-volatile memory module 406 . For example, in an exemplary embodiment, according to the third read voltage level, the physical unit to which the above-mentioned first region belongs may also be marked as damaged and so on. In addition, in an exemplary embodiment, according to the third read voltage level, any information beneficial to the management of the rewritable nonvolatile memory module 406 such as the service life of the rewritable nonvolatile memory module 406 is also can be obtained.

It should be noted that although the above-mentioned exemplary embodiments are described by taking one storage unit to store one bit as an example, in another exemplary embodiment, the above-mentioned operation of reading the coding unit, the above-mentioned operation of decoding the coding unit, and estimation The operation of measuring the read voltage level can also be applied to the usage scenario where one memory cell can store multiple bits. For example, the estimated read voltage level may also be used to read data stored in memory cells operating in MLC mode or TLC mode.

FIG. 12 is a flowchart of a method for estimating a read voltage level according to an exemplary embodiment of the present invention.

Please refer to FIG. 12, in step S1201, according to the first read voltage level, the first area in the rewritable non-volatile memory module will be read to obtain the first encoding unit, wherein the first A coding unit belongs to the block code. In step S1202, a first decoding procedure for the first coding unit is executed and first decoding information is recorded. In step S1203, according to the second reading voltage level, the first area is read to obtain a second encoding unit, wherein the second encoding unit belongs to the block code. In step S1204, a second decoding procedure for the second coding unit is executed and second decoding information is recorded. In step S1205, according to the first decoded information and the second decoded information, a third read voltage level is estimated and obtained. In step S1206, according to the third read voltage level, at least one preset operation related to the rewritable non-volatile memory module may be performed.

However, each step in FIG. 12 has been described in detail above, and will not be repeated here. It should be noted that each step in FIG. 12 can be implemented as a plurality of program codes or circuits, which is not limited in the present invention. In addition, the method in FIG. 12 can be used in combination with the above exemplary embodiments, or can be used alone, which is not limited by the present invention.

To sum up, after reading the memory with different read voltage levels and attempting to decode the obtained data, decoded information corresponding to different encoding units will be recorded. Thereafter, the decoded information can be used as a basis for estimating an appropriate read voltage level, and at least one predetermined operation can be performed accordingly. Thereby, the management capability of the rewritable non-volatile memory module using the block code can be improved.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (33)

1. A method for estimating a read voltage level, characterized in that, for a rewritable non-volatile memory module, the method for estimating a read voltage level comprises: reading a first area in the rewritable non-volatile memory module according to a first read voltage level to obtain a first coding unit, wherein the first coding unit belongs to a block code; performing a first decoding procedure on the first encoding unit and recording first decoding information; reading the first area according to a second reading voltage level to obtain a second encoding unit, wherein the second encoding unit belongs to the block code; performing a second decoding procedure on the second encoding unit and recording second decoding information; Estimating and obtaining a third read voltage level according to the first decoded information and the second decoded information; reading the first region according to the third read voltage level to obtain a third encoding unit; and Execute a third decoding procedure on the third coding unit. 2. The method for estimating the read voltage level according to claim 1, wherein the block code is composed of a plurality of sub-coding units, and the first bit in these sub-coding units is composed of a plurality of coding programs Decide. 3. The method for estimating the read voltage level according to claim 2, wherein the encoding programs have different encoding directions. 4. The method for estimating the read voltage level according to claim 1, wherein the first decoded information includes a first value, and the second decoded information includes a second value, The step of estimating and obtaining the third reading voltage level according to the first decoding information and the second decoding information includes: The first value is compared with the second value and the third read voltage level is determined according to the comparison result. 5. The method for estimating the reading voltage level according to claim 4, wherein the first value is related to the first decoding result of the first decoding procedure, and the second value is related to the first decoding result. The second decoding result of the second decoding procedure is related. 6. The method for estimating the reading voltage level according to claim 5, wherein the first numerical value is positively related to the number of first successfully decoded units of the first decoding procedure, and the second numerical value is positively related to the number of successful decoding units of the first decoding program. A second number of successfully decoded units related to the second decoding program. 7. The method for estimating the reading voltage level according to claim 6, further comprising: Obtain the number of successfully decoded units in the first row and the number of successfully decoded units in the first column according to the first decoding result; determining the first value according to the number of successfully decoded units in the first row and the number of successfully decoded units in the first column; Obtain the number of successfully decoded units in the second row and the number of successfully decoded units in the second column according to the second decoding result; and The second value is determined according to the number of successfully decoded units in the second row and the number of successfully decoded units in the second column. 8. The method for estimating the read voltage level according to claim 1, wherein the third read voltage level is estimated and obtained according to the first decoded information and the second decoded information The steps include: One of the first read voltage level and the second read voltage level is determined as the third read voltage level. 9. The method for estimating the reading voltage level according to claim 1, further comprising: judging whether the first decoding procedure fails, The step of reading the first area according to the second read voltage level is performed after determining that the first decoding process fails. 10. The read voltage level estimation method according to claim 1, further comprising: performing a preset operation related to the rewritable non-volatile memory module according to the third read voltage level, Wherein the preset operation includes at least one of the following operations: reading the first area to obtain a plurality of soft bits corresponding to a third decoding unit and performing iterative decoding on the third decoding unit according to the soft bits; determining the degree of wear of a plurality of memory cells in the first region or the voltage distribution state of the memory cells; and A preset programming voltage corresponding to the first region is determined. 11. The read voltage level estimation method according to claim 1, wherein both the first decoding process and the second decoding process are hard bit mode decoding. 12. A memory storage device, comprising: connecting the interface unit for electrically connecting to the host system; a rewritable non-volatile memory module; and a memory control circuit unit electrically connected to the connection interface unit and the rewritable non-volatile memory module, Wherein the memory control circuit unit is used to send a first read instruction sequence, wherein the first read instruction sequence is used to instruct to read the rewritable non-volatile memory according to a first read voltage level the first area in the module to obtain the first coding unit, wherein the first coding unit belongs to the block code, Wherein the memory control circuit unit is further configured to execute a first decoding program on the first encoding unit and record first decoding information, Wherein the memory control circuit unit is further used to send a second read instruction sequence, wherein the second read instruction sequence is used to instruct to read the first area according to the second read voltage level, so as to obtain the second read instruction sequence. two coding units, wherein the second coding unit belongs to the block code, Wherein the memory control circuit unit is further configured to execute a second decoding program on the second encoding unit and record second decoding information, Wherein the memory control circuit unit is further configured to estimate and obtain a third read voltage level according to the first decoded information and the second decoded information, The memory control circuit unit is further configured to send a third read command sequence, wherein the third read command sequence is used to instruct to read the first area according to the third read voltage level, to obtain the third coding unit, Wherein the memory control circuit unit is further configured to execute a third decoding program on the third encoding unit. 13. The memory storage device according to claim 12, wherein the block code is composed of a plurality of sub-coding units, and the first bit in the sub-coding units is determined by a plurality of coding procedures. 14. The memory storage device according to claim 13, wherein the encoding programs have different encoding directions. 15. The memory storage device of claim 12, wherein the first decoded information includes a first value, the second decoded information includes a second value, The operation of the memory control circuit unit estimating and obtaining the third read voltage level according to the first decoding information and the second decoding information includes: The first value is compared with the second value and the third read voltage level is determined according to the comparison result. 16. The memory storage device according to claim 15, wherein the first numerical value is related to the first decoding result of the first decoding procedure, and the second numerical value is related to the first decoding result of the second decoding procedure. The second decoding result is related. 17. The memory storage device according to claim 16, wherein the first numerical value is positively related to the first number of successfully decoded units of the first decoding program, and the second numerical value is positively related to the first number of successfully decoded units of the first decoding program. The second decoding success unit number of the second decoding program. 18. The memory storage device according to claim 17, wherein the memory control circuit unit is further configured to obtain the number of successfully decoded units in the first row and the number of successfully decoded units in the first column according to the first decoding result, Wherein the memory control circuit unit is further configured to determine the first value according to the number of successfully decoded units in the first row and the number of successfully decoded units in the first column, Wherein the memory control circuit unit is also used to obtain the number of successfully decoded units in the second row and the number of successfully decoded units in the second column according to the second decoding result, The memory control circuit unit is further configured to determine the second value according to the number of successfully decoded units in the second row and the number of successfully decoded units in the second column. 19. The memory storage device according to claim 12, wherein the memory control circuit unit estimates and obtains the third read voltage level according to the first decoded information and the second decoded information Bit operations include: One of the first read voltage level and the second read voltage level is determined as the third read voltage level. 20. The memory storage device according to claim 12, wherein the memory control circuit unit is further configured to determine whether the first decoding procedure fails, The operation of sending the second read instruction sequence by the memory control circuit unit is performed after determining that the first decoding procedure fails. 21. The memory storage device according to claim 12, wherein the memory control circuit unit is further configured to execute the rewritable non-volatile memory module according to the third read voltage level the default action concerned, Wherein the preset operation includes at least one of the following operations: instructing to read the first area to obtain a plurality of soft bits corresponding to a third decoding unit and perform iterative decoding on the third decoding unit according to the soft bits; determining the degree of wear of a plurality of memory cells in the first region or the voltage distribution state of the memory cells; and A preset programming voltage corresponding to the first region is determined. 22. The memory storage device according to claim 12, wherein both the first decoding process and the second decoding process are hard bit mode decoding. 23. A memory control circuit unit, characterized in that it is used to control a rewritable non-volatile memory module, the memory control circuit unit comprising: a host interface for electrically connecting to a host system; a memory interface for electrically connecting to the rewritable non-volatile memory module; error checking and correction circuitry; and a memory management circuit electrically connected to the host interface, the memory interface and the error checking and correction circuit, Wherein the memory management circuit is used to send a first read instruction sequence, wherein the first read instruction sequence is used to instruct to read the rewritable non-volatile memory module according to a first read voltage level in the first region to obtain the first coding unit, wherein the first coding unit belongs to the block code, wherein the error checking and correction circuit is used to execute a first decoding procedure on the first encoding unit, and the memory management circuit is also used to record first decoding information, Wherein the memory management circuit is further used to send a second read instruction sequence, wherein the second read instruction sequence is used to instruct to read the first area according to the second read voltage level to obtain the second a coding unit, wherein said second coding unit belongs to said block code, Wherein the error checking and correction circuit is also used to execute a second decoding program on the second encoding unit, and the memory management circuit is also used to record the second decoding information, Wherein the memory management circuit is further configured to estimate and obtain a third read voltage level according to the first decoded information and the second decoded information, Wherein the memory management circuit is further used to send a third read instruction sequence, wherein the third read instruction sequence is used to instruct to read the first area according to the third read voltage level to obtain third coding unit, Wherein the error checking and correcting circuit is further used for executing a third decoding procedure on the third coding unit. 24. The memory control circuit unit according to claim 23, wherein the block code is composed of a plurality of sub-coding units, and the first bit in the sub-coding units is determined by a plurality of coding procedures. 25. The memory control circuit unit according to claim 24, wherein the encoding programs have different encoding directions. 26. The memory control circuit unit according to claim 23, wherein the first decoded information includes a first value, the second decoded information includes a second value, The operation of the memory management circuit estimating and obtaining the third read voltage level according to the first decoded information and the second decoded information includes: The first value is compared with the second value and the third read voltage level is determined according to the comparison result. 27. The memory control circuit unit according to claim 26, wherein the first numerical value is related to the first decoding result of the first decoding program, and the second numerical value is related to the first decoding result of the second decoding program. The second decoding result is related. 28. The memory control circuit unit according to claim 27, wherein the first value is positively related to the number of first decoding success units of the first decoding program, and the second value is positively related to the The second number of successfully decoded units of the second decoding procedure. 29. The memory control circuit unit according to claim 28, wherein the memory management circuit is further configured to obtain the number of successfully decoded cells in the first row and the number of successfully decoded cells in the first column according to the first decoding result, Wherein the memory management circuit is further configured to determine the first value according to the number of successfully decoded units in the first row and the number of successfully decoded units in the first column, Wherein the memory management circuit is also used to obtain the number of successfully decoded units in the second row and the number of successfully decoded units in the second column according to the second decoding result, The memory management circuit is further configured to determine the second value according to the number of successfully decoded units in the second row and the number of successfully decoded units in the second column. 30. The memory control circuit unit according to claim 23, wherein the memory management circuit estimates and obtains the third read voltage standard according to the first decoded information and the second decoded information Bit operations include: One of the first read voltage level and the second read voltage level is determined as the third read voltage level. 31. The memory control circuit unit according to claim 23, wherein the memory management circuit is further configured to determine whether the first decoding procedure fails, The operation of sending the second read instruction sequence by the memory management circuit is performed after determining that the first decoding procedure fails. 32. The memory control circuit unit according to claim 23, wherein the memory management circuit is further configured to perform communication with the rewritable non-volatile memory module according to the third read voltage level the default action concerned, Wherein the preset operation includes at least one of the following operations: Instructing to read the first area to obtain a plurality of soft bits corresponding to the third decoding unit and the error checking and correction circuit is further configured to perform iterative decoding on the third decoding unit according to the soft bits; determining the degree of wear of a plurality of memory cells in the first region or the voltage distribution state of the memory cells; and A preset programming voltage corresponding to the first region is determined. 33. The memory control circuit unit according to claim 23, wherein both the first decoding process and the second decoding process are hard bit mode decoding.