CN112634972B - Voltage identification method, memory control circuit unit, and memory storage device - Google Patents

Abstract

The invention provides a voltage identification method, a memory control circuit unit and a memory storage device. The method comprises the following steps: reading the first memory cell according to a first read voltage group of the plurality of read voltage groups and performing a first decoding operation to generate first verification information; identifying a plurality of second read voltage sets corresponding to the first interval in the plurality of read voltage sets according to the first interval in which the first verification information is located in the plurality of intervals; the first memory cell is read using a third read voltage set of the second read voltage sets and a first decoding operation is performed.

Description

Voltage identification method, memory control circuit unit, and memory storage device

technical field

The invention relates to a voltage identification method, a memory control circuit unit and a memory storage device.

Background technique

Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Since the rewritable non-volatile memory module (such as flash memory) has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, it is very suitable for being built in various portable devices such as the above examples. in the multimedia device.

Generally speaking, when reading data from the rewritable non-volatile memory module, the memory management circuit can first perform a hard bit pattern decoding operation to decode to obtain the data to be read. When performing the decoding operation of the hard bit pattern, the read voltage can be used to read the memory cell and perform decoding. If the decoding fails, the memory management circuit will obtain another read voltage again, and use the another read voltage to read the aforementioned memory cells for re-decoding. If the decoding fails again and the number of times to re-acquire the read voltage does not exceed the default number of times, the memory management circuit will re-acquire other voltages, and read the aforementioned memory cells according to the re-acquired read voltage to re-decode. code. When the number of executions of the step of re-obtaining the read voltage exceeds the default number of times, the memory management circuit may instead perform other decoding operations (eg, soft bit pattern decoding operations).

In particular, the aforementioned preset number of times is usually "the number of all read voltages available to be retrieved", and this number is usually large and will cause other decode operations to be performed instead (e.g., soft bit pattern decoding). It takes a lot of time to perform the operation of reacquiring the read voltage to perform the read and decode operation. Therefore, how to quickly determine which read voltages will fail to decode and avoid using these read voltages for reading to reduce the running time of the hard bit pattern decoding operation is one of the problems that those skilled in the art want to solve. .

Contents of the invention

The present invention provides a voltage identification method, a memory control circuit unit, and a memory storage device, which can quickly determine which read voltages will fail to decode and avoid using these read voltages for reading to reduce hard bit pattern decoding operations running time.

The present invention proposes a voltage identification method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of storage units, and the method includes: according to a plurality of read voltages The first read voltage group in the group reads a plurality of first memory cells in the plurality of memory cells and performs a first decoding operation to generate first verification information; according to the plurality of intervals (interval) The first interval where the first verification information is located, identifying a plurality of second read voltage groups corresponding to the first interval among the plurality of read voltage groups; and using the plurality of second read voltage groups A third read voltage set in the set reads the plurality of first memory cells and performs the first decode operation.

In an embodiment of the present invention, the step of identifying the plurality of second read voltage groups corresponding to the first interval in the plurality of read voltage groups includes: according to the The first section where the first verification information is located identifies a plurality of fourth read voltage groups that are not used to read the plurality of first memory cells among the plurality of read voltage groups.

In an embodiment of the present invention, read the plurality of first memory cells in the plurality of memory cells according to the first read voltage group in the plurality of read voltage groups and execute the Before the first decoding operation to generate the first verification information, the method further includes: storing a verification information lookup table for each of the plurality of read voltage groups, wherein the The verification information lookup table is used to record the plurality of first read voltage groups in the plurality of read voltage groups corresponding to each of the plurality of intervals of the read voltage group to which the verification information lookup table belongs. A type of read voltage group and a plurality of second type of read voltage groups.

In an embodiment of the present invention, the check information lookup table is used to record a bit sequence corresponding to each of the plurality of intervals, and in the bit sequence corresponding to the plurality of first types A plurality of bits of the read voltage group are respectively set to a first bit value, and a plurality of bits corresponding to the plurality of second type read voltage groups in the bit sequence are respectively set to a second bit value.

In an embodiment of the present invention, at least one of the plurality of first-type read voltage groups is used to perform a read operation, and the plurality of second-type read voltage groups are not used for The read operation is performed.

In an embodiment of the present invention, the step of identifying the plurality of second read voltage groups corresponding to the first interval among the plurality of read voltage groups includes: from the first read voltage group Obtain the first bit sequence corresponding to the first interval from the check information lookup table, and identify the multiple bits according to a plurality of bits in the first bit sequence set as the first bit value A second read voltage group.

In an embodiment of the present invention, using the third read voltage group in the plurality of second read voltage groups to read the plurality of first memory cells and perform the first decoding operation The steps include: reading the plurality of first memory cells using the third read voltage group of the plurality of second read voltage groups and performing the first decoding operation to generate second verification information ; According to the second interval in which the second verification information is located in the plurality of intervals, obtain the second interval corresponding to the second interval from the verification information lookup table of the third read voltage group A two-bit sequence; performing a logical operation on the first bit sequence and the second bit sequence to obtain a third bit sequence; identifying a plurality of fifth in the plurality of read voltage groups according to the third bit sequence Read voltage groups, wherein the value of the bit corresponding to each of the plurality of fifth read voltage groups in the third bit sequence is the second bit value, and the plurality of fifth read voltage groups A fifth read voltage group will not be used to read the plurality of first memory cells; and using other read voltages in the plurality of read voltage groups other than the plurality of fifth read voltage groups A group reads the plurality of first memory cells.

The present invention proposes a memory control circuit unit for a rewritable non-volatile memory module, the rewritable non-volatile memory module includes a plurality of storage units, the memory control circuit unit includes a host interface, a memory interface and memory management circuitry. The host interface is used to electrically connect to the host system. The memory interface is used to electrically connect to the rewritable non-volatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used to perform the following operations: read a plurality of first memory cells in the plurality of memory cells according to a first read voltage group in the plurality of read voltage groups and perform a first decoding operation to generate First verification information; according to the first interval in which the first verification information is located in a plurality of intervals (intervals), identify a plurality of second reading voltage groups corresponding to the first interval in the plurality of read voltage groups a read voltage set; and read the plurality of first memory cells and perform the first decoding operation using a third read voltage set of the plurality of second read voltage sets.

In an embodiment of the present invention, during the operation of identifying the plurality of second read voltage groups corresponding to the first interval among the plurality of read voltage groups, the memory management circuit is further used to According to the first interval in which the first verification information is located in the plurality of intervals, identify a plurality of read voltage groups that are not used to read the plurality of first memory cells A fourth read voltage set.

In an embodiment of the present invention, after reading the plurality of first memory cells in the plurality of memory cells according to the first read voltage group in the plurality of read voltage groups and executing the Before the first decoding operation to generate the first verification information, the memory management circuit is also used to store a verification information lookup table for each of the plurality of read voltage groups . Wherein the verification information lookup table is used to record the plurality of read voltage groups corresponding to each of the plurality of intervals of the read voltage group to which the verification information lookup table belongs A first type of read voltage group and a plurality of second type of read voltage groups.

In an embodiment of the present invention, the check information lookup table is used to record a bit sequence corresponding to each of the plurality of intervals, and in the bit sequence corresponding to the plurality of first types A plurality of bits of the read voltage group are respectively set to a first bit value, and a plurality of bits corresponding to the plurality of second type read voltage groups in the bit sequence are respectively set to a second bit value.

In an embodiment of the present invention, at least one of the plurality of first-type read voltage groups is used to perform a read operation, and the plurality of second-type read voltage groups are not used for The read operation is performed.

In an embodiment of the present invention, during the operation of identifying the plurality of second read voltage groups corresponding to the first interval among the plurality of read voltage groups, the memory management circuit is further used to Obtain a first bit sequence corresponding to the first interval from the check information lookup table of the first read voltage group, and set it as the first bit according to the first bit sequence The plurality of bits of the value identify the plurality of second read voltage groups.

In an embodiment of the present invention, after using the third read voltage group in the plurality of second read voltage groups to read the plurality of first memory cells and perform the first decoding operation In operation, the memory management circuit is further configured to perform the following operations: use the third read voltage group in the plurality of second read voltage groups to read the plurality of first memory cells and execute The first decoding operation is to generate second verification information; according to the second interval in which the second verification information is located in the plurality of intervals, the verification from the third read voltage group obtaining a second bit sequence corresponding to the second interval in the information lookup table; performing a logical operation on the first bit sequence and the second bit sequence to obtain a third bit sequence; identifying according to the third bit sequence A plurality of fifth read voltage groups among the plurality of read voltage groups, wherein each of the plurality of fifth read voltage groups corresponds to a bit in the third bit sequence The value of is the second bit value, and the plurality of fifth read voltage groups will not be used to read the plurality of first memory cells; and using the plurality of read voltage groups described in The plurality of first memory cells are read by other read voltage groups than the plurality of fifth read voltage groups.

The present invention provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to electrically connect to the host system. A rewritable nonvolatile memory module has a plurality of storage cells. The memory control circuit unit is used to electrically connect to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to perform the following operations: read a plurality of first memory cells in the plurality of memory cells according to a first read voltage group in the plurality of read voltage groups and perform a first decoding operation to generating first verification information; identifying a plurality of first intervals corresponding to the first interval in the plurality of read voltage groups according to the first interval in which the first verification information is located in the plurality of intervals (intervals) two sets of read voltages; and using a third set of read voltages in the plurality of second read voltage sets to read the plurality of first memory cells and perform the first decoding operation.

In an embodiment of the present invention, in the operation of identifying the plurality of second read voltage groups corresponding to the first interval among the plurality of read voltage groups, the memory control circuit unit further uses to identify, according to the first interval in which the first verification information is located in the plurality of intervals, which of the plurality of read voltage groups is not used to read the plurality of first memory cells A fourth read voltage group.

In an embodiment of the present invention, after reading the plurality of first memory cells in the plurality of memory cells according to the first read voltage group in the plurality of read voltage groups and executing the Before the operation of the first decoding operation to generate the first verification information, the memory control circuit unit is also used to store the verification information lookup for each of the plurality of read voltage groups surface. Wherein the verification information lookup table is used to record the plurality of read voltage groups corresponding to each of the plurality of intervals of the read voltage group to which the verification information lookup table belongs A first type of read voltage group and a plurality of second type of read voltage groups.

In an embodiment of the present invention, the check information lookup table is used to record a bit sequence corresponding to each of the plurality of intervals, and in the bit sequence corresponding to the plurality of first types A plurality of bits of the read voltage group are respectively set to a first bit value, and a plurality of bits corresponding to the plurality of second type read voltage groups in the bit sequence are respectively set to a second bit value.

In an embodiment of the present invention, at least one of the plurality of first-type read voltage groups is used to perform a read operation, and the plurality of second-type read voltage groups are not used for The read operation is performed.

In an embodiment of the present invention, in the operation of identifying the plurality of second read voltage groups corresponding to the first interval among the plurality of read voltage groups, the memory control circuit unit further uses Obtaining a first bit sequence corresponding to the first interval from the check information lookup table of the first read voltage group, and setting it as the first bit sequence according to the first bit sequence A plurality of bits of the bit value identify the plurality of second read voltage groups.

In an embodiment of the present invention, after using the third read voltage group in the plurality of second read voltage groups to read the plurality of first memory cells and perform the first decoding operation In the operation, the memory control circuit unit is further configured to perform the following operation: use the third read voltage group in the plurality of second read voltage groups to read the plurality of first memory cells and performing the first decoding operation to generate second verification information; according to the second interval in which the second verification information is located in the plurality of intervals, from the calibration of the third read voltage group Obtain the second bit sequence corresponding to the second interval in the verification information lookup table; perform logical operations on the first bit sequence and the second bit sequence to obtain a third bit sequence; according to the third bit sequence identifying a plurality of fifth read voltage groups of the plurality of read voltage groups, wherein each of the plurality of fifth read voltage groups corresponds to a The value of the bit is the second bit value, and the plurality of fifth read voltage groups will not be used to read the plurality of first memory cells; and using all of the plurality of read voltage groups The plurality of first memory cells are read by other read voltage groups other than the plurality of fifth read voltage groups.

Based on the above, the voltage identification method, the memory control circuit unit and the memory storage device of the present invention can quickly determine which read voltage groups may fail to decode, and avoid using these read voltage groups to perform the reading of the memory cells. Reduced runtime of hard bit pattern decode operations.

Description of drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the present invention.

FIG. 2 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the present invention.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an exemplary embodiment.

FIG. 6 is a schematic diagram of a memory cell array according to an exemplary embodiment.

FIG. 7 is a graph showing statistical distribution of gate voltages corresponding to written data stored in a memory cell array according to an exemplary embodiment.

FIG. 8 is a schematic diagram of a programmed memory cell according to an exemplary embodiment.

Fig. 9 is a schematic diagram of reading data from a storage unit according to an exemplary embodiment.

Fig. 10 is a schematic diagram of reading data from a storage unit according to another exemplary embodiment.

FIG. 11 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

FIG. 12 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment.

FIG. 13 is a diagram illustrating hard bit pattern decoding according to an exemplary embodiment.

Fig. 14 is a schematic diagram showing a check information lookup table according to an exemplary embodiment.

FIG. 15 is a diagram illustrating logical operations performed on bit sequences according to an exemplary embodiment.

FIG. 16 is a flowchart illustrating a voltage identification method according to an exemplary embodiment.

Explanation of reference signs:

10, 30: memory storage device;

11, 31: host system;

110: system bus;

111: processor;

112: random access memory;

113: read-only memory;

114: data transmission interface;

12: input/output (I/O) device;

20: main board;

201: U disk;

202: memory card;

203: solid state drive;

204: wireless memory storage device;

205: a global positioning system module;

206: network adapter;

207: wireless transmission device;

208: keyboard;

209: screen;

210: Horn;

32: SD card;

33: CF card;

34: embedded storage device;

341: embedded multimedia card;

342: Embedded multi-chip packaging storage device;

402: connect the interface unit;

404: memory control circuit unit;

406: a rewritable non-volatile memory module;

2202: storage unit array;

2204: word line control circuit;

2206: bit line control circuit;

2208: row decoder;

2210: data input/output buffer;

2212: control circuit;

502: storage unit;

504: bit line;

506: word line;

508: shared source line;

512: select the gate-drain transistor;

514: select the gate source transistor;

VA, VB, VC, VD, VE, VF, VG: read voltage;

400(0)～400(N): Entity erasing unit;

702: memory management circuit;

704: host interface;

706: memory interface;

708: error checking and correction circuit;

710: buffer memory;

712: power management circuit;

1410, 1420: distribution;

1430: area;

1440~1444: read voltage;

SI_0～SI_2: Interval;

T0～T15: read the voltage group;

1400: Check the information lookup table;

IBS, BS1~BS2, NBS1~NBS2, NBSn: bit sequence;

Step S1601: a step of reading a first memory cell according to a first read voltage group in multiple read voltage groups and performing a first decoding operation to generate first verification information;

Step S1603: According to the first interval where the first verification information is located in the plurality of intervals, the step of identifying multiple second read voltage groups corresponding to the first interval among the aforementioned multiple read voltage groups;

Step S1605: a step of reading the first memory cell by using the third read voltage group in the second read voltage group and performing the first decoding operation.

Detailed ways

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also called a control circuit). Typically memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the present invention.

Referring to FIG. 1 and FIG. 2 , the host system 11 generally includes a processor 111 , a random access memory (random access memory, RAM) 112 , a read only memory (ROM) 113 and a data transmission interface 114 . The processor 111 , random access memory 112 , ROM 113 and data transmission interface 114 are all electrically connected to a system bus 110 .

In this exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114 . For example, the host system 11 can store data into the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114 . In addition, the host system 11 is electrically connected to the I/O device 12 through the system bus 110 . For example, host system 11 may transmit output signals to or receive input signals from I/O devices 12 via system bus 110 .

In this exemplary embodiment, the processor 111 , the random access memory 112 , the read-only memory 113 and the data transmission interface 114 can be disposed on the motherboard 20 of the host system 11 . The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114 , the motherboard 20 can be electrically connected to the memory storage device 10 via wire or wirelessly. The memory storage device 10 can be, for example, a USB flash drive 201 , a memory card 202 , a solid state drive (Solid State Drive, SSD) 203 or a wireless memory storage device 204 . The wireless memory storage device 204 can be, for example, a near field communication (Near Field Communication, NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device or a Bluetooth low energy memory storage device (for example, iBeacon ) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be electrically connected to various I/Os such as a Global Positioning System (GPS) module 205, a network adapter 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207 .

In an example embodiment, reference to a host system is substantially any system that can cooperate with a memory storage device to store data. Although in the above exemplary embodiments, the host system is described as a computer system, however, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. Please refer to FIG. 3 , in another exemplary embodiment, the host system 31 can also be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 can be used for it. SD card 32, CF card 33 or embedded storage device 34 and other non-volatile memory storage devices. The embedded storage device 34 includes various types of substrates such as an embedded multimedia card (embedded MMC, eMMC) 341 and/or an embedded multi-chip package storage device (embedded Multi Chip Package, eMCP) 342, etc., directly electrically connecting the memory module to the host system. embedded storage on the .

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

Referring to FIG. 4 , the memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a device conforming to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 Standard, high-speed peripheral component connection interface (Peripheral Component Interconnect Express, PCI Express) standard, Universal Serial Bus (Universal Serial Bus, USB) standard, Secure Digital (SecureDigital, SD) interface standard, Ultra High Speed-I , UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, memory stick (Memory Stick, MS) interface standard, multi-chip package (Multi-Chip Package) interface standard, multimedia Memory card (Multi Media Card, MMC) interface standard, embedded multimedia memory card (Embedded Multimedia Card, eMMC) interface standard, universal flash memory (Universal Flash Storage, UFS) interface standard, embedded multi-chip package (embedded Multi Chip Package, eMCP) ) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 402 can be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 can be arranged outside the chip including the memory control circuit unit 404 .

The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and write and read data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11. Fetch and erase operations.

The rewritable non-volatile memory module 406 is electrically connected to the memory control circuit unit 404 and used for storing data written by the host system 11 . The rewritable non-volatile memory module 406 can be a single-level storage unit (Single Level Cell, SLC) NAND flash memory module (that is, a flash memory module that can store 1 bit in a storage unit), a second-level storage unit (Multi Level Cell, MLC) NAND flash memory module (that is, a flash memory module that can store 2 bits in a storage unit), multi-level storage unit (Triple Level Cell, TLC) NAND flash memory module (that is, a storage unit that can store 3-bit flash module), other flash modules, or other memory modules with the same characteristics.

The storage units in the rewritable non-volatile memory module 406 are arranged in an array. The storage unit array is described below as a two-dimensional array. However, it should be noted that the following exemplary embodiment is only an example of the storage unit array, and in other exemplary embodiments, the configuration of the storage unit array can be adjusted to meet practical requirements.

FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an exemplary embodiment. FIG. 6 is a schematic diagram of a memory cell array according to an exemplary embodiment.

Please refer to FIG. 5 and FIG. 6 at the same time, the rewritable non-volatile memory module 406 includes a memory cell array 2202, a word line control circuit 2204, a bit line control circuit 2206, a row decoder (column decoder) 2208, a data input/ The output buffer 2210 and the control circuit 2212 .

In this exemplary embodiment, the memory cell array 2202 may include a plurality of memory cells 502 for storing data, a plurality of select gate drain (SGD) transistors 512 and a plurality of select gate sources (select gate source, SGS) transistor 514, and a plurality of bit lines 504, a plurality of word lines 506, and a shared source line 508 connected to these memory cells (as shown in FIG. 6). The memory cells 502 are arranged in an array (or in a three-dimensional stack) at intersections of the bit lines 504 and the word lines 506 . When receiving a write instruction or a read instruction from the memory control circuit unit 404, the control circuit 2212 will control the word line control circuit 2204, the bit line control circuit 2206, the row decoder 2208, and the data input/output buffer 2210 to write Entering data into the memory cell array 2202 or reading data from the memory cell array 2202, wherein the word line control circuit 2204 is used to control the voltage applied to the word line 506, and the bit line control circuit 2206 is used to control the voltage applied to the bit line 504 The row decoder 2208 selects the corresponding bit line according to the column address in the instruction, and the data input/output buffer 2210 is used for temporarily storing data.

The storage cells in the rewritable non-volatile memory module 406 store multiple bits by changing the threshold voltage. Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This process of changing the threshold voltage is also called "writing data into the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the memory cell array 2202 has multiple storage states. And by reading the voltage, it can be judged which storage state the memory cell belongs to, so as to obtain the bit stored in the memory cell.

FIG. 7 is a graph showing statistical distribution of gate voltages corresponding to written data stored in a memory cell array according to an exemplary embodiment.

Please refer to Figure 7, taking MLC NAND flash memory as an example, with different threshold voltages, each memory cell has 4 storage states, and these storage states represent "11", "10", "00" and "01" and so on. In other words, each storage state includes a least significant bit (Least Significant Bit, LSB) and a most significant bit (Most Significant Bit, MSB). In this exemplary embodiment, the first bit from the left in the storage states (i.e., "11", "10", "00" and "01") is the LSB, and the bit from the left 2 bits are MSB. Therefore, in this example embodiment, each memory cell can store 2 bits. It should be understood that the threshold voltage and its storage state correspondence shown in FIG. 8 is just an example. In another exemplary embodiment of the present invention, the correspondence between the threshold voltage and the storage state can also be arranged in "11", "10", "01" and "00" as the threshold voltage increases, or other arrangements. In addition, in another example, the first bit from the left can also be defined as the MSB, and the second bit from the left can be defined as the LSB.

FIG. 8 is a schematic diagram of a programmed memory cell according to an exemplary embodiment.

Referring to FIG. 8 , in this exemplary embodiment, the programming of the memory cells is accomplished by pulse write/verify threshold voltage method. Specifically, when data is to be written into the storage unit, the memory control circuit unit 404 will set the initial write voltage and write pulse time, and instruct the control circuit 2212 of the rewritable non-volatile memory module 406 to use the The memory cell is programmed with the set initial write voltage and write pulse time to write data. Afterwards, the memory control circuit unit 404 will apply a verification voltage to the control gate to determine whether the memory cell is turned on, and then determine whether the memory cell is in the correct storage state (with the correct threshold voltage). If the memory cell is not programmed to the correct storage state, the memory control circuit unit 404 instructs the control circuit 2212 to adjust with the currently applied write voltage plus an incremental step pulse program (Incremental-step-pulse programming, ISPP) value as the new write voltage and program the memory cell again according to the new write voltage and write pulse time. Conversely, if the memory cell has been programmed to a correct storage state, it means that the data has been correctly written into the memory cell. For example, the initial write voltage will be set to 16 volts (Voltage, V), the write pulse time will be set to 18 microseconds (microseconds, μs) and the incremental step pulse program adjustment value will be set to 0.6 V, but the present invention is not limited thereto.

FIG. 9 is a schematic diagram of reading data from a storage unit according to an exemplary embodiment, which takes MLCNAND flash memory as an example.

Please refer to FIG. 9 , the read operation of the memory cells of the memory cell array 2202 is to identify the data stored in the memory cells by applying the read voltage to the control gate and through the conduction state of the memory cells. The verification bit (VA) is used to indicate whether the memory cell is turned on when the read voltage VA is applied; the verification bit (VC) is used to indicate whether the memory cell is turned on when the read voltage VC is applied; the verification bit (VB ) is used to indicate whether the memory cell is turned on when the read voltage VB is applied. Here, it is assumed that when the verification bit is "1", it means that the corresponding memory cell is turned on, and when the verification bit is "0", it means that the corresponding memory cell is not turned on. As shown in FIG. 9 , the storage state of the storage unit can be determined through the verification bits (VA)˜(VC), and then the stored bits can be obtained.

Fig. 10 is a schematic diagram of reading data from a storage unit according to another exemplary embodiment.

Please refer to Figure 10, taking TLC NAND flash memory as an example, each storage state includes the least significant bit LSB of the first bit from the left, the middle significant bit (Center Significant bit) of the second bit from the left Bit, CSB) and the most significant bit MSB of the third bit from the left. In this example, according to different threshold voltages, the memory cell has 8 storage states (i.e., "111", "110", "100", "101", "001", "000", "010" and " 011"). By applying read voltages VA˜VG to the control gates, the bits stored in the memory cells can be identified.

FIG. 11 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

Please refer to FIG. 11, the storage unit 502 of the rewritable non-volatile memory module 406 will constitute a plurality of physical programming units, and these physical programming units will constitute a plurality of physical erasing units 400(0)-400( N). Specifically, the storage units on the same character line will form one or more physical programming units. If each storage unit can store more than 2 bits, the physical programming units on the same character line can be classified into lower physical programming units and upper physical programming units. For example, the LSB of each storage unit belongs to the lower physical programming unit, and the MSB of each storage unit belongs to the upper physical programming unit. In this exemplary embodiment, the entity programming unit is the smallest unit of programming. That is, the entity programming unit is the smallest unit for writing data. For example, the entity programming unit is an entity page or an entity sector. If the physical programming unit is a physical page, each physical programming unit usually includes a data bit area and a redundant bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (eg, error correction code). In this exemplary embodiment, each data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the present invention does not limit the size and number of physical sectors. On the other hand, the entity erasing unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased. For example, the physical erasing unit is a physical block.

FIG. 12 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment. It must be understood that the structure of the memory control circuit unit shown in FIG. 12 is just an example, and the present invention is not limited thereto.

Referring to FIG. 12 , the memory control circuit unit 404 includes a memory management circuit 702 , a host interface 704 , a memory interface 706 and an error checking and correction circuit 708 .

The memory management circuit 702 is used to control the overall operation of the memory control circuit unit 404 . Specifically, the memory management circuit 702 has a plurality of control instructions, and when the memory storage device 10 is operating, these control instructions will be executed to perform operations such as writing, reading, and erasing data. When describing the operation of the memory management circuit 702 or any circuit components included in the memory control circuit unit 404 , it is equivalent to describing the operation of the memory control circuit unit 404 .

In this exemplary embodiment, the control commands of the memory management circuit 702 are implemented in the form of firmware. For example, the memory management circuit 702 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are written into the read-only memory. When the memory storage device 10 is in operation, these control instructions will be executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 702 may also be stored in a specific area of the rewritable non-volatile memory module 406 in the form of program code (for example, a system area dedicated to storing system data in the memory module) middle. In addition, the memory management circuit 702 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to store in the rewritable non-volatile memory module The control instructions in 406 are loaded into the random access memory of the memory management circuit 702 . Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 702 can also be implemented in hardware. For example, the memory management circuit 702 includes a microcontroller, a memory unit management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit and a data processing circuit. The storage unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The storage unit management circuit is used for managing the storage units or groups thereof of the rewritable non-volatile memory module 406 . The memory writing circuit is used to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406 . The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406 . The memory erasing circuit is used for issuing an erase command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406 . The data processing circuit is used for processing data to be written into the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406 . The write command sequence, the read command sequence and the erase command sequence may respectively include one or more program codes or scripts and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding write, read and Erase etc. In an exemplary embodiment, the memory management circuit 702 can also issue other types of instruction sequences to the rewritable non-volatile memory module 406 to instruct to perform corresponding operations.

The host interface 704 is electrically connected to the memory management circuit 702 and used for receiving and identifying commands and data transmitted by the host system 11 . That is to say, the commands and data sent by the host system 11 are sent to the memory management circuit 702 through the host interface 704 . In this exemplary embodiment, the host interface 704 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 704 may also be compatible with PATA standard, IEEE 1394 standard, PCIExpress standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 706 is electrically connected to the memory management circuit 702 and used for accessing the rewritable non-volatile memory module 406 . That is to say, the data to be written into the rewritable nonvolatile memory module 406 will be converted into a format acceptable to the rewritable nonvolatile memory module 406 via the memory interface 706 . Specifically, if the memory management circuit 702 wants to access the rewritable non-volatile memory module 406, the memory interface 706 will transmit the corresponding instruction sequence. For example, these command sequences may include a write command sequence for writing data, a read command sequence for reading data, an erase command sequence for erasing data, and instructions for various memory operations such as changing the read the corresponding sequence of instructions to fetch voltage levels or execute garbage collection routines, etc.). These instruction sequences are, for example, generated by the memory management circuit 702 and transmitted to the rewritable non-volatile memory module 406 through the memory interface 706 . These command sequences may include one or more signals, or data on a bus. These signals or data may include script or program code. For example, in the read command sequence, information such as read identification code and memory address will be included.

The error checking and correcting circuit 708 is electrically connected to the memory management circuit 702 and used for executing error checking and correcting procedures to ensure the correctness of data. Specifically, when the memory management circuit 702 receives a write command from the host system 11, the error checking and correction circuit 708 will generate a corresponding error correcting code (ECC code) for the data corresponding to the write command or error checking code (error detecting code, EDC), and the memory management circuit 702 will write the data corresponding to the write command and the corresponding error correction code or error checking code into the rewritable non-volatile memory module 406 . Afterwards, when the memory management circuit 702 reads data from the rewritable non-volatile memory module 406, it will read the error correction code or error check code corresponding to the data at the same time, and the error check and correction circuit 708 will base on this error Correction code or error checking code performs error checking and correction procedures on the read data.

In an exemplary embodiment of the present invention, the memory control circuit unit 404 further includes a buffer memory 710 and a power management circuit 712 . The buffer memory 710 is electrically connected to the memory management circuit 702 and used for temporarily storing data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406 . The power management circuit 712 is electrically connected to the memory management circuit 702 and used for controlling the power of the memory storage device 100 .

FIG. 13 is a diagram illustrating hard bit pattern decoding according to an exemplary embodiment.

Please refer to FIG. 13 , taking the SLC flash memory as an example here, the distribution 1410 and the distribution 1420 are used to represent the storage states of a plurality of first storage units, and the distributions 1410 and 1420 respectively represent different storage states. These first storage units may belong to the same physical programming unit or different physical programming units, and the present invention is not limited thereto. It is assumed here that when a memory unit belongs to the distribution 1410 , the memory unit stores a bit “1”; when the memory unit belongs to the distribution 1420 , the memory unit stores a bit “0”. When the memory management circuit 702 reads the memory cell with the read voltage 1440 , the memory management circuit 702 obtains a verification bit, which is used to indicate whether the memory cell is turned on. It is assumed here that the verification bit is “1” when the memory cell is turned on, and “0” otherwise, but the present invention is not limited thereto. If the verification bit is “1”, the memory management circuit 702 will determine that the storage unit belongs to the distribution 1410 , otherwise it is the distribution 1420 . However, distribution 1410 and distribution 1420 overlap in region 1430 . That is, there are several storage units that should belong to distribution 1410 but are identified as distribution 1420 , and there are several storage units that should belong to distribution 1420 but are identified as distribution 1410 .

In this exemplary embodiment, when these first memory cells are to be read, the memory management circuit 702 will first select a read voltage (eg, read voltage 1441) to read these first memory cells to obtain the first memory cells verification bit. The error checking and correction circuit 708 performs a decoding operation including a probabilistic decoding algorithm (also referred to as a first decoding operation) according to the verification bit of the first storage unit to generate a plurality of decoding bits, and these decoding bits can form a codeword.

In this exemplary embodiment, the probabilistic decoding algorithm takes the possible decoding result of a symbol (symbol) as a candidate (candidate), and the information input in the decoding process or the value of the intermediate operation process is based on these candidates The probability value of a person or the ratio of the probability among candidates is expressed to determine which one is the most likely candidate. For example, if a symbol has two candidates (bits 0 and 1), the probabilistic decoding algorithm calculates the most likely candidate with a probability of 0 or 1 occurring, respectively, or with a probability between 0 and 1 ratio to calculate the most likely candidates. If there are N candidates, for example, the possible values in a finite field (Finite Field) are 0 to N-1 (N is a positive integer, and each candidate represents multiple bits), then the probabilistic decoding algorithm is calculated separately The probability of N candidates to determine the most likely candidate, or use the probability of one of the values as the denominator to calculate the relative probability ratio to determine the most likely candidate. In an exemplary embodiment, the ratio of the above probabilities may also be expressed in logarithmic form.

In this exemplary embodiment, the probabilistic decoding algorithm may be convolutional code, turbo code, low-density parity-check code (low-density parity-check code) or other algorithms with probabilistic decoding characteristics . For example, in convolutional codes and turbo codes, a finite state machine (finite state machine) can be used for encoding and decoding, and in this exemplary embodiment, the most probable multiple states are calculated according to the verification bits, thereby generating decoding bits. The following will take the low density parity check code as an example for description.

If the low density parity check code is used, when performing the first decoding operation according to the verification bit, the memory management circuit 702 also obtains the decoding initial value of each storage unit according to each verification bit. For example, if the verification bit is "1", the memory management circuit 702 will set the initial decoding value of the corresponding storage unit to n; if the verification bit is "0", the initial decoding value is -n. Where n is a positive number, but the present invention does not limit the value of the positive integer n. In one embodiment, n is 8, for example.

Next, the ECC circuit 708 performs iterative decoding of the LDPC algorithm according to the decoding initial values to generate a codeword comprising a plurality of decoded bits. In iterative decoding, these decoding initial values are constantly updated to represent a probability value, and this probability value is also called reliability (reliability) or confidence (belief). The updated decoded initial value will be converted into a plurality of decoded bits, and the error checking and correcting circuit 708 will regard these decoded bits as a vector, and compare this vector with the parity check matrix (parity check matrix) of the LDPC algorithm -checkmatrix) do matrix multiplication of module 2 to obtain multiple syndromes. These syndromes can be used to judge whether a codeword composed of decoded bits is a valid codeword. If the codeword composed of decoded bits is a valid codeword, the iterative decoding stops, and the error checking and correction circuit 708 outputs the codeword composed of these decoded bits. If the decoded byte becomes an invalid codeword, the decoding initial value will continue to be updated and a new decoded bit will be generated for the next iteration. When the number of iterations reaches the preset number of iterations, iterative decoding will stop. The ECC circuit 708 uses the decoded bits generated in the last iteration to determine whether the decoding is successful. For example, if it is judged according to the syndrome that the decoded byte generated in the last iteration is a valid codeword, then the decoding is successful; if the first decoded byte is an invalid codeword, it means that the decoding fails.

In another exemplary embodiment, the probabilistic decoding algorithms included in the decoding operation are convolutional codes and turbo codes, and other error correction codes are also included in the decoding operation. For example, convolutional codes and turbo codes can be used with parity codes of any algorithm. After the decoding part of the convolutional code or the turbo code is executed in the decoding operation, the parity code can be used to judge whether the codeword composed of the generated decoding bits is a valid codeword, and then judge whether the decoding is successful.

No matter what kind of error correction code is used, if the decoding fails, it means that the first storage units store uncorrectable error bits. If the decoding fails, the memory management circuit 702 will obtain another read voltage again, and use the other read voltage (for example, the read voltage 1442 ) to read the first memory cells, so as to obtain the verification bits of the memory cells again. The memory management circuit 702 performs the above-mentioned first decoding operation according to the retrieved verification bits to obtain another codeword formed from a plurality of decoded bytes. In an exemplary embodiment, the ECC circuit 708 judges whether the other codeword is a valid codeword according to the syndrome corresponding to the other codeword. If the other codeword is not a valid codeword, the memory management circuit 702 will judge that the decoding fails. If the times of re-obtaining the read voltage does not exceed the default times, the memory management circuit 702 will re-acquire other voltages (for example, the read voltage 1443), and read the first memory cell according to the re-acquired read voltage 1443, to retrieve the verification bits and perform the first decoding operation.

In other words, when there is an uncorrectable error bit, by re-acquiring the read voltage, the verify bit of some memory cells will be changed, thereby changing several probability values in the probabilistic decoding algorithm, thereby changing the decoding operation decoding result. Logically speaking, the above-mentioned action of reacquiring the read voltage is to flip several bits in a codeword and re-decode the new codeword. In some cases, codewords that could not be decoded (with uncorrectable error bits) before flipping may be decodable after flipping. Moreover, in an exemplary embodiment, the memory management circuit 702 will try decoding several times until the number of attempts exceeds a preset number. However, the present invention does not limit the number of preset times.

It should be noted that although the above-mentioned Retry-Read mechanism is to obtain a read voltage again, the present invention is not limited thereto. In an embodiment applied to MLC or TLC flash memory, the re-read mechanism is used to obtain a set of read voltages, and use multiple read voltages in this set of read voltages to read the memory cell and perform the first decoding operation . In more detail, the memory management circuit 702 pre-configures a default read voltage set and multiple re-read voltage sets for re-reading. When reading the first storage unit for the first time, the memory management circuit 702 may use multiple read voltages in the above-mentioned default read voltage group to read the first storage unit to perform a hard bit pattern decoding operation. When using the first voltage in the default read voltage group to read the first memory cell but a decoding failure occurs, the memory management circuit 702 can execute a re-read mechanism to select one of the above-mentioned re-read voltage groups to Perform the first refetch and perform the hard bit pattern decode operation. When a decoding failure occurs during the first re-read process, the memory management circuit 702 may perform a second re-read. For example, the memory management circuit 702 may select another read voltage group from the above-mentioned re-read voltage group to read the first memory cell and perform a hard bit pattern decoding operation. It should be noted that although the above embodiment only performs two re-read operations, the present invention is not intended to limit the number of re-read operations. In addition, the present invention does not limit the use of SLC, MLC or TLC flash memory. It should be noted that although the foregoing examples describe that the read voltage set includes a plurality of read voltages, the present invention is not intended to limit the number of read voltages in the read voltage set. In other embodiments, the read voltage group may only include one read voltage.

In the exemplary embodiment of FIG. 13 , the decoded initial value of the memory cell is divided into two values (eg, n and -n) according to a verification bit. Iterative decoding performed according to two values is also called hard bit mode iterative decoding. However, the above steps of changing the read voltage can also be applied to iterative decoding of soft bit mode, wherein the decoding initial value of each memory cell is determined according to a plurality of verification bits. It is worth noting that, whether it is a hard bit pattern or a soft bit pattern, the probability value of the bit is calculated in iterative decoding, so it belongs to the probability decoding algorithm.

Based on the above, when reading data from the rewritable non-volatile memory module 406 , the memory management circuit 702 will first perform a hard bit pattern decoding operation to decode to obtain the data to be read. When performing the decoding operation of the hard bit pattern, the read voltage group can be used to read the memory cell and perform decoding. If the decoding fails and the number of times to re-acquire the read voltage group does not exceed the default number of times, the memory management circuit 702 will re-acquire other obtained voltage groups, and read the aforementioned memory cells according to the re-acquired read voltage group to re-acquire decoding. When the number of executions of the step of re-acquiring the read voltage group exceeds the default number of times, the memory management circuit 702 may instead perform other decoding operations (eg, soft bit pattern decoding operations).

In particular, the aforementioned preset number of times is usually "the number of all read voltage groups available for retrieval", and this number is usually large in MLC or TLC flash memory and causes other decoding operations to be performed instead. (For example, soft bit pattern decoding operation) It takes a lot of time to perform the operation of re-acquiring the read voltage set to perform the reading and decoding.

Therefore, the present invention proposes a voltage identification method, which can quickly determine which read voltage groups may fail to decode, and avoid using these read voltage groups to perform reading of memory cells to reduce hard bit pattern decoding operations running time.

In detail, in this embodiment, the memory management circuit 702 stores a corresponding check information lookup table for each read voltage group. For example, FIG. 14 is a schematic diagram showing a check information lookup table according to an exemplary embodiment.

Referring to FIG. 14 , it is assumed that in this embodiment, the memory management circuit 702 is configured with read voltage groups T0 - T15 . For each read voltage group in the read voltage groups T0 - T15 , the memory management circuit 702 pre-stores a corresponding check information lookup table. Taking the reading voltage group T0 as an example, it is assumed that the verification information lookup table 1400 in FIG. 14 is a verification information lookup table corresponding to the reading voltage group T0. In the verification information lookup table 1400 , the relationship between each of the multiple intervals SI_0 - SI_2 and the aforementioned read voltage groups T0 - T15 can be recorded.

It should be noted here that each of the intervals SI_0˜SI_2 is used to represent the range of the parity information (eg, the aforementioned syndrome). For example, interval SI_0 indicates that the syndrome value is less than or equal to 600; interval SI_1 indicates that the syndrome value is greater than 600 and less than 800; interval SI_2 indicates that the syndrome value is greater than or equal to 800. However, the present invention is not intended to limit the number of the foregoing intervals and the numerical range of each interval.

In particular, for each interval in SI_0˜SI_2, the check information lookup table 1400 will store a corresponding bit sequence, and a plurality of bits in the bit sequence will correspond to the read voltage groups T0˜T15 respectively. Taking the interval SI_0 in the check information lookup table 1400 as an example, the bit sequence of the interval SI_0 is "0110111111111101". Wherein, the first bit corresponds to the read voltage group T0, the second bit corresponds to the read voltage group T1, the third bit corresponds to the read voltage group T2, and so on. And the read voltage group whose bit value is set to 1 (also referred to as the first bit value) can be called "the first type of read voltage group", and the bit value is set to 0 (also referred to as, The read voltage group of the second digit value) may also be referred to as "the second type of read voltage group". In this embodiment, the "first type of read voltage group" represents the read voltage group that can be used to retrieve in the re-read mechanism, and these read voltage groups can have a higher probability of successful decoding The read data (that is, the probability of decoding failure is less than the threshold value), so the first type of read voltage group can be used to perform the read operation. The "second type of read voltage group" represents the read voltage group that will not be used for re-acquisition in the re-read mechanism, and these read voltage groups have a higher probability of decoding failure (e.g., decoding failure occurs The probability is greater than the aforementioned threshold value), so the second type of read voltage group will not be used to perform the read operation.

It should be noted here that, the bits in the bit sequence of each interval need to be set to 0 or 1, which can be determined by reading the voltage distribution diagram, through statistical or experimental methods. Taking the verification information lookup table 1400 of the read voltage group T0 as an example, in the bit sequence of the interval SI_0, the read voltage groups T3 and T14 corresponding to the bit whose bit value is set to 0 are shown in the read voltage distribution diagram The distance from the read voltage group T0 is far (for example, the distance is greater than the threshold value), and reading with the read voltage groups T3 and T14 has a higher probability of decoding failure, so the bit sequence of the interval SI_0 can be Bits (that is, the 4th and 15th bits) corresponding to the read voltage groups T3 and T14 are set to 0. In addition, in the reading voltage distribution diagram, since the reading voltage groups other than the reading voltage group T3 and T14 are closer to the reading voltage group T0, it means that these reading voltage groups have a higher probability of successfully translating Therefore, bits corresponding to other read voltage groups other than the read voltage group T3 and T14 are set to 1. In addition, since the verification information lookup table 1400 is a verification information lookup table of the read voltage group T0, the value corresponding to the read voltage group T0 is set to 0 to avoid repeated use in the re-read mechanism Read voltage group T0.

Although the foregoing example is described by taking the interval SI_0 in the verification information lookup table 1400 as an example, a similar method can also be applied to the intervals SI_1 and SI_2 in the verification information lookup table 1400 . In addition, for each read voltage group in the read voltage groups T0 - T15 , the memory management circuit 702 stores a check information lookup table similar to the check information check table 1400 .

Afterwards, when the memory management circuit 702 reads a plurality of first storage units in the rewritable non-volatile memory module 406 for the first time, it is assumed that the memory management circuit 702 first uses the read voltage group T0 (also referred to as the first A read voltage set) to read the first memory cells and perform a first decoding operation to generate a syndrome (also referred to as first check information). Afterwards, the memory management circuit 702 will use the first verification information to determine whether the decoding is successful (that is, whether the codeword composed of decoded bits is a valid codeword).

When the first check information is used to determine that the decoding fails (that is, the codeword composed of decoded bits is not a valid codeword), a re-reading mechanism will be executed. In more detail, assuming that the value of the first check information is 400 (that is, the value of the syndrome is 400), the memory management circuit 702 will determine that the first check information is located in the interval SI_0 in the check information lookup table 1400 (Also known as, first interval). The memory management circuit 702 obtains the bit sequence (also referred to as the first bit sequence) corresponding to the interval SI_0 from the parity information lookup table 1400 . In particular, since it is the first time to read the first storage unit, in this embodiment, the memory management circuit 702 will first generate an initial bit sequence IBS with the same length as the first bit sequence, and each of the initial bit sequence IBS All bits are 1. Next, the memory management circuit 702 performs logic operations on the initial bit sequence IBS and the first bit sequence, such as an AND (AND) operation.

For example, FIG. 15 is a diagram illustrating logical operations performed on bit sequences according to an exemplary embodiment.

Referring to FIG. 15 , after obtaining the first bit sequence BS1 , the memory management circuit 702 performs a logic operation on the initial bit sequence IBS and the first bit sequence BS1 to obtain the bit sequence NBS1 . In particular, since each bit of the initial bit sequence IBS is 1, the value of each bit of the bit sequence NBS1 is the same as that of the first bit sequence BS1. Afterwards, the memory management circuit 702 will identify the read voltage groups T1-T2, T4-T13 and T15 (collectively referred to as the second read voltage group) corresponding to the bits set to 1 in the bit sequence NBS1 as being re- The reading mechanism can be used to read the reading voltage group of the first memory cell; in addition, the memory management circuit 702 will set the reading voltage group T0, T3 corresponding to the bit set to 0 in the bit sequence NBS1 and T14 (collectively, the fourth set of read voltages) identifies the set of read voltages that will not be used to read the first memory cell in the re-read mechanism.

Assume that the memory management circuit 702 selects the read voltage set T1 (also referred to as the third read voltage set) from the read voltage sets T1 - T2 , T4 - T13 and T15 for re-reading the first memory cell. The first memory cell is read again using the read voltage set T1 and the first decoding operation is performed to generate a syndrome (also referred to as second verification information). The memory management circuit 702 will use the second verification information to determine whether the decoding is successful (that is, whether the codeword composed of decoded bits is a valid codeword).

When the second check information is used to determine that the decoding fails (that is, the codeword composed of decoded bits is not a valid codeword), the re-reading mechanism will be executed again. In more detail, assuming that the value of the second verification information is 700 (that is, the value of the syndrome is 700), the memory management circuit 702 will determine that the second verification information is the verification information located in the read voltage group T1 Interval SI_1 (also referred to as second interval) in a lookup table (not shown). The memory management circuit 702 obtains the bit sequence BS2 (also referred to as the second bit sequence) corresponding to the interval SI_1 from the check information lookup table of the read voltage group T1. Next, the memory management circuit 702 performs logic operations on the bit sequence NBS1 (which is the same as the bit sequence BS1 ) and the bit sequence BS2 to obtain the bit sequence NBS2 (also referred to as the third bit sequence) as shown in FIG. 15 . In the example of FIG. 15 , since the bit sequence NBS1 is “011011111111101” and the bit sequence BS2 is “1000111000010101”, the bit sequence NBS2 of “0000111000010101” can be obtained after logical operation of the two.

Afterwards, the memory management circuit 702 will identify the read voltage groups T4˜T6, T11, T13 and T15 corresponding to the bits set to 1 in the bit sequence NBS2 as being available for reading the first A read voltage group of a memory cell; in addition, the memory management circuit 702 will set the read voltage groups T0-T3, T7-T10, T12 and T14 (collectively referred to as, A fifth set of read voltages) is identified as the set of read voltages that will not be used to read the first memory cell in the re-read mechanism. Afterwards, the memory management circuit 702 can use one of the read voltage groups T4 - T6 , T11 , T13 and T15 to read the aforementioned first memory cell.

In the aforementioned re-reading mechanism, a logical operation of the bit sequence may be performed when the decoding fails to select a read voltage group for re-reading according to the bit sequence obtained after the logical operation. In particular, when each bit of the bit sequence obtained after the logical operation is 0 (for example, the bit sequence NBSn in FIG. 15 ), it means that the data read by the read voltage groups T0-T15 cannot be successfully read. At this time, the memory management circuit 702 can instead perform other decoding operations (eg, soft bit pattern decoding operations). In particular, when the corresponding bit of a read voltage group in the bit sequence is set to 0, it means that the data read using the read voltage group cannot be successfully decoded, so the memory management circuit 702 The use of the read voltage group can be avoided, thereby reducing the runtime of the hard bit pattern decoding operation.

FIG. 16 is a flowchart illustrating a voltage identification method according to an exemplary embodiment.

Referring to FIG. 16 , in step S1601 , the memory management circuit 702 reads the first memory cell according to the first read voltage group in the plurality of read voltage groups and performs a first decoding operation to generate first verification information. In step S1603, the memory management circuit 702 identifies the plurality of second read voltage groups corresponding to the first interval among the aforementioned plurality of read voltage groups according to the first interval in which the first verification information is located in the plurality of intervals . In step S1605, the memory management circuit 702 reads the first memory cell using the third read voltage set in the second read voltage set and performs a first decoding operation.

To sum up, the voltage identification method, the memory control circuit unit and the memory storage device of the present invention can quickly determine which reading voltage groups may fail to decode, and avoid using these reading voltage groups to perform memory cell reading. Taken to reduce the runtime of hard bit pattern decode operations.

Claims (21)

1. A voltage identification method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, the method comprising:

reading a plurality of first memory cells in the plurality of memory cells according to a first read voltage group in the plurality of read voltage groups and performing a first decoding operation to generate first verification information;

identifying a plurality of second read voltage groups corresponding to a first interval in the plurality of read voltage groups according to the first interval in which the first verification information is located in the plurality of intervals; and

the plurality of first memory cells are read using a third read voltage group of the plurality of second read voltage groups and the first decoding operation is performed.

2. The voltage identification method of claim 1, wherein identifying the plurality of second read voltage groups of the plurality of read voltage groups corresponding to the first interval comprises:

And identifying a plurality of fourth read voltage groups which are not used for reading the plurality of first memory cells in the plurality of read voltage groups according to the first interval in which the first verification information is located in the plurality of intervals.

3. The voltage identification method of claim 1, wherein prior to the step of reading the plurality of first memory cells of the plurality of memory cells according to the first one of the plurality of read voltage groups and performing the first decoding operation to generate the first verification information, the method further comprises:

storing a check information lookup table for each of the plurality of read voltage sets, wherein the check information lookup table is used for recording a plurality of first-type read voltage sets and a plurality of second-type read voltage sets in the plurality of read voltage sets corresponding to each of the plurality of intervals of the read voltage sets to which the check information lookup table belongs.

4. The voltage identification method of claim 3, wherein the check information lookup table is used to record a bit sequence corresponding to each of the plurality of intervals, wherein a plurality of bits corresponding to the plurality of first type read voltage groups are respectively set to a first bit value, and a plurality of bits corresponding to the plurality of second type read voltage groups are respectively set to a second bit value.

5. The voltage identification method of claim 4, wherein at least one of the plurality of first type read voltage sets is used to perform a read operation and the plurality of second type read voltage sets is not used to perform the read operation.

6. The voltage identification method of claim 4, wherein identifying the plurality of second read voltage groups of the plurality of read voltage groups corresponding to the first interval comprises:

a first bit sequence corresponding to the first interval is obtained from the check information lookup table of the first read voltage group, and the plurality of second read voltage groups are identified according to a plurality of bits set to the first bit value in the first bit sequence.

7. The voltage identification method of claim 6, wherein reading the plurality of first memory cells and performing the first decoding operation using the third one of the plurality of second read voltage sets comprises:

reading the plurality of first memory cells using the third read voltage group of the plurality of second read voltage groups and performing the first decoding operation to generate second parity information;

Obtaining a second bit sequence corresponding to a second section from the check information lookup table of the third read voltage group according to the second section in which the second check information is located in the sections;

performing a logical operation on the first bit sequence and the second bit sequence to obtain a third bit sequence;

identifying a plurality of fifth read voltage groups of the plurality of read voltage groups according to the third bit sequence, wherein a value of a bit corresponding to each of the plurality of fifth read voltage groups in the third bit sequence is the second bit value, and the plurality of fifth read voltage groups are not used for reading the plurality of first memory cells; and

and reading the plurality of first memory cells using other read voltage groups than the fifth read voltage groups.

8. A memory control circuit unit for a rewritable nonvolatile memory module including a plurality of memory cells, the memory control circuit unit comprising:

the host interface is used for being electrically connected to a host system;

A memory interface electrically connected to the rewritable non-volatile memory module; and

a memory management circuit electrically connected to the host interface and the memory interface,

wherein the memory management circuit is used for reading a plurality of first memory cells in the plurality of memory cells according to a first read voltage group in a plurality of read voltage groups and performing a first decoding operation to generate first verification information,

wherein the memory management circuit is further configured to identify a plurality of second read voltage sets corresponding to the first interval from the plurality of read voltage sets according to a first interval in which the first verification information is located,

the memory management circuit is also configured to read the plurality of first memory cells using a third read voltage set of the plurality of second read voltage sets and perform the first decoding operation.

9. The memory control circuit unit of claim 8, wherein in operation of identifying the plurality of second read voltage sets of the plurality of read voltage sets corresponding to the first interval,

the memory management circuit is further configured to identify a fourth plurality of read voltage groups of the plurality of read voltage groups that are not used to read the plurality of first memory cells according to the first interval in which the first verification information is located.

10. The memory control circuit unit of claim 8, wherein prior to the operation of reading the plurality of first memory cells of the plurality of memory cells according to the first read voltage group of the plurality of read voltage groups and performing the first decoding operation to generate the first verification information,

the memory management circuit is also configured to store a verification information lookup table for each of the plurality of read voltage sets,

the check information lookup table is used for recording a plurality of first type read voltage groups and a plurality of second type read voltage groups in the plurality of read voltage groups corresponding to each interval in the plurality of intervals, wherein the read voltage groups to which the check information lookup table belongs.

11. The memory control circuit unit of claim 10, wherein the check information lookup table is to record a bit sequence corresponding to each of the plurality of intervals in which a plurality of bits corresponding to the plurality of first type read voltage groups are respectively set to a first bit value and a plurality of bits corresponding to the plurality of second type read voltage groups are respectively set to a second bit value.

12. The memory control circuit unit of claim 11, wherein at least one of the plurality of first type read voltage sets is used to perform a read operation and the plurality of second type read voltage sets is not used to perform the read operation.

13. The memory control circuit unit of claim 11, wherein in operation of identifying the plurality of second read voltage sets of the plurality of read voltage sets corresponding to the first interval,

the memory management circuit is further configured to obtain a first bit sequence corresponding to the first interval from the check information lookup table of the first read voltage group, and identify the plurality of second read voltage groups according to a plurality of bits set to the first bit value in the first bit sequence.

14. The memory control circuit unit of claim 13, wherein in an operation of reading the plurality of first memory cells using the third read voltage group of the plurality of second read voltage groups and performing the first decoding operation,

the memory management circuit is also configured to read the plurality of first memory cells using the third one of the plurality of second read voltage sets and perform the first decoding operation to generate second parity information,

The memory management circuit is further configured to obtain a second bit sequence corresponding to a second interval from the check information lookup table of the third read voltage group according to the second interval in which the second check information is located among the plurality of intervals,

the memory management circuit is also configured to perform a logical operation on the first bit sequence and the second bit sequence to obtain a third bit sequence,

the memory management circuit is further configured to identify a plurality of fifth read voltage sets of the plurality of read voltage sets according to the third bit sequence, wherein a value of a bit corresponding to each of the plurality of fifth read voltage sets in the third bit sequence is the second bit value, and the plurality of fifth read voltage sets are not used to read the plurality of first memory cells,

the memory management circuit is also configured to read the plurality of first memory cells using other read voltage sets of the plurality of read voltage sets than the fifth read voltage set.

15. A memory storage device, comprising:

the connection interface unit is used for being electrically connected to the host system;

a rewritable nonvolatile memory module having a plurality of memory cells; and

A memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is used for reading a plurality of first memory cells in the plurality of memory cells according to a first read voltage group in the plurality of read voltage groups and performing a first decoding operation to generate first verification information,

wherein the memory control circuit unit is further configured to identify a plurality of second read voltage sets corresponding to a first section among the plurality of read voltage sets according to a first section in which the first verification information is located among the plurality of sections,

the memory control circuit unit is also used for reading the plurality of first memory cells by using a third read voltage group in the plurality of second read voltage groups and executing the first decoding operation.

16. The memory storage device of claim 15, wherein in operation of identifying the plurality of second read voltage sets of the plurality of read voltage sets corresponding to the first interval,

the memory control circuit unit is further configured to identify a fourth plurality of read voltage groups of the plurality of read voltage groups that are not used to read the plurality of first memory cells according to the first section in which the first verification information is located.

17. The memory storage device of claim 15, wherein prior to the operation of reading the first ones of the plurality of memory cells according to the first one of the plurality of read voltage sets and performing the first decoding operation to generate the first verification information,

the memory control circuit unit is further configured to store a check information lookup table for each of the plurality of read voltage sets,

the check information lookup table is used for recording a plurality of first type read voltage groups and a plurality of second type read voltage groups in the plurality of read voltage groups corresponding to each interval in the plurality of intervals, wherein the read voltage groups to which the check information lookup table belongs.

18. The memory storage device of claim 17, wherein the check information lookup table is configured to record a bit sequence corresponding to each of the plurality of intervals, wherein a plurality of bits corresponding to the plurality of first type read voltage sets are respectively set to a first bit value in the bit sequence, and wherein a plurality of bits corresponding to the plurality of second type read voltage sets are respectively set to a second bit value in the bit sequence.

19. The memory storage device of claim 18, wherein at least one of the plurality of first-type read voltage sets is used to perform a read operation and the plurality of second-type read voltage sets is not used to perform the read operation.

20. The memory storage device of claim 18, wherein in operation of identifying the plurality of second read voltage sets of the plurality of read voltage sets corresponding to the first interval,

the memory control circuit unit is further configured to obtain a first bit sequence corresponding to the first section from the check information lookup table of the first read voltage group, and identify the plurality of second read voltage groups according to a plurality of bits set to the first bit value in the first bit sequence.

21. The memory storage device of claim 20, wherein in operation of reading the plurality of first memory cells using the third set of read voltages of the plurality of second set of read voltages and performing the first decoding operation,

the memory control circuit unit is also configured to read the plurality of first memory cells using the third read voltage group of the plurality of second read voltage groups and perform the first decoding operation to generate second parity information,

The memory control circuit unit is further configured to obtain a second bit sequence corresponding to a second section from the check information lookup table of the third read voltage group according to the second section in which the second check information is located among the plurality of sections,

the memory control circuit unit is also configured to perform a logical operation on the first bit sequence and the second bit sequence to obtain a third bit sequence,

the memory control circuit unit is further configured to identify a plurality of fifth read voltage sets of the plurality of read voltage sets according to the third bit sequence, wherein a bit value corresponding to each of the plurality of fifth read voltage sets in the third bit sequence is the second bit value, and the plurality of fifth read voltage sets are not used to read the plurality of first memory cells,

the memory control circuit unit is further configured to read the plurality of first memory cells using other read voltage groups than the fifth read voltage groups among the plurality of read voltage groups.