CN105957811A - Method for manufacturing trench gate power devices with shielded gate - Google Patents

Abstract

The invention discloses a method for manufacturing trench gate power devices with shielded gate. The method comprises the following steps: 1) providing a silicon substrate and forming a trench at the bottom of the silicon substrate; 2) forming a first silicon oxide layer and a shielded gate at the bottom of the trench; 3) forming a second silicon oxide layer; 4) depositing a BPSG film and carrying out backflow planarization so as to completely fill in the top of the trench with the BPSG film and the second silicon oxide layer; 5) performing silicon oxide etch-back to form a polysilicon isolation dielectric layer consisting of the BPSG film after etch-back treatment and the second silicon oxide layer; and 6) forming a gate dielectric layer and a polysilicon gate at the top of the trench. With the method of the invention, the size of one unit structure of a device can be reduced for a thin gate dielectric layer so as to reduce the device's conduction voltage drop for low-voltage applications.

Description

Method of manufacturing trench gate power device with shielded gate

technical field

The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a trench gate power device with a shield gate (Shield Gate Trench, SGT).

Background technique

A trench gate power device with a shield gate needs to form a shield gate at the bottom of the trench gate. The shield gate and the trench gate are generally composed of polysilicon, and the shield gate and the trench gate need to be isolated by an isolation dielectric layer between polysilicon . In the existing method, there are two methods for forming the isolation dielectric layer between polysilicon. The first method is to deposit silicon oxide to fill the top of the shield gate after the shield gate is formed. trenches, and then silicon oxide is etched back to form an isolation dielectric layer between polysilicon; the second method is to form an isolation dielectric layer between polysilicon by using a thermal oxidation process, and the isolation dielectric layer between polysilicon and the interpolysilicon isolation dielectric layer on the side of the top trench A gate oxide layer is formed simultaneously by a thermal oxidation process.

As shown in FIG. 1 , it is a schematic structural diagram of a trench gate power device with a shield gate formed by the first existing method; taking an N-type device as an example, a semiconductor substrate such as a silicon substrate 101 is formed on the surface of an N-type semiconductor substrate. N-type epitaxial layer 102, a trench is formed in the N-type epitaxial layer 102 in the gate region, and a shield gate 104 made of polysilicon is formed on the top of the trench, and a dielectric layer such as an oxide layer is isolated between the shield gate 104 and the side of the trench. Silicon layer 103 . After the shielding gate 104 is formed, the HDP CVD process is used to form silicon oxide, densify the silicon oxide, perform chemical mechanical polishing (CMP) and wet etch back to form the isolation dielectric layer 105a between polysilicon; then form a gate dielectric layer such as gate oxide Layer 106 is filled with polysilicon and etched back on top of the trench to form a trench gate, polysilicon gate 107 . After that, it also includes the formation steps of P-type well 108, source region 109 composed of N+ region, interlayer film 110, contact hole 111, well region contact region 112, front metal layer 113, and finally patterning the front metal layer 113 to form the source Pole and Grid.

The advantage of the existing first process method is that the thickness of the inter-polysilicon isolation dielectric layer 105a can be precisely controlled by wet etching back time, and the process window is relatively large. The disadvantage is that the filling of HDP CVD has requirements on the trench aspect ratio, which leads to a relatively large step of the device unit, that is, a relatively large cell pitch, which limits its application in low-voltage MOS transistors. Generally, the conduction region of a device is formed by arranging multiple unit structures. The unit structure includes a trench and the interval between the trenches. The size of a unit, pitch, is the sum of the width of the trench and the pitch of the trench.

As shown in Figure 2, it is a schematic structural diagram of a trench gate power device with a shield gate formed by the second existing method; the difference from the existing first method is only the formation process of the isolation dielectric layer between polysilicon. , in the existing second method: after the shield gate 104 is formed, the inter-polysilicon isolation dielectric layer 105b and the gate oxide layer 106 are simultaneously formed through a thermal oxidation process, and the inter-polysilicon isolation dielectric layer 105b is formed by the polysilicon on the top of the shield gate 104 Formed by oxidation, the gate oxide layer 106 is formed by oxidation of silicon on the sides of the trench. The second process method has simple steps, and forms isolation silicon oxide on polysilicon while growing gate oxide through one oxidation. However, the quality of thermal silicon oxide grown on polysilicon is relatively poor, and a sufficiently thick isolation silicon oxide must be obtained by increasing the thickness of the gate silicon oxide; this will affect the threshold voltage (VT) of the device and the switching process of the unclamped inductive load. switching, UIS) capabilities.

Contents of the invention

The technical problem to be solved by the present invention is to provide a method for manufacturing a trench gate power device with a shielding gate, which can reduce the unit structure size of the device and obtain a thin gate dielectric layer, thereby reducing the conduction voltage drop of the device and realizing low pressure applications.

In order to solve the above-mentioned technical problems, the method for manufacturing a trench gate power device with a shielding gate provided by the present invention includes the following steps:

Step 1, providing a silicon substrate, and performing photolithography to form grooves in the silicon substrate.

Step 2, forming a shielding gate composed of a first polysilicon layer at the bottom of the trench, a first silicon oxide layer is isolated between the shielding gate and the trench side and bottom surface, and the first The surface of the silicon oxide layer is lower than or equal to the surface of the shielding grid.

Step 3: Forming a second silicon oxide layer by using a thermal oxidation process, the second silicon oxide layer is formed on the top surface of the shielding gate and the sides of the trench on the top of the first silicon oxide layer and outside the trench of the silicon substrate surface.

Step 4, depositing a BPSG film and performing reflow planarization on the BPSG film, the planarized BPSG film and the second silicon oxide layer together completely fill the top of the trench; combine the BPSG film and the The second silicon oxide layer fills the trench together to improve the filling capability of the trench and to reduce the size of the trench.

Step 5, performing silicon oxide etching back on the BPSG film and the second silicon oxide layer, and forming an inter-polysilicon isolation dielectric layer from the BPSG film etched back on the silicon oxide layer and the second silicon oxide layer, The inter-polysilicon isolation dielectric layer is located on the top of the shielding gate, and the thickness of the inter-polysilicon isolation dielectric layer is controlled by the silicon oxide etching back process.

Step 6, forming a gate dielectric layer and a polysilicon gate on the top of the trench where the inter-polysilicon isolation dielectric layer is formed, the gate dielectric layer is formed on the side of the top of the trench, and the polysilicon gate connects the trench The top of the slot is completely filled.

A further improvement is that in step 1, a silicon epitaxial layer is formed on the surface of the silicon substrate, and the groove is formed in the silicon epitaxial layer.

A further improvement is that forming the trench in step 1 includes the following sub-steps:

A hard mask layer is formed on the surface of the silicon substrate.

A photoresist pattern formed through a photolithography process defines a trench formation region.

The hard mask layer in the region where the trench is formed is removed by an etching process.

removing the photoresist pattern, and using the etched hard mask layer as a mask to etch the silicon in the formation region of the trench to form the trench.

The hard mask layer is removed.

A further improvement is that the hard mask layer consists of an oxide layer or an oxide layer plus a nitride layer.

A further improvement is that step 2 includes the following sub-steps:

A first silicon oxide layer is formed on side and bottom surfaces of the trench, and the first silicon oxide layer also extends outside the trench.

depositing a first polysilicon layer to completely fill the trench formed with the first silicon oxide layer, the first polysilicon layer also extending to the first silicon oxide layer outside the trench surface.

Etching back the polysilicon, the first polysilicon layer after the etching back of the polysilicon is located at the bottom of the trench and forms the shielding gate.

Etching back the silicon oxide is performed, and after the etching back of the silicon oxide, the first silicon oxide layer is located at the bottom of the trench and realizes the isolation between the shielding gate and the side surface and the bottom surface of the trench.

A further improvement is that step six includes the following sub-steps:

The gate dielectric layer is formed on the side of the top of the trench where the inter-polysilicon isolation dielectric layer is formed, and the gate dielectric layer also extends to the outside of the trench.

A second polysilicon layer is filled on the top of the trench formed with the gate dielectric layer, and the second polysilicon layer also extends to the surface of the gate dielectric layer outside the trench.

Etching back the polysilicon, the second polysilicon layer after the etching back of the polysilicon fills the top of the trench and forms the polysilicon gate.

A further improvement is that the gate dielectric layer is a gate silicon oxide layer.

A further improvement is that after step six, the following steps are also included:

Step 7. Perform ion implantation and thermal annealing process to form a well region in the silicon substrate. The polysilicon gate covers the well region from the side and the surface of the well region covered by the polysilicon gate side is used to form ditch.

Step 8, performing heavily doped source implantation to form a source region on the surface of the well region.

Step 9, forming an interlayer film, a contact hole, and a front metal layer on the front side of the silicon substrate, performing photolithography and etching on the front metal layer to form a source and a gate, and the source passes through the contact hole and the front metal layer. The source region is in contact with the shielding gate, and the gate is in contact with the polysilicon gate through a contact hole.

Step 10, thinning the back of the silicon substrate to form a heavily doped drain region, and forming a back metal layer on the back of the drain region as a drain.

A further improvement is that the trench gate power device is a trench gate power MOSFET device.

A further improvement is that after forming the opening of the contact hole in step 9 and before filling the metal, a step of performing heavy doping implantation at the bottom of the contact hole in contact with the source region to form a well contact region is also included.

The present invention fills the trench at the top of the shield gate by combining the reflowed BPSG film and the second silicon oxide layer formed by the thermal oxidation process, and utilizes the reflow characteristics of the BPSG film to increase the filling capacity of the trench, thereby reducing the size of the trench. That is to say, compared with the existing first method, the present invention has a stronger ability to fill trenches, so it can realize the filling of trenches with smaller widths, and the reduction of the trench width can reduce the overall device unit structure. The size of the device can reduce the pitch, which is beneficial to reduce the conduction voltage drop of the device and realize the application of the device in low voltage.

In addition, the inter-polysilicon isolation dielectric layer of the present invention is obtained after etching back the BPSG film and the second silicon oxide layer, not only the thickness can be precisely controlled, but also the formation process of the inter-polysilicon isolation dielectric layer and the gate dielectric layer are separated, so that Eliminate the negative impact of different thickness requirements between the polysilicon isolation dielectric layer and the gate dielectric layer, and obtain a sufficiently thin gate dielectric layer while obtaining a sufficient thickness of the polysilicon isolation dielectric layer, so that good VT and The UIS capability further benefits the application of the device in low voltage.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention will be described in further detail:

FIG. 1 is a schematic structural view of a trench gate power device with a shield gate formed by the first existing method;

2 is a schematic structural view of a trench gate power device with a shield gate formed by the second existing method;

Fig. 3 is a flow chart of the method of the embodiment of the present invention;

4A-4O are schematic diagrams of device structures in each step of the method of the embodiment of the present invention.

detailed description

As shown in Figure 3, it is a flow chart of the method of the embodiment of the present invention; as shown in Figure 4A to Figure 4O, it is a schematic diagram of the device structure in each step of the method of the embodiment of the present invention. The manufacturing method of the trench gate power device with the shield gate 4 in the embodiment of the present invention includes the following steps:

Step 1, as shown in FIG. 4A , a silicon substrate 1 is provided, and a groove 303 is formed in the silicon substrate 1 by photolithography.

Preferably, a silicon epitaxial layer 2 is formed on the surface of the silicon substrate 1 , and the trench 303 is formed in the silicon epitaxial layer 2 .

Forming the trench 303 includes the following sub-steps:

As shown in FIG. 4B , a hard mask layer 301 is formed on the surface of the silicon substrate 1 . The hard mask layer 301 is composed of an oxide layer or an oxide layer plus a nitride layer.

A photoresist pattern formed through a photolithography process defines a formation area of the trench 303 .

The hard mask layer 301 in the region where the trench 303 is formed is removed by an etching process.

As shown in FIG. 4C , the photoresist 302 pattern is removed. As shown in FIG. 4D , using the etched hard mask layer 301 as a mask, the silicon in the formation region of the trench 303 is etched to form the trench 303 .

As shown in FIG. 4E , the hard mask layer 301 is removed.

Step 2, forming a shielding gate 4 composed of a first polysilicon layer 4 at the bottom of the trench 303, and a first silicon oxide layer is isolated between the shielding gate 4 and the side and bottom surface of the trench 303 3. The surface of the first silicon oxide layer 3 is lower than or equal to the surface of the shielding grid 4 .

Preferably, step two includes the following sub-steps:

As shown in FIG. 4F , a first silicon oxide layer 3 is formed on the side surface and the bottom surface of the trench 303 , and the first silicon oxide layer 3 also extends to the outside of the trench 303 .

As shown in FIG. 4G, depositing the first polysilicon layer 4 will completely fill the trench 303 formed with the first silicon oxide layer 3, and the first polysilicon layer 4 also extends to the trench. The surface of the first silicon oxide layer 3 outside the groove 303 .

As shown in FIG. 4H , polysilicon etch-back is performed, and the first polysilicon layer 4 after polysilicon etching-back is located at the bottom of the trench 303 and forms the shielding gate 4 .

As shown in FIG. 4H, silicon oxide etch back is performed, and after the silicon oxide is etched back, the first silicon oxide layer 3 is located at the bottom of the trench 303 and realizes the shielding gate 4 and the side and bottom surfaces of the trench 303 isolated between.

Step 3, as shown in FIG. 4I, a second silicon oxide layer 5a is formed by using a thermal oxidation process, and the second silicon oxide layer 5a is formed on the top surface of the shielding grid 4 and the top of the first silicon oxide layer 3. The side surfaces of the trench 303 and the surface of the silicon substrate 1 outside the trench 303 .

Step 4, as shown in FIG. 4J, depositing a BPSG film 5b; as shown in FIG. 4K, performing reflow planarization on the BPSG film 5b, and the planarized BPSG film 5b is together with the second silicon oxide layer 5a Fill the top of the trench 303 completely; fill the trench 303 together with the BPSG film 5b and the second silicon oxide layer 5a to improve the filling capability of the trench 303 and to shrink the trench 303 size of. That is to say, the embodiment of the present invention can reduce the size of the cell of the device, that is, reduce the pitch, so that it can be suitable for implementing low-voltage applications of the device.

Step 5, as shown in FIG. 4L, perform silicon oxide etching back on the BPSG film 5b and the second silicon oxide layer 5a, and the BPSG film 5b and the second oxide layer after etching back from the silicon oxide The silicon layer 5a forms an inter-polysilicon isolation dielectric layer, the inter-polysilicon isolation dielectric layer is located on the top of the shield gate 4 and the thickness of the inter-polysilicon isolation dielectric layer is controlled by the silicon oxide etching back process.

Step 6, forming a gate dielectric layer 6 and a polysilicon gate 7 on the top of the trench 303 where the inter-polysilicon isolation dielectric layer is formed, the gate dielectric layer 6 is formed on the side of the top of the trench 303, and the polysilicon The gate 7 completely fills the top of the trench 303 .

Preferably, step six includes the following sub-steps:

As shown in FIG. 4M , the gate dielectric layer 6 is formed on the side of the top of the trench 303 where the inter-polysilicon isolation dielectric layer is formed, and the gate dielectric layer 6 also extends to the outside of the trench 303 . The gate dielectric layer 6 is a gate silicon oxide layer.

As shown in FIG. 4N, the second polysilicon layer 7 is filled on the top of the trench 303 formed with the gate dielectric layer 6, and the second polysilicon layer 7 also extends to the outside of the trench 303. the surface of the gate dielectric layer 6;

As shown in FIG. 4N , the polysilicon is etched back, and the second polysilicon layer 7 after the polysilicon is etched back fills the top of the trench 303 and forms the polysilicon gate 7 .

Step 7, as shown in FIG. 4N, perform ion implantation and thermal annealing process to form a well region 8 in the silicon substrate 1, the polysilicon gate 7 covers the well region 8 from the side and is covered by the polysilicon gate 7 The surface of the well region 8 covered by the sides is used to form a channel.

Step 8, as shown in FIG. 4N , perform heavily doped source implantation to form a source region 9 on the surface of the well region 8 .

Step 9, as shown in FIG. 4N, forming an interlayer film 10, a contact hole 11, and a front metal layer 13 on the front side of the silicon substrate 1, and performing photolithography on the front metal layer 13 to form a source and a gate , the source is in contact with the source region 9 and the shielding gate 4 through the contact hole 11 , and the gate is in contact with the polysilicon gate 7 through the contact hole 11 .

After the opening of the contact hole 11 is formed and before metal filling, a step of performing heavy doping implantation at the bottom of the contact hole 11 in contact with the source region 9 to form a well contact region 12 is also included.

The trench gate power device of the embodiment of the present invention is a trench gate power MOSFET device, and further includes:

Step 10, thinning the back of the silicon substrate 1 to form a heavily doped drain region, and forming a back metal layer on the back of the drain region as a drain.

When the trench gate power device in the embodiment of the present invention is an N-type device, the silicon substrate 1, the silicon epitaxial layer 2, the source region 9 and the drain region are all N-type doped, and the The well region 8 is a P well. When the trench gate power device in the embodiment of the present invention is a P-type device, the silicon substrate 1, the silicon epitaxial layer 2, the source region 9 and the drain region are all P-type doped, and the Well region 8 is an N well.

The method of the embodiment of the present invention can simultaneously break through the pitch limitation of silicon oxide formed by HDPCVD as the isolation medium and the gate oxide thickness limitation of thermal oxygen as the isolation medium; thus, the unit size of the device can be reduced, for example, a 1.2 μm pitch can be produced, Devices below the gate oxide thickness; thus, it is possible to make low-voltage and low-power separated gate power MOS transistors, that is, trench gate power MOS devices with shielded gates. At present, most of the split-gate power MOS transistors on the market are used for more than 30V applications, and the 20V split-gate power MOS transistors can be fabricated by adopting the method of the embodiment of the present invention.

The present invention has been described in detail through specific examples above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (10)

1. A method for manufacturing a trench gate power device with a shielding grid, characterized in that it may further comprise the steps: Step 1, providing a silicon substrate, performing photolithography and etching to form grooves in the silicon substrate; Step 2, forming a shielding gate composed of a first polysilicon layer at the bottom of the trench, a first silicon oxide layer is isolated between the shielding gate and the trench side and bottom surface, and the first The surface of the silicon oxide layer is lower than or equal to the surface of the shielding grid; Step 3: Forming a second silicon oxide layer by using a thermal oxidation process, the second silicon oxide layer is formed on the top surface of the shielding gate and the sides of the trench on the top of the first silicon oxide layer and outside the trench The surface of the silicon substrate; Step 4, depositing a BPSG film and performing reflow planarization on the BPSG film, the planarized BPSG film and the second silicon oxide layer together completely fill the top of the trench; combine the BPSG film and the Filling the trench with the second silicon oxide layer to improve the filling capability of the trench and reduce the size of the trench; Step 5, performing silicon oxide etching back on the BPSG film and the second silicon oxide layer, and forming an inter-polysilicon isolation dielectric layer from the BPSG film etched back on the silicon oxide layer and the second silicon oxide layer, The inter-polysilicon isolation dielectric layer is located on the top of the shielding gate and the thickness of the inter-polysilicon isolation dielectric layer is controlled by the silicon oxide etching back process; Step 6, forming a gate dielectric layer and a polysilicon gate on the top of the trench where the inter-polysilicon isolation dielectric layer is formed, the gate dielectric layer is formed on the side of the top of the trench, and the polysilicon gate connects the trench The top of the slot is completely filled. 2. The manufacturing method of a trench gate power device with a shield gate as claimed in claim 1, characterized in that: in step 1, a silicon epitaxial layer is formed on the surface of the silicon substrate, and the trench is formed on the in the silicon epitaxial layer. 3. The manufacturing method of a trench-gate power device with a shielded gate as claimed in claim 1 or 2, characterized in that: forming the trench in step 1 includes the following sub-steps: forming a hard mask layer on the surface of the silicon substrate; The photoresist pattern formed by the photolithography process defines the formation area of the trench; removing the hard mask layer in the region where the trench is formed by using an etching process; removing the photoresist pattern, and using the etched hard mask layer as a mask to etch the silicon in the formation region of the trench to form the trench; The hard mask layer is removed. 4 . The method for manufacturing a trench gate power device with a shield gate according to claim 3 , wherein the hard mask layer is composed of an oxide layer or an oxide layer plus a nitride layer. 5. The method for manufacturing a trench gate power device with a shielded gate as claimed in claim 1, wherein step 2 includes the following sub-steps: forming a first silicon oxide layer on the side and bottom surfaces of the trench, the first silicon oxide layer also extending to the outside of the trench; depositing a first polysilicon layer to completely fill the trench formed with the first silicon oxide layer, the first polysilicon layer also extending to the first silicon oxide layer outside the trench surface; Performing polysilicon etching back, the first polysilicon layer after polysilicon etching back is located at the bottom of the trench and forms the shielding gate; Etching back the silicon oxide is performed, and after the etching back of the silicon oxide, the first silicon oxide layer is located at the bottom of the trench and realizes the isolation between the shielding gate and the side surface and the bottom surface of the trench. 6. The method for manufacturing a trench gate power device with a shielded gate as claimed in claim 1, wherein step six includes the following sub-steps: forming the gate dielectric layer on the side of the top of the trench where the inter-polysilicon isolation dielectric layer is formed, and the gate dielectric layer also extends to the outside of the trench; filling a second polysilicon layer on the top of the trench formed with the gate dielectric layer, and the second polysilicon layer also extends to the surface of the gate dielectric layer outside the trench; Etching back the polysilicon, the second polysilicon layer after the etching back of the polysilicon fills the top of the trench and forms the polysilicon gate. 7. The manufacturing method of a trench-gate power device with a shielded gate according to claim 1 or 6, wherein the gate dielectric layer is a gate silicon oxide layer. 8. The manufacturing method of a trench gate power device with a shielded gate as claimed in claim 1, characterized in that: after step six, further comprising the following steps: Step 7. Perform ion implantation and thermal annealing process to form a well region in the silicon substrate, the polysilicon gate covers the well region from the side and the surface of the well region covered by the polysilicon gate side is used to form ditch; Step 8, performing heavily doped source implantation to form a source region on the surface of the well region; Step 9, forming an interlayer film, a contact hole, and a front metal layer on the front side of the silicon substrate, performing photolithography and etching on the front metal layer to form a source and a gate, and the source passes through the contact hole and the front metal layer. The source region is in contact with the shielded gate, and the gate is in contact with the polysilicon gate through a contact hole; Step 10, thinning the back of the silicon substrate to form a heavily doped drain region, and forming a back metal layer on the back of the drain region as a drain. 9 . The method for manufacturing a trench gate power device with a shielded gate according to claim 8 , wherein the trench gate power device is a trench gate power MOSFET device. 10. The manufacturing method of a trench gate power device with a shielded gate according to claim 8, characterized in that: after the opening of the contact hole in step 9 is formed and before the metal filling, it also includes The step of performing heavy doping implantation on the bottom of the contact hole in contact with each other to form a well contact region.