CN105812062A

CN105812062A - MLD interface adapting method and system of optical transport network

Info

Publication number: CN105812062A
Application number: CN201610124011.XA
Authority: CN
Inventors: 魏明
Original assignee: Fiberhome Telecommunication Technologies Co Ltd
Current assignee: Fiberhome Telecommunication Technologies Co Ltd
Priority date: 2016-03-04
Filing date: 2016-03-04
Publication date: 2016-07-27
Anticipated expiration: 2036-03-04
Also published as: CN105812062B

Abstract

The invention discloses an MLD (Multiple Lane Distribution) interface adapting method and system of an optical transport network. The system includes a bit_demux module demultiplexing physical lanes to logical lanes; an ll_align module obtaining FP through implementing detection of frame positioning bytes of the logical lanes, and outputting channel data and alarm signals after frame synchronization, wherein the frame synchronization is implemented by a standard frame synchronization state machine; an llm_recovery module implementing recovery and ranking of logical channel numbers, wherein the recovery process is implemented by a standard recovery state machine; a deskew_pro module composed of a deskew_ctrl sub module and a correction FIFO sub module and performing delayed alignment treatment of the logical channels according to the FP; and an ll_mux module implementing data frame re-organization after data alignment in the logical channels. According to the invention, read operation of a lane correction FIFO is controlled according to the extracted and recovered FP and logical lane number, so that a problem of multiple lane data delayed correction in 100G MLC interface transmission is solved.

Description

Optical transfer network MLD method for interface adaptation and system

Technical field

The present invention relates to technical field of optical network communication, be specifically related to optical transfer network MLD method for interface adaptation and system.

Background technology

Along with the enforcement that " broadband China light net city " plans, and the powerful driving of the novel bandwidth applications such as mobile Internet, Internet of Things and cloud computing, in the urgent need to transmitting network, there is higher capacity.The explosive growth of the brought packet stream amount of cloud service, domestic broadband and wireless backhaul is promoting a new round for operator to invest, and supports that 100G network transmits with dilatation optical transport network.

Multichannel distribution (MLD) is the core mechanism that 100G technology realizes, MLD is based on inverse multiplexing technology, high speed signal is distributed into several low speed signals at transmitting terminal and carries out multi-channel parallel transmission, and each passage has the calibration mark of self.High-speed data-flow is carried out multichannel distribution, reduces the speed of each passage, thus reducing requirement and the implementation complexity of interface-clock-frequency.

Fig. 1 is 100GOTU4 frame MLD mode；As it is shown in figure 1,100GOTU4 frame data are divided into 1020 groups based on 16 byte modes, then in loop distribution to 20 logical channel (logicallanes, LL).Every OTU4 frame boundaries, channel allocation rotates；For the distribution of OTU4 to 20 logical channel, the 3rd OA2 byte on OTU4 frame is defined as logical channel labelling (LLM), LLM value with continuous OTU4 frame successively from 0 to 239 be incremented by add 1；Logical channel number (LCN) is to be obtained by LLM modulus 20 (LLMmod20) computing.

At present, logical channel, for different physical channel quantity, is carried out bit multiplexing by 100GOTN.20 tunnel logical channels are multiplexed into 10 physical channels, tunnel (OTL4.10) by 2:1 bit multiplexer, or it is multiplexed into 4 physical channels, tunnel (OTL4.4) by 5:1 bit multiplexer, 100GOTN transmits system and constitutes two kinds of multichannel physical light interfaces of 4 × 28G and 10 × 11G, wave division multiplex mode is adopted at photosphere, multiple physical light path are transmitted in an optical fiber, the speed of single optical channel is reduced to 28G and 11G from 100G, substantially increase the customer side optical interface tolerance limit to chromatic dispersion and polarization mode dispersion (PMD), this be changed to network application provide more motility, and reduce network cost.But bring problems with:

MLD processing mode, while reducing high-speed data intractability, also brings multi-channel data time delay correction problem.Each physical channel parallel data is after different wavelength and line transmission process, and between passage, inevitably dislocation and time delay, causes existing between logical channel delay deviation, cannot revert to initial data when data receiver.

In view of this, it is badly in need of providing one to eliminate interchannel delay inequality, it is achieved multi-channel data aligns, it is achieved channel data restructuring reverts to the system and method for initial data.

Summary of the invention

The technical problem to be solved be data in different wavelength and line transmission process, exist dislocation and time delay, cause existing between logical channel delay deviation, the problem that initial data cannot be reverted to when data receiver.

In order to solve above-mentioned technical problem, the technical solution adopted in the present invention there is provided a kind of optical transfer network MLD interface adaption system, including:

Bit_demux module: for physical channel bit is demultiplexed into logical channel；

Ll_align module: for the detection of the frame alignment byte of completion logic passage, obtains FP mark, and exports the channel data after framing and alarm indication signal, and framing completes by the framing state machine of standard；

Llm_recovery module: for recovery and the sequence of completion logic channel number, and recovery process by standard recover state machine carry out；

Deskew_pro module: for identifying the time delay registration process of completion logic passage according to described FP, it is made up of deskew_ctrl submodule and FIFO submodule, adjustment and the degree of depth that wherein FIFO submodule completion logic communication channel delay is rectified a deviation are determined by maximum correction parameter, and the read-write operation of deskew_ctrl submodule error correct fifo module；

Ll_mux module: for the restructuring of the Frame after alignment of data in completion logic passage.

In such scheme, described bit polling mode includes but not limited to:

For OTL4.10 data-interface, every 2 bits, 1 physical channel data being distributed to 2 logical channels, the speed of logical channel is 1/2nd of original physical channel；

For OTL4.4 data-interface, every 5 bits, 1 physical channel data being distributed to 5 logical channels, the speed of logical channel is 1/5th of original physical channel；

After bit has demultiplexed, raw 20 logical channels of common property, each described logical channel is the 16320-byteOTU frame structure of standard, and has fixing OA1OA2 frame alignment byte and LLM byte.

In such scheme, described framing state machine defines 3 alarm statuses: OOF, IF and LOF, wherein:

At described OOF state, every 16320-byte joint periodically search 2 × OA1 and 2 × OA2 framing pattern, being found that framing pattern as determined after M 16320-byte cycle, search procedure enters described IF state；

In described IF state, continuously performing the detection of OA1OA2OA2 framing sub pattern in predetermined frame start position, as do not found framing pattern in M continuously 16320-byte cycle, search procedure returns to described OOF state；

As described OOF state continues 3ms, described LOF state will be entered；When described IF state uninterruptedly continues 3ms, remove described LOF alarm.

In such scheme, described logical channel number (LCN) is obtained by LLM modulus 20 computing, and recovery process is undertaken by standard state machine.

In such scheme, described recovery state machine defines 3 alarm statuses: OOR, IR and LOR, wherein:

Through continuous multiple 16320-byte cycles, " LLMMOD20 " value as obtained is identical, then accept this and be designated logical channel number (LCN), enters described IR state；

In described IR state, when " LLMMOD20 " value received each in continuous multiple 16320-byte cycles and accepted ident value differ, enter described OOR state, and retain the index value of last reception as logical channel number (LCN)；

When described OOR state continues 3ms, enter described LOR state；When described IR state continues 3ms, exit LOR state.

Present invention also offers a kind of optical transfer network MLD method for interface adaptation, comprise the following steps:

Physical channel bit demultiplexes to logical channel；

Detect state machine according to framing, at each logical channel inner search OA1OA2 framing byte-pattern, produce the channel data after FP identifies and export framing, and export corresponding alarm status；

Each logical channel has path marking LLM byte, obtains logical channel number (LCN) by LLM modulus 20 computing, and recovery process is undertaken by standard state machine, and exports corresponding alarm status；

The process of MLD transmission data can cause existing between logical channel delay deviation, compensation of delay must be carried out at receiving terminal, eliminate interchannel delay inequality, logical channel frame alignment mark is as the mark of interchannel delay inequality, then by the logical channel number (LCN) after sequence and data write corresponding correction FIFO, then pass through the Different Logic passage frame alignment home position read in correction FIFO and control the read operation of each lane deskew FIFO, the registration process of completion logic interchannel data delay difference；It addition, the correction size of logical channel depends on the degree of depth of correction FIFO；

Logical channel interleaves, by 16byte, OTU4 Frame and the corresponding OTU4 frame alignment signal that repeating query is recombinated out original successively.

In the above-mentioned methods, the process of framing includes herein below:

In the above-mentioned methods, logical channel number (LCN) recovers following content:

In the above-mentioned methods, described logical channel time delay registration process comprises the following steps:

When LOF or LOR state occurs in arbitrary logical channel, then all logical channels will be in reset state；Write FP mark and data successively to correction FIFO when all logical channels are in IF and IR state, the read-write operation of FIFO is performed continuously over；The FP of the passage 0 read in correction FIFO is identified 19 OTU4 frame periods of time delay, and the FP of passage 1 identifies 18 OTU4 frame periods of time delay, the like, the FP mark of passage 19 does not need time delay；FP FP_DLY after time delay represents, after delay process, interchannel FP only exists transmission delay deviation；The maximum correction value of communication channel delay deviation requires to be not more than the half in passage frame period, and otherwise delay inequality will be unable to compensate；

Reading side at correction FIFO, FP_DLY signal after real-time sampling time delay, when the FP_DLY=1 of certain passage of correction FIFO being detected, makes to can request that rdreq sets to 0 by the reading of this passage, control this passage and suspend reading data, and continue to detect the passage arrived thereafter；

The rdreq of all correction FIFO passages is carried out line or computing, obtains rdreq_or control signal；All correction FIFO passage FP_DLY are carried out line and computing, obtains fp_dly_and control signal；When detecting that rdreq_or is 0, the rdreq signal of all correction FIFO passages is put 1 simultaneously, recover the normal read operations of all correction FIFO passages；

Follow-up after fp_dly_and=1 being detected, then time delay correction has processed；

As arbitrary correction FIFO passage occurs that writing spill-over goes out alarm, then time delay correction processes unsuccessfully.

The present invention is according to logical channel frame alignment (FP) mark extracted and recover and logical channel number (LCN), control the read operation of lane deskew FIFO, solve the multi-channel data delay deviation problem occurred in the transmission of 100GMLD interface, and the correction range of communication channel delay is by the degree of depth flexible of the FIFO that rectifies a deviation.

This circuit realiration small scale, autgmentability is strong, fully meets 100G and the adaptive demand of super 100GOTN line interface；Additionally the logical channel time delay alignment techniques in this method can equally be well applied to the high speed MLD coffret delay process such as interconnection between 100GE, INTERLAKEN and sheet.

Accompanying drawing explanation

Fig. 1 is existing OTU4 frame MLD mode schematic diagram；

Fig. 2 is MLD interface adaption system block diagram provided by the invention；

Fig. 3 is logical channel deskew sequential chart；

Fig. 4 is the flow chart of MLD method for interface adaptation.

Detailed description of the invention

The invention provides a kind of optical transfer network MLD interface adaption system, below in conjunction with specific embodiment and Figure of description, the present invention is described in detail.

As in figure 2 it is shown, MLD interface adaption system block diagram provided by the invention, including bit_demux module 10, ll_align module 20, llm_recovery module 30, deskew_pro module 40 and ll_mux module 50；Wherein:

Bit_demux module 10: for physical channel data bit being demultiplexed into logical channel according to bit polling mode；For OTL4.10 data-interface, every 2 bits, 1 physical channel data being distributed to 2 logical channels, the speed of logical channel is 1/2nd of original physical channel；For OTL4.4 data-interface, every 5 bits, 1 physical channel data being distributed to 5 logical channels, the speed of logical channel is 1/5th of original physical channel；

After bit has demultiplexed, raw 20 logical channels of common property, each logical channel is 16320-byte (4080 × 4) the OTU frame structure of standard, and has fixing OA1OA2 frame alignment byte and LLM byte.

Ll_align module 20: be used for the detection of the frame alignment byte of 20 tunnel logical channels, obtain passage frame alignment (FP) mark, and export the channel data after framing and alarm indication signal, framing completes by the framing state machine of standard, and framing state machine defines 3 alarm status: OOF (OOF), IF (framing) and LOF (LOF).

IF (framing) includes herein below:

In OOF state, every 16320-byte joint periodically search 2 × OA1 and 2 × OA2 framing pattern, if certain was determined after the 16320-byte cycle is found that framing pattern, search procedure enters IF state；

In IF state, the detection of OA1OA2OA2 (logical channel frame first trip 3/4/5 byte) framing sub pattern is continuously performed in predetermined frame start position, if not finding framing sub pattern in M continuously 16320-byte cycle, search procedure returns to OOF state；

If OOF state continues 3ms, LOF state will be entered；When IF state uninterruptedly continues 3ms, remove LOF alarm.

If IF state duration is less than 3ms, original OOF state duration is not removed, it is necessary to add up with OOF state duration later, carries out the phenomenon of long-time concussion to avoid framing state to be likely to occur between OOF and IF.

Llm_recovery module 30: for recovery and the sequence of completion logic channel number.Logical channel number (LCN) is obtained by LLM modulus 20 (LLMmod20) computing, for ensureing the stability of logical channel number (LCN), recovery process is recovered state machine by standard and is carried out, and recovers state machine and defines 3 alarm statuses: recovers step-out (OOR), recovers correct (IR) and recover to lose (LOR).

The following content of recovery process:

Through continuous 5 16320-byte cycles, if " LLMMOD20 " value obtained is identical, accept this ident value as logical channel index value, enter IR and process state；

In IR state, when " LLMMOD20 " value received each in continuous 5 16320-byte cycles and accepted ident value differ, enter OOR state, and retain the ident value of last reception as logical channel number (LCN)；

When OOR state continues 3ms, enter LOR state.When IR state continues 3ms, exit LOR state.

In order to the uniqueness of completion logic channel number detects and channel number rearrangement, each channel number recovered is carried out 20 bits of encoded.Coding signal uniquely reflects, for the bit position of " 1 ", the index value that this logical channel is actual.Such as channel number 3 is encoded to " 00000000000000001000 ".

20 logical channel index value after coding are arranged, forms the rectangular channel list of 20 × 20 shown in table 1.In his-and-hers watches, each row carry out the statistics of bit 1, if statistical value is 1, then shows that the logical channel number (LCN) value of input is unique, otherwise have two or more input logic passages identical channel number value occur.According to each column in table 1, the position of bit 1 occurs, select respective channel data and FP frame alignment to be sent in passage originally from 20 logical channels of input.The coding information of such as output channel is " 00000000000000001000 ", then select the data of the 3rd input logic passage and FP framing in this output channel.

Table 1: logical channel sorted lists

Deskew_pro module 40: identify completion logic communication channel delay registration process according to FP；

It is provided with deskew_ctrl submodule 410 in deskew_pro module 40, is used for controlling the read-write operation of 20 tunnel correction FIFO submodules 420.

The time delay registration process of logical channel comprises the following steps:

A41, when logical channel occur effective LOF or LOR alarm, 20 tunnel correction FIFO submodules 420 will be in reset state, now all logical channels read-write of 20 tunnels correction FIFO submodules 420 is enabled invalid (for low level) by deskew_ctrl submodule 410, and the read/write address of FIFO submodule 420 of being rectified a deviation on 20 tunnels arranges a little deviation (such as value is 2), it is prevented that after normal operation, read/write address conflict occur in 20 tunnel correction FIFO submodules 420；When all logical channels are in IF and IR state, all logical channels read-write of 20 tunnels correction FIFO submodules 420 is enabled effectively (for high level) by deskew_ctrl submodule 410, and read/write address adds 1 and is incremented by, and is in normal duty.

A42, according to the logical channel number (LCN) after sequence, the FP of 20 tunnel logical channels is identified and data is respectively written in 20 tunnels correction FIFO submodules 420 of correspondence.

The logical channel FP mark read in correction FIFO submodule 420 is carried out delay process by A43, deskew_pro module, eliminates the intrinsic difference of interchannel；By 19 OTU4 frame periods of passage 0FP time delay, 18 OTU4 frame periods of passage 1FP time delay, the like, passage 19FP does not need delay process.Time initial, owing to interchannel exists circuit delay difference, the FP_DLY position after time delay is random, in Fig. 3 shown in fp_dly [x] waveform, fp_dly is carried out line and computing (&fp_dly simultaneously), obtain alignment and control the fp_dly_and signal of mark.After fp_dly_and=1 being detected, it was shown that the channel data read from FIFO aligns, and interchannel delay deviation eliminates, and correction process completes.Can be seen that as fp_dly_and=1 from the waveform of Fig. 3, the fp_dly signal on 20 tunnels is alignment.

A44, FP_DLY signal to the passage after time delay carry out real-time sampling, when the FP_DLY=1 of certain passage being detected, make the reading of this passage to can request that rdreq [x] puts ' 0 ', control this passage and suspend and read data, and read address value and keep.The 20bitrdreq control signal produced is carried out line or computing (| rdreq) simultaneously, obtains rdreq_or signal；When rdreq_or=0 being detected, it was shown that have been found that the logical channel that time delay is maximum, now the rdreq reading of all passages is made can request that and puts ' 1 ' simultaneously by deskew_ctrl submodule 410, recovers the normal read operations of all passages；In Fig. 3 shown in rdreq [x] and rereq_or waveform.

A45, rectify a deviation in processing procedure in time delay, if the passage of arbitrary correction FIFO submodule occurs that writing spill-over goes out (overflow) alarm, it was shown that the delay value of this passage is beyond the FIFO maximum correction value set, then time delay correction processes unsuccessfully.

Ll_mux module 50: for the restructuring of the OTU4 Frame after alignment of data in completion logic passage.Logical channel interleaves, by 16byte, OTU4 Frame and the corresponding OTU4 frame alignment signal that repeating query is recombinated out original successively.

OTU4 frame regrouping process: with logical channel 0FP framing signal for benchmark, by shifting, the logical channel data of input are latched once by every 8 clock cycle, constitute 16bytes data width, then then through 8 clock cycle, 20 × 16=320bytes byte is converted to the OTU4 that data width is 40bytes (320bit) successively and exports signal.

The operation principle of present system is as follows:

nullWhen input has data to input，Bit_demux module 10 is according to bit polling mode，By OTL4.10 data-interface, physical channel data bit is distributed in 20 tunnel logical channels，Then ll_align module 20 is by every 16320-byte periodically search 2 × OA1 and 2 × OA2 framing pattern，Carry out the detection of frame alignment byte，If certain was determined after the 16320-byte cycle is found that framing pattern，Search procedure enters IF state，And continuously perform the detection of OA1OA2OA2 (logical channel frame first trip 3/4/5 byte) framing sub pattern in predetermined frame start position，If finding framing sub pattern in the 16320-byte cycle，Then produce the framing mark FP signal of logical channel，And the channel data after framing transports to llm_recovery module 30；If not finding framing pattern in M continuously 16320-byte cycle, search procedure returns to OOF state, when OOF state continues 3ms, LOF state will be entered, now ll_align module 20 will proceed every 16320-byte periodically search framing pattern, if finding, framing pattern and IF state uninterruptedly continue 3ms, LOF alarm and will remove.

Llm_recovery module 30 receives the channel data of ll_align module 20 input, through continuous 5 16320-byte cycles, if " LLMMOD20 " value obtained is identical, then accepts this logical channel index value, enters IR and processes state；If each " LLMMOD20 " value received and accepted ident value differ, enter OOR state, and retain the index value of last reception as logical identifier value；When OOR state continues 3ms, entering LOR state, for the channel data of input, llm_recovery module 30 will constantly carry out " LLMMOD20 " computing, if " LLMMOD20 " value obtained is identical, and IR state continues 3ms, exits LOR state.

nullWhen effective LOF or LOR alarm occurs in logical channel，20 tunnel correction FIFO submodules 420 will be in reset state，When all logical channels are in IF and IR state，The read-write of 20 tunnel correction FIFO submodules 420 enables all effectively (for high level)，Read/write address adds 1 and is incremented by，And it is in normal duty，According to the logical channel number (LCN) after sequence，The FP frame alignment mark of 20 tunnel logical channels and data are respectively written in 20 tunnel correction FIFO submodules 420 of correspondence，And logical channel FP framing signal will be carried out corresponding delay process by deskew_pro module 40，And obtain the FP_DLY framing signal after sampling time delay，Deskew_ctrl submodule 410 controls the read-write operation of 20 tunnel correction FIFO submodules 420 simultaneously；When the FP_DLY=1 of certain FIFO passage being detected, the reading of this passage FIFO is made to can request that rdreq [x] puts ' 0 ' by deskew_ctrl submodule 410, as fp_dly_and=1, illustrate that the FP_DLY signal on 20 tunnels aligns, now, rdreq_or=0, the rdreq reading of all passage FIFO is made can request that by deskew_ctrl submodule 410 puts ' 1 ' simultaneously, recover the normal read operations of all FIFO, in time delay correction process, as arbitrary passage FIFO occurs that writing spill-over goes out (overflow) alarm, then procedure failure of rectifying a deviation.

Data in the passage of 20 tunnels correction fifo modules 50 are interleave, by the number order of 0-19 and 16byte, OTU4 Frame and the corresponding OTU4 frame alignment signal that repeating query is recombinated out original by last ll_mux module 50 successively.

The circuit realiration small scale of the method, autgmentability is strong, fully meets 100G and the adaptive demand of super 100GOTN line interface；Additionally the logical channel time delay alignment techniques in this method can equally be well applied to the high speed MLD coffret delay process such as interconnection between 100GE, INTERLAKEN and sheet.

As shown in Figure 4, present invention also offers a kind of optical transfer network MLD method for interface adaptation, comprise the following steps:

S1: physical channel bit demultiplexes: physical channel is demultiplexing as 20 tunnel logical channels.Each OTL4.10 channel data is distributed in 2 tunnel logical channels by bit poll, or each OTL4.4 channel data is distributed in 5 tunnel logical channels by bit poll.

S2: logical channel frame alignment (FP) is extracted: detect state machine according to framing, at each logical channel inner search OA1OA2 framing byte-pattern, the channel data after producing FP signal and exporting framing, and exports corresponding alarm status.

S3: logical channel number (LCN) recovers and sequence, and each logical channel has path marking (LLM) byte, obtains logical channel number (LCN) by LLM modulus 20 (LLMmod20) computing.

Logical channel number (LCN) is certain integer between 0 to 19, and for ensureing the stability of logical channel number (LCN), recovery process provides the protection mechanism of forward and backward, and exports corresponding alarm status；The logical channel number (LCN) recovered is carried out uniqueness detection, it is ensured that occur without the situation that logical channel number (LCN) is identical simultaneously；The logical channel number (LCN) additionally recovered in circuit is arbitrary, and receiving terminal must also re-start sequence by the number order of 0 to 19.

S4: logical channel time delay is alignd: the MLD process transmitting data can cause existing between logical channel delay deviation, compensation of delay must be carried out at receiving terminal, eliminating interchannel delay inequality (deskew), logical channel frame alignment (FP) mark is as the mark of deskew.By in the logical channel number (LCN) after sequence and data write corresponding correction FIFO, then pass through the Different Logic passage frame alignment home position read in correction FIFO and control the read operation (read address and read to enable) of each lane deskew FIFO, the registration process of completion logic interchannel data delay difference；It addition, the correction size of logical channel depends entirely on the degree of depth of correction FIFO.

Logical channel time delay alignment comprises the following steps:

B1, in step S20 and S30 process, as LOF or LOR state occurs in arbitrary logical channel, then all correction FIFO passages will be in reset state；Write FP mark and data successively to correction FIFO when all logical channels are in IF and IR state, the read-write operation of FIFO is performed continuously over.According to the multichannel distribution mechanism of OTU4, adjacent FP signal 1 fixing OTU4 frame period of existence offsets, passage 0 (lane0) FP read in correction FIFO is identified 19 OTU4 frame periods of time delay, passage 1 (lane1) FP identifies 18 OTU4 frame periods of time delay, the like, passage 19 (lane19) frame FP does not need time delay；FP FP_DLY after time delay represents.After delay process, interchannel FP only exists transmission delay deviation, and in this programme, the maximum correction value of communication channel delay deviation requires to be not more than the half in passage frame period, and otherwise delay inequality will be unable to compensate.

B2, in the reading side of FIFO, FP_DLY signal after real-time sampling time delay, when the FP_DLY=1 of certain passage of correction FIFO being detected, makes to can request that rdreq sets to 0 by the reading of this passage, control this passage and suspend reading data, and continue to detect the passage arrived thereafter；

The rdreq of all correction FIFO passages are carried out line or computing (| rdreq), obtains rdreq_or control signal.The FP_DLY of all correction FIFO passages is carried out line and computing (&fp_dly), obtain fp_dly_and control signal；When detecting that rdreq_or is 0, it was shown that the maximum correction FIFO passage of time delay arrives, now the rdreq signal of all logical channels is put 1 simultaneously, recover the normal read operations of all correction FIFO passages；Follow-up after fp_dly_and=1 being detected, it was shown that the channel data read from correction FIFO aligns, and interchannel delay deviation eliminates, and time delay correction has processed；If arbitrary correction FIFO passage occurs that writing spill-over goes out (overflow) alarm, then time delay correction processes unsuccessfully.

S5: logical channel interleaves, by 16byte, OTU4 Frame and the corresponding OTU4 frame alignment signal that repeating query is recombinated out original successively.

The present invention is not limited to above-mentioned preferred forms, and anyone should learn the structure change made under the enlightenment of the present invention, and every have same or like technical scheme with the present invention, each falls within protection scope of the present invention.

Claims

1. optical transfer network MLD interface adaption system, it is characterised in that including:

2. the system as claimed in claim 1, it is characterised in that described bit polling mode includes but not limited to:

3. the system as claimed in claim 1, it is characterised in that described framing state machine defines 3 alarm statuses: OOF, IF and LOF, wherein:

4. the system as claimed in claim 1, it is characterised in that described logical channel number (LCN) is obtained by LLM modulus 20 computing, and recovery process is undertaken by standard state machine.

5. the system as claimed in claim 1, it is characterised in that described recovery state machine defines 3 alarm statuses: OOR, IR and LOR, wherein:

6. optical transfer network MLD method for interface adaptation, it is characterised in that comprise the following steps:

Physical channel bit demultiplexes to logical channel；

7. method as claimed in claim 6, it is characterised in that the process of framing includes herein below:

8. method as claimed in claim 6, it is characterised in that the following content of logical channel number (LCN) recovery process:

9. method as claimed in claim 6, it is characterised in that between described logical channel, the registration process of data delay difference comprises the following steps: