CN101039158A - Apparatus for canceling frame dislocation - Google Patents
Apparatus for canceling frame dislocation Download PDFInfo
- Publication number
- CN101039158A CN101039158A CN 200610057172 CN200610057172A CN101039158A CN 101039158 A CN101039158 A CN 101039158A CN 200610057172 CN200610057172 CN 200610057172 CN 200610057172 A CN200610057172 A CN 200610057172A CN 101039158 A CN101039158 A CN 101039158A
- Authority
- CN
- China
- Prior art keywords
- frame
- unit
- bit
- dislocation
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a frame dislocation elimination device, consisting of a reference frame generator used for the production of the frame alignment reference frame, and one or more frame position regulator. The frame position regulator consists of a bit displacement unit which is used to do displacement treatment to the receiving frame data, and send the frame data after displacement to a frame synchronization treatment unit, the frame synchronization treatment unit which is used to find frame joint characteristics word from the receiving frame data, and product frame joint position mark pulse signal to a frame dislocation comparison unit, at the same time output the frame data, the frame dislocation comparison unit which is used to compare the receiving frame joint position mark pulse signal and the frame alignment reference frame sent by reference frame generator, and send the comparative result information to a bit displacement control unit, the bit displacement control unit which calculates and send displacement bit number to the bit displacement unit according to the comparative result data. The devices of the invention can eliminate the frame dislocation, the implementation is easy, and the integrated cost is decreased greatly.
Description
Technical field
The present invention relates to the frame treatment technology in synchronous digital hierarchy/Synchronous Optical Network system, particularly apparatus for canceling frame dislocation.
Background technology
Synchronous digital hierarchy/Synchronous Optical Network (SDH/SONET) system is that a kind of employing interleaves the communication system of the signal multiplexing of different rates grade being transmitted to the interface rate of several standards with the mode of synchronous multiplexing.In the SDH system, the SDH frame of low order speed is multiplexed in the process of SDH frame of high-order speed, must guarantee that at first the frame structure between the several low order SDH frame aligns.In this case, general common use RAM buffer memory low order SDH frame data, control is read and the achieve frame alignment synchronously.As seen, the degrees of tolerance of low order SDH frame dislocation is depended on the degree of depth of RAM, the just memory capacity of RAM.If in nervous programmable logic device (CPLD/FPGA) or application-specific integrated circuit (ASIC) (ASIC), adopt big capacity RAM, all will make this realization become difficult, and cost raise significantly.Equally, for the SONET system, also there is same problem.
Summary of the invention
Technical problem to be solved by this invention provides a kind of apparatus for canceling frame dislocation, realize eliminating the frame dislocation, and overcome realization difficulty and the high problem of integrated cost of in programmable logic device or application-specific integrated circuit (ASIC), using RAM to eliminate the frame dislocation in a large number and bringing.
For solving the problems of the technologies described above, it is as follows to the invention provides scheme:
A kind of apparatus for canceling frame dislocation comprises: the reference frame generator and the one or more framing bit adjuster that are used to produce frame alignment reference frame;
Wherein, the framing bit adjuster comprises:
Bit shifter unit be used for the frame data that receive are made shifting processing, and the frame data after will being shifted sends to the frame synchronization process unit;
The frame synchronization process unit is used for finding the frame head tagged word from the frame data that receive, and produces frame head tick lables pulse signal to frame misplace comparing unit, output frame data simultaneously;
Frame dislocation comparing unit is used for the frame head tick lables pulse signal that will the receive reference frame that aligns with the frame that the reference frame generator sends and compares, and comparative result information is sent to the bit control unit that is shifted;
Bit displacement control unit, according to receiving the comparative result data, calculating and sending send the shifted bits number to bit shifter unit.
Device of the present invention replaces buffer memory RAM by described device, has realized the elimination of frame dislocation, and when this device is applied to eliminate in programmable logic device or the application-specific integrated circuit (ASIC) frame dislocation, can save the use of RAM, realize simply, and greatly reduce integrated cost.
Technical problem to be solved by this invention, technical scheme main points and beneficial effect will be in conjunction with the embodiments, are further described with reference to accompanying drawing.
Description of drawings
Fig. 1 is the structural representation of the described apparatus for canceling frame dislocation of the embodiment of the invention;
Fig. 2 is the workflow diagram of the described apparatus for canceling frame dislocation of the embodiment of the invention;
Fig. 3 is described four road STM64 apparatus for canceling frame dislocation of the embodiment of the invention.
Embodiment
Be example with the SDH frame data below, be described further.
With reference to Fig. 1, the described apparatus for canceling frame dislocation of the embodiment of the invention comprises: reference frame generator 100 and one or more (N, N＞1) framing bit adjuster 200.Wherein, each described framing bit adjuster 200 comprises: bit shifter unit 21, frame synchronization process unit 22, frame dislocation comparing unit 23, bit displacement control unit 24.
Described bit shifter unit 21 be used for the frame data that receive are made shifting processing, and the frame data after will being shifted sends to frame synchronization process unit 22;
Described frame synchronization process unit 22 is used for finding the frame head tagged word from the frame data that receive, and produces frame head tick lables pulse signal to frame misplace comparing unit, output frame data simultaneously;
Described frame dislocation comparing unit 23 is used for the frame head tick lables pulse signal that will the receive reference frame that aligns with the frame that reference frame generator 100 sends and compares, and comparative result information is sent to the bit control unit that is shifted;
Described bit displacement control unit 24, according to receiving the comparative result data, calculating and sending send the shifted bits number to bit shifter unit.
At first, one road frame data that will receive by the bit shifter unit 21 in each framing bit adjuster 200 are sent to frame synchronization process unit 22; Frame synchronization process unit 22 finds the frame head tagged word from the frame data that receive, and produces frame head tick lables pulse signal to frame dislocation comparing unit 23, and simultaneously frame data is exported; Frame dislocation comparing unit 23 compares the frame head tick lables pulse signal the received reference frame that aligns with frame that the reference frame generator produces, send frame head alternate position spike information to the bit control unit 24 that is shifted by calculating and sending relatively; Perhaps, when frame dislocation comparing unit 23 was not received the frame head tick lables pulse signal of frame synchronous processing device 22 transmissions, the frame mistake was that comparing unit 23 transmit frame step-out information are to bit displacement control unit 24; Bit displacement control unit 24 is according to frame head alternate position spike information or the OOF information received, calculate the shifted bits number and be sent to bit shifter unit 21, bit shifter unit 21 is shifted to frame data according to the shifted bits data, frame data after the displacement are sent to frame synchronization process unit 22, like this, entire frame data shift processing procedure constantly repeats said process.
With reference to Fig. 2, the operation principle flow process of apparatus for canceling frame dislocation of the present invention is as follows:
Be described in detail the method for work of apparatus for canceling frame dislocation below.
Step 201: displacement is adjusted; According to the indication of bit displacement control unit, the SDH frame data are moved to left or move to right export after some bit process.
Step 202: frame synchronization process; The output (the SDH frame data after the shifting processing) of bit shifter unit is made to seek SDH frame head tagged word handle, as search out SDH frame head tagged word, then provide frame head tick lables pulse signal.
Step 203: frame head tick lables pulse signal and reference frame are compared, as no frame dislocation, execution in step 205, otherwise execution in step 204.The frame head tick lables pulse signal of frame synchronization process unit output is compared with the frame head tick lables pulse signal of reference frame, and as occurring at synchronization, then execution in step 205, and as in the synchronization appearance, then execution in step 204.
Step 204: number of shift bits is calculated, and execution in step 201 then.According to frame dislocation result relatively in the step 204, the direction of bit displacement and the bit number of displacement in the calculation procedure 201, execution in step 201 then.
Step 205: alignment output; At this moment, the N road SDH frame data stream from the output of frame synchronization process unit is the frame structure complete matching.
With reference to Fig. 3, be to adopt four road STM64 apparatus for canceling frame dislocation of the present invention.Use first via STM64 frame as reference frame, be sent to frame dislocation comparing unit, simultaneously described first via STM64 frame is exported by output 11, after four road STM64 frames all find the frame head position, comparative result according to frame dislocation comparing unit, adjust the direction of displacement and the number of shift bits of bit shifter unit by bit displacement control unit, thereby reach the second the tunnel, purpose that Third Road and the four road STM64 frame all align with first via STM frame frame structure.As seen, the degree of the frame dislocation that this device can be eliminated depends on the bit number that bit shifter unit can move to left and move to right.
A kind of apparatus for canceling frame dislocation of the present invention, be not restricted to listed utilization in specification and the execution mode, it can be applied to various suitable the present invention's field fully, for those skilled in the art, can easily realize additional advantage and make amendment, therefore under the situation of the spirit and scope of the universal that does not deviate from claim and equivalency range and limited, the examples shown that the present invention is not limited to specific details, representational equipment and illustrates here and describe.
Claims (7)
1, a kind of apparatus for canceling frame dislocation is characterized in that comprising: the reference frame generator (100) and the one or more framing bit adjuster (200) that are used to produce frame alignment reference frame;
Wherein, framing bit adjuster (200) comprising:
Bit shifter unit (21) be used for the frame data that receive are made shifting processing, and the frame data after will being shifted sends to frame synchronization process unit (22);
Frame synchronization process unit (22) is used for finding the frame head tagged word from the frame data that receive, and produces frame head tick lables pulse signal to frame misplace comparing unit, output frame data simultaneously;
Frame dislocation comparing unit (23) is used for the frame head tick lables pulse signal that will the receive reference frame that aligns with the frame that reference frame generator (100) sends and compares, and comparative result information is sent to the bit control unit that is shifted;
Bit displacement control unit (24), according to receiving the comparative result data, calculating and sending send the shifted bits number to bit shifter unit.
2, device according to claim 1 is characterized in that: described reference frame generator (100), the road frame data input that is used for receiving is as the reference frame that sends to frame dislocation comparing unit (23).
3, device according to claim 2 is characterized in that: described reference frame generator (100) also comprises frame data output 11, is used for the road frame data output that will receive.
4, device according to claim 1 is characterized in that: frame dislocation comparing unit (23) is used for the frame head alternate position spike information of relatively back generation is sent to bit displacement control unit.
5, device according to claim 1 is characterized in that: frame dislocation comparing unit (23) is used for the OOF information of relatively back generation is sent to bit displacement control unit.
6, device according to claim 1 is characterized in that: described bit displacement control unit (24), be used for according to the frame head alternate position spike information of receiving, and calculating and sending send the shifted bits number to bit shifter unit.
7, device according to claim 1 is characterized in that: described bit displacement control unit (24), be used for according to the OOF information of receiving, and calculating and sending send the shifted bits number to bit shifter unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006100571728A CN101039158B (en) | 2006-03-13 | 2006-03-13 | Apparatus for canceling frame dislocation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006100571728A CN101039158B (en) | 2006-03-13 | 2006-03-13 | Apparatus for canceling frame dislocation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101039158A true CN101039158A (en) | 2007-09-19 |
| CN101039158B CN101039158B (en) | 2011-08-24 |
Family
ID=38889825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006100571728A Expired - Fee Related CN101039158B (en) | 2006-03-13 | 2006-03-13 | Apparatus for canceling frame dislocation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101039158B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521560B (en) * | 2009-03-26 | 2011-11-16 | 上海交通大学 | Forward error correction coding state synchronous system in single-frequency network broadcast |
| CN105812062A (en) * | 2016-03-04 | 2016-07-27 | 烽火通信科技股份有限公司 | MLD interface adapting method and system of optical transport network |
| CN106918730A (en) * | 2017-02-09 | 2017-07-04 | 深圳市鼎阳科技有限公司 | A kind of digital oscilloscope and its multi channel signals synchronous method |
| CN108234075A (en) * | 2016-12-22 | 2018-06-29 | Macom连接解决有限公司 | By being compared, for the power optimization mechanism of framer using serial in being handled in frame alignment |
| CN109714145A (en) * | 2018-12-29 | 2019-05-03 | 杭州迪普科技股份有限公司 | A kind of method and device of multi-channel data alignment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1534906B (en) * | 2003-04-02 | 2010-04-28 | 华为技术有限公司 | Frame aligning method and circuit |
-
2006
- 2006-03-13 CN CN2006100571728A patent/CN101039158B/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521560B (en) * | 2009-03-26 | 2011-11-16 | 上海交通大学 | Forward error correction coding state synchronous system in single-frequency network broadcast |
| CN105812062A (en) * | 2016-03-04 | 2016-07-27 | 烽火通信科技股份有限公司 | MLD interface adapting method and system of optical transport network |
| CN105812062B (en) * | 2016-03-04 | 2018-11-30 | 烽火通信科技股份有限公司 | Optical transfer network MLD method for interface adaptation and system |
| CN108234075A (en) * | 2016-12-22 | 2018-06-29 | Macom连接解决有限公司 | By being compared, for the power optimization mechanism of framer using serial in being handled in frame alignment |
| CN108234075B (en) * | 2016-12-22 | 2022-03-04 | Macom连接解决有限公司 | Power optimization mechanism for framers by using serial comparisons in frame alignment processing |
| CN106918730A (en) * | 2017-02-09 | 2017-07-04 | 深圳市鼎阳科技有限公司 | A kind of digital oscilloscope and its multi channel signals synchronous method |
| CN109714145A (en) * | 2018-12-29 | 2019-05-03 | 杭州迪普科技股份有限公司 | A kind of method and device of multi-channel data alignment |
| CN109714145B (en) * | 2018-12-29 | 2021-09-21 | 杭州迪普科技股份有限公司 | Method and device for aligning multi-channel data |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101039158B (en) | 2011-08-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7839839B2 (en) | Differential inverse multiplexing virtual channels in 40G ethernet applications | |
| CN101039158A (en) | Apparatus for canceling frame dislocation | |
| JP4783245B2 (en) | Transceiver, transmitter, and receiver | |
| CN109450610B (en) | Channel phase alignment circuit and method | |
| DE69231871T2 (en) | Parallel transmission method | |
| US7835401B2 (en) | System and method for inverse multiplexing using transcoding and frame alignment markers | |
| CA2376971A1 (en) | Combining a clock signal and a data signal | |
| CN102710240A (en) | Signal processing device and method, SERDES and processor | |
| CN1905558A (en) | Individualized ethernet exchange plate and data exchanging method | |
| EP2745456B1 (en) | Circuit arrangement and method for transmitting signals | |
| CN101552766A (en) | Deskew device and method applied to high-speed parallel optical interconnection system | |
| WO2013023653A2 (en) | Circuit arrangement and method for transmitting signals | |
| CN1132313C (en) | Over-sampling type clock recovery circuit with power consumption reduced | |
| CN1622067A (en) | Method for high speed SATA interface data recovery and serial-parallel conversion and circuit module | |
| CN1062400C (en) | Synchronizing circuit arrangement | |
| CN105468561A (en) | High-speed asynchronous serial communication method | |
| CN101577598A (en) | Multiple signal multiplexing and demultiplexing methods, devices and systems | |
| CN1230886C (en) | Method for realizing high speed celf transmission | |
| CN1297093C (en) | Transmit-receive method and apparatus for synchronous signal | |
| CN1162015C (en) | Synchronization method between base transceiver station and network clock | |
| CN1913422A (en) | Time server and method for increasing output precision of time server | |
| CN1275434C (en) | Method of transmitting asychronous linking data and its performance device | |
| EP2745458B1 (en) | Circuit arrangement and method for transmitting signals | |
| US5781587A (en) | Clock extraction circuit | |
| CN1798117A (en) | Synchronization method and synchronization circuit for serial signal in high speed |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170817 Address after: 455000 No. 2, unit 7, building 751, Delong street, Wenfeng District, Henan, Anyang, 2702 Patentee after: Hu Haotian Address before: 518057 Nanshan District high tech Industrial Park, Guangdong, South Road, science and technology, ZTE building, legal department Patentee before: ZTE Corporation |
|
| TR01 | Transfer of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110824 Termination date: 20180313 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |