CN111416630A - Coding and decoding method and system - Google Patents

Abstract

The invention discloses a coding and decoding method and system, which relate to the technical field of communication. The method includes the following steps: establishing a plurality of independent channels, and each channel corresponds to a buffer space; each channel receives data frames and buffers them into corresponding Cache space; according to the preset scheduling strategy, the transmission and encoding and decoding of data frames in each buffer space are completed one buffer space at a time; wherein, the transmission and encoding and decoding of data frames include: reading a data frame in a buffer space, transmitting To the RS codec, the codec work of the data frame in the buffer space is completed, and the codec data frame is obtained. The present invention can perform encoding and decoding work on multi-channel data, so as to meet various work requirements at the present stage.

Description

A coding and decoding method and system

technical field

The present invention relates to the field of communication technologies, in particular to a coding and decoding method and system.

Background technique

As the bandwidth capacity of the 5G bearer network increases, FlexE, FlexO, and OTUk have more and more service types and access channels. The transmission of various services requires the support of FEC to ensure reliable transmission.

In the related art, the RS code is widely used to carry FEC. However, the complexity of the RS coding algorithm is high, and the scale of the circuit logic is large. If each service uses one codec, the overall circuit logic scale will be reduced. If it is too large, the cost of chip tape-out is too high. Therefore, the single-channel RS codec can no longer meet the application requirements, and an RS codec that supports parallel access of multiple services is required.

However, the RS code is a block code, and a codeword is a complete and indivisible whole. The rate of each service is different, so the multiplexing method has its own particularity. In addition, RS encoding and decoding is an intermediate link in the processing flow of the bearer network node, and the data from its entry to the exit is required in some occasions. The delay is fixed, and the output data envelope is required to be kept uniform. Therefore, the RS coding and decoding scheme that supports parallel access of multiple services cannot be provided at this stage.

Therefore, a new encoding and decoding method is urgently needed to solve the above problems.

SUMMARY OF THE INVENTION

In view of the defects existing in the prior art, the purpose of the present invention is to provide a method and system for encoding and decoding, which can perform encoding and decoding work on multi-channel data and meet various work requirements at the present stage.

In order to achieve the above purpose, the technical scheme adopted in the present invention is:

In a first aspect, the present invention discloses a coding and decoding method, which comprises the following steps:

Establish multiple independent channels, and each channel corresponds to a buffer space;

Each of the channels receives the data frame and buffers it into the corresponding buffer space;

According to the preset scheduling policy, the transmission and encoding and decoding of data frames in each buffer space are completed one buffer space at a time; wherein, the transmission and encoding and decoding of data frames include:

A data frame in the buffer space is read, and transmitted to the RS codec, the encoding and decoding work of the data frame in the buffer space is completed, and the encoding and decoding data frame is obtained.

On the basis of the above technical solution, the scheduling strategy includes the following steps:

The number of readable addresses in each of the cache spaces is polled, the channel with the largest readable address and a length greater than 1 codeword is located, and the corresponding channel is authorized to obtain the next read operation permission.

On the basis of the above technical solution, before each of the channels receives the data frames and buffers them in the corresponding buffer space, the method further includes a data shaping process, and the data sorting process includes the following steps:

comparing the data length of the data frame with a preset standard data length;

When the data length of the data frame is consistent with the standard data length, the data frame is normally transmitted;

When the data length of the data frame is greater than the standard data length, only the part of the data frame that conforms to the standard data length is transmitted;

When the data length of the data frame is smaller than the standard data length, according to a preset compensation rule, the data length of the data frame is adjusted to the standard data length, and the adjusted data frame is transmitted.

On the basis of the above technical solution, when the data length of the data frame is greater than the standard data length, only the part of the data frame that conforms to the standard data length is transmitted, and the frame start indication signal is detected. When the frame start indication signal is used, the data length of the next data frame is compared with the preset standard data length.

On the basis of the above technical solution, when the data length of the data frame is smaller than the standard data length, according to a preset compensation rule, the acquired frame start indication signal is deleted, and the data length of the data frame is Adjust to the standard data length, and transmit the adjusted data frame.

On the basis of the above technical solution, the method further comprises the following steps:

A first delay processing is performed on the data frame in the buffer space.

On the basis of the above technical solution, before correspondingly transmitting the encoded and decoded data frame to the corresponding output channel, the method further includes a data compensation process, and the data compensation process includes the following steps:

Obtain the first delay value of the encoded and decoded data frame during the first delay processing, and denote it as T1;

Obtain the data frame corresponding to the encoded and decoded data frame and store it in the buffer space at the beginning and the transmission delay value of the output channel corresponding to the incoming of the encoded and decoded data frame, denoted as T2;

Calculate the inherent delay value of the incoming channel corresponding to the encoded and decoded data frame, and denote it as T3, where T3=T2-T1;

Delay compensation is performed according to the inherent delay value corresponding to the encoded and decoded data frame.

In a second aspect, the present invention also discloses a coding and decoding system, the system comprising:

a channel configuration unit, which is used to establish a plurality of independent channels, and each channel corresponds to a buffer space;

a data receiving unit, which is used to control each of the channels to receive data frames and buffer them into corresponding buffer spaces;

A data encoding and decoding unit, which is used for completing the transmission and encoding and decoding of data frames in each buffer space one buffer space at a time according to a preset scheduling strategy, wherein the transmission and encoding and decoding of data frames include:

A data frame in the buffer space is read, and transmitted to the RS codec, the encoding and decoding work of the data frame in the buffer space is completed, and the encoding and decoding data frame is obtained.

Based on the above technical solutions, poll the number of readable addresses in each of the cache spaces, locate the channel with the largest readable address and a length greater than 1 codeword, and authorize the corresponding channel to obtain the next read operation permission.

On the basis of the above technical solution, the system further includes a data preprocessing unit, which is configured to perform data shaping on each of the data frames before the data receiving unit receives the data frames of the data receiving unit;

the data preprocessing unit, which is specifically configured to compare the data length of the data frame with a preset standard data length;

the data preprocessing unit, which is specifically configured to transmit the data frame normally when the data length of the data frame is consistent with the standard data length;

the data preprocessing unit, which is specifically configured to transmit only the part of the data frame that conforms to the standard data length when the data length of the data frame is greater than the standard data length;

The data preprocessing unit is specifically configured to adjust the data length of the data frame to the standard data length according to a preset compensation rule when the data length of the data frame is smaller than the standard data length , and transmit the adjusted data frame.

Compared with the prior art, the advantages of the present invention are:

(1) The present invention obtains data frames from different sources by presetting mutually independent channels, and encodes and decodes the data frames in multiple channels in batches, thereby realizing multi-channel encoding and decoding work and satisfying various tasks. need.

(2) The present invention keeps the output data envelope consistent with the input data envelope and has the same uniformity, avoiding adverse impact on the cache of downstream modules.

(3) The preset scheduling strategy of the present invention completes the transmission and encoding and decoding of data frames in each buffer space one buffer space at a time, avoiding bandwidth waste and effectively controlling the occupancy rate of the buffer space.

(5) In the present invention, the input and output delays of data are controllable, which is convenient for staff to adjust and control, and meets various work requirements.

Description of drawings

FIG. 1 is a flowchart of steps of a coding and decoding method in Embodiment 1 of the present invention;

2 is a flow chart of the steps of the data sorting process in the encoding and decoding method in the first embodiment of the present invention;

3 is a flow chart of the steps of the data compensation process in the encoding and decoding method in Embodiment 1 of the present invention;

4 is a flowchart of steps of RS (255, 239) encoding and decoding supporting 4-channel OTU4/OTU2 access in the encoding and decoding method according to Embodiment 1 of the present invention;

Fig. 5 is the internal processing flow chart of the 4-channel RS (255, 239) code scheduler module in the encoding and decoding method in Embodiment 1 of the present invention;

6 is a structural block diagram of a coding and decoding system in Embodiment 2 of the present invention;

In the figure: 1. Channel configuration unit; 2. Data receiving unit; 3. Data coding and decoding unit; 4. Data preprocessing unit; 5. Time delay compensation unit.

Detailed ways

The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

Embodiments of the present invention provide a method and system for encoding and decoding, which can perform encoding and decoding work on multi-channel data and meet various work requirements at the present stage.

In order to achieve the above-mentioned technical effect, the general idea of the application is as follows:

A coding and decoding method, the method comprises the following steps:

S1. Establish multiple independent channels, and each channel corresponds to a buffer space;

S2, each channel receives the data frame and buffers it to the corresponding buffer space;

S3. According to the preset scheduling strategy, the data frame transmission and encoding and decoding in each buffer space are completed one buffer space at a time;

Among them, the transmission and encoding and decoding of the data frame include:

A data frame in a buffer space is read, and transmitted to the RS codec to complete the encoding and decoding of the data frame in the buffer space to obtain the encoded and decoded data frame.

The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

Example 1

Referring to FIGS. 1 to 5, Embodiment 1 of the present invention provides a method for encoding and decoding, and the method includes the following steps:

S1. Establish multiple independent channels, and each channel corresponds to a buffer space;

S2, each channel receives the data frame and buffers it to the corresponding buffer space;

S3. According to the preset scheduling strategy, the data frame transmission and encoding and decoding in each buffer space are completed one buffer space at a time;

Among them, the transmission and encoding and decoding of the data frame include:

A data frame in a buffer space is read, and transmitted to the RS codec to complete the encoding and decoding of the data frame in the buffer space, and the encoded and decoded data frame is obtained.

In the embodiment of the present invention, a plurality of independent channels are first established, each channel is used to receive data from different senders, and each channel corresponds to a buffer space, that is, each channel is configured with its own dedicated cache space;

Further, each channel receives the transmitted data frame, and stores the respectively received data frame in the corresponding buffer space;

Finally, start the data encoding and decoding work. According to the preset scheduling policy, each time a data frame is obtained from a buffer space for transmission and encoding and decoding. The transmission and encoding and decoding of the data frame include:

A data frame in a buffer space is read, and transmitted to the RS codec to complete the encoding and decoding of the data frame in the buffer space, and the encoded and decoded data frame is obtained.

In addition, it should be noted that the transmission and encoding and decoding of data frames in each buffer space are completed one buffer space at a time. Since one data frame is acquired from one buffer space for transmission and encoding and decoding at a time, the obtained data The data frame and the next acquired data frame can come from the same cache space or from different cache spaces, and the encoding and decoding work is that after multiple extractions and encoding and decoding, when the data in each cache space is read. It will end when it is finished.

In the embodiment of the present invention, by presetting mutually independent channels, data frames are obtained from different sources respectively, and data frames in multiple channels are encoded and decoded in batches, thereby realizing multi-channel encoding and decoding work and satisfying various tasks. need.

It should be noted that the coding and decoding work is mainly performed by the RS codec. The processing bandwidth of the RS codec must be greater than the sum of the bandwidths of each channel. Otherwise, if the bandwidth of each channel is greater than the processing bandwidth of the RS codec, data will be lost. lost.

In another implementation manner in the embodiment of the present invention, the scheduling policy includes the following steps:

Poll the number of readable addresses in each buffer space, locate the channel with the largest readable address and a length greater than 1 codeword, and authorize the corresponding channel to obtain the next read operation permission.

In the specific operation, a read operation will continuously read the length of one RS codeword from one channel, because the RS code is a block code, and a codeword is an associated whole. If the encoding and decoding are not processed continuously, the intermediate operation state Staging processing would be too complicated.

In addition, this scheduling method with codewords as the basic unit will also bring additional benefits: because a read operation continues for multiple shots, the scheduling strategy for judging the next permission allocation operation can be completed in multiple shots. It is beneficial to the high-speed realization of digital circuits;

The scheduling policy is specifically: during a read operation, compare the number of readable addresses in the cache space of each channel, and the channel with the largest readable address and greater than a codeword length obtains the permission for the next read operation, or all channels are not When the authorization conditions are met, it enters the idle state.

The advantages brought by the scheduling policy in the embodiment of the present invention: 1. Because the authority for the next scheduling is allocated to the channel with the largest number of readable addresses in the buffer space in each channel, instead of a fixed ratio of the rate of each channel Therefore, it can ensure that the waterline of the buffer space of each channel is kept balanced, and there will be no abnormal phenomenon that the waterline of the buffer space of the channel will skyrocket or even overflow due to the uniform fluctuation of the data envelope of a channel; 2. Since the permission allocation for the next scheduling has been completed during the previous scheduling period, there can be no gap between the read operation scheduled for the previous time and the read operation scheduled for the next time, and bandwidth will not be wasted;

It should be noted that the waterline is a measure used to represent the total size of data stored in the cache space.

In another implementation in the embodiment of the present invention, before each channel receives the data frame and buffers it in the corresponding buffer space, the method further includes a data shaping process, and the data sorting process includes the following steps:

A1. Compare the data length of the data frame with the preset standard data length;

A2. When the data length of the data frame is consistent with the standard data length, the data frame is transmitted normally;

A3. When the data length of the data frame is greater than the standard data length, only the part of the data frame that conforms to the standard data length is transmitted;

A4. When the data length of the data frame is smaller than the standard data length, according to the preset compensation rule, the data length of the data frame is adjusted to the standard data length, and the adjusted data frame is transmitted.

Specifically, when the data length of the data frame is greater than the standard data length, only the part of the data frame that meets the standard data length is transmitted, and the part of the data frame that exceeds the standard data length is not transmitted, and the frame start indicator signal is detected. When starting the signal, compare the data length of the next data frame with the preset standard data length;

When the data length of the data frame is less than the standard data length, according to the preset compensation rule, delete the acquired frame start indication signal, adjust the data length of the data frame to the standard data length, and transmit the adjusted data frame;

The preset compensation rule may be such that the length of the data frame conforms to the standard data length without affecting the functional data in the data frame.

In the specific implementation, when performing the data shaping process, the specific operation method is: first define a shaping state machine, and the shaping state machine has three states: normal, truncated, compensated, the data frame in the normal state is output as it is, and the truncated state machine is The data frame in the short state is not output, and the data frame in the compensation state is also output as it is.

Among them, the initialization state is the truncated state, until the frame start indication signal is received to be valid, it means that the data frame enters the normal state. If in the normal state, the number of received data beats is continuously calculated, when theoretically the frame should appear If the position of the start indication signal actually appears, it will continue to maintain the normal state, otherwise it will enter the truncated state. If it is in the normal state, the position of the frame start indication signal should not appear in theory, but the frame start actually appears. Indication signal, which means that the frame length of the received data frame is less than the theoretical value, then the frame start indication valid signal is cleared first when outputting, and then the compensation state is entered, until the frame length reaches the theoretical value, then theoretically the frame should appear. The position of the starting valid indication is supplemented with a valid signal;

The result of the data shaping process is that the output frame is always a frame with a standard interval, which prevents the subsequent steps from entering an abnormal state due to abnormal frames.

In another implementation manner in the embodiment of the present invention, the method further comprises the following steps:

Perform the first delay processing on the data frame in the buffer space;

Specifically, the data frames in each buffer space are delayed according to work requirements.

In the specific implementation, the specific operation method of the first delay processing is as follows: firstly, the data valid indication signal is tapped, and the maximum number of taps is the configurable maximum number of delay beats, so that the optional output signal can be It is any one between the delay 1 beat and the configurable maximum delay beats. When actually outputting, select the delay beats corresponding to the actual configuration value.

The minimum configuration value of the delay should be greater than the maximum time required for the data frame of each channel from receiving, compiling, and then outputting, otherwise it will cause abnormal functions. By performing the first delay processing, it can be realized that the delay of each data frame passing through the multi-channel and multi-rate RS codec used for encoding and decoding in the embodiment of the present invention is a fixed value, and in addition, the output data envelope can be The input data envelope remains consistent and has the same uniformity, avoiding adverse impact on the cache of downstream modules.

In another implementation manner in the embodiment of the present invention, before correspondingly transmitting the encoded and decoded data frame to the corresponding output channel, the method further includes a data compensation process, and the data compensation process includes the following steps:

B1. Obtain the first delay value of the encoded and decoded data frame during the first delay processing, and denote it as T1;

B2. Obtain the data frame corresponding to the encoded and decoded data frame and store it in the buffer space at the beginning and the transmission delay value of the encoded and decoded data frame transmitted to the corresponding output channel, denoted as T2;

B3. Calculate the inherent delay value of the incoming channel corresponding to the encoded and decoded data frame, denoted as T3, T3=T2-T1;

B4. Perform delay compensation according to the inherent delay value corresponding to the encoded and decoded data frame.

It should be noted that, in actual operation, a compensation buffer space will be allocated to each channel, and after the data frame of each channel is encoded and decoded, a data compensation process will be performed in the corresponding supplementary buffer space.

In the embodiment of the present invention, the encoded and decoded data frames of each channel are written into the compensation buffer space. Due to the previous operation steps, the delay for the encoded and decoded data frames to reach the compensation buffer space is an indeterminate value. In order to make the delay of each data passing through the multi-channel multi-rate RS codec of the embodiment of the present invention to be a fixed value, it is necessary to wait for a period of time in the compensation buffer space before outputting the encoded data frame to compensate for the difference in delay value;

Furthermore, after the data compensation process ends, the encoded and decoded data frames processed by the data compensation process are output from the compensation buffer space.

Here, for the method mentioned in the embodiment of the present invention, a specific embodiment is given, and the 4-channel RS (255, 239) applied to the optical transmission network OTU2 and OTU4 is used as an example to illustrate, but it needs to be declared Yes, the present invention is also applicable to other occasions such as FlexE and FlexO that use RS codes.

4 is a flowchart of RS (255, 239) encoding and decoding supporting 4-channel OTU4/OTU2 access according to an embodiment of the present invention, including 4 OTU frame shaping modules, 4 buffer space modules, and 1 4-channel data valid indication signal Delay module, 1 4-channel RS (255, 239) code scheduling module, 1 RS (255, 239) codec module, 1 4-channel data distribution module, 4 compensation FIFO modules. in:

4 OTU frame shaping modules are used to organize data for 4 OTU4/OTU2 services, so that the frame interval is always a standard value. The 4 channels of the shaping module here all support OTU2 services with 10G bandwidth and OTU4 services with 100G bandwidth;

4 buffer space modules for buffering 4-way OTU4/OTU2 data services;

The 4-channel data valid indication signal delay module is used to delay the data valid indication signal for a configurable fixed period of time;

4-channel RS (255, 239) code scheduler module, used to read out RS (255, 239) code words from the buffer space, and output to the RS (255, 239) code and decoding module;

High-speed and high-parallel RS (255,239) codec module, where high-speed refers to the highest operating clock frequency of digital logic synthesis timing, high parallelism refers to the parallelism of encoding or decoding, and one clock beat requires processing For multiple RS symbols, for example, when the data bit width is 320 bits, one clock beat needs to process 320/8=40 RS (255,239) symbols, and the working clock frequency and parallelism jointly determine the maximum processing bandwidth of the codec;

4-channel data distribution module, used to distribute data to each channel according to the data channel number synchronized with the data;

4 compensation buffer spaces, each channel corresponds to one compensation buffer space, used to compensate the delay between the entry of the device of the present invention to the compensation buffer space and the fixed delay of the configured data from the entry to the exit of the device of the present invention The difference between the data is a fixed value after compensation, and the delay between the entrance and the exit of the device of the present invention is a fixed value. In addition, since the read enable of the compensation buffer space comes from the output of the data valid indication signal delay module, so It has the same envelope as the input data and also has consistent uniformity.

As shown in Figure 4, the specific implementation steps of the RS (255,239) encoding and decoding device supporting 4-channel OTU4/OTU2 service access:

C1 and 4 OTU frame shapers respectively shape the OTU4/OTU2 services of 4 channels of access;

C2 and 4 cache spaces respectively cache the shaped 4-way OTU4/OTU2 service data;

C3, 4-channel data valid indication signal delay module delays the envelope of 4-channel OTU4/OTU2 service data;

C4, the 4-channel RS (255, 239) code scheduler module reads the RS (255, 239) code word from the buffer space, and outputs it to the RS (255, 239) encoding and decoding module;

C5. The high-speed and high-parallel RS (255, 239) encoder or decoder module serially processes the service data from 4 channels, and performs RS (255, 239) encoding and decoding;

C6, 4-channel data distribution module will distribute data to parallel channels;

C7, write the 4 channel data output in step C6 into each corresponding compensation buffer space module;

C8. Use the delayed envelopes of each channel output in step C3 as a read enable, read data from the four compensation buffer space modules, and output them.

In the above steps, the internal processing flow of the 4-channel RS (255, 239) code scheduler module in step C4 is shown in Figure 5:

Step D1, initialization, scheduling to enter an idle state;

Step D2, polling each channel 0 to 3, when the number of readable addresses in the buffer space of a channel is greater than the length of an RS (255, 239) codeword, the channel obtains scheduling authorization and enters the scheduling state;

Step D3: During the scheduling process, determine the number of readable addresses in the buffer space of channels 0 to 3, find the channel with the largest and greater than one RS (255, 239) codeword length, and authorize it to be the object of the next scheduling , if there is no qualified authorization object, go to step D1.

In the frame structure of OTU4/OTU2 in the embodiment of the present invention, the OTUk frame has the same frame structure, and is composed of 4 rows and 4080 columns in total, and the unit is 1 RS (255, 239) symbol, that is, 8 bits,

Each row consists of 16 interleaved RS (255, 239) codewords, of which 1 to 3824 are information bits and 3825 to 4080 are check bits.

Based on the same inventive concept, the present application provides an embodiment of a coding and decoding system corresponding to Embodiment 1, and details are detailed in Embodiment 2

Embodiment 2

Referring to FIG. 6, an embodiment of the present invention provides a coding and decoding system, and the system includes:

A channel configuration unit 1, which is used to establish a plurality of independent channels, and each channel corresponds to a buffer space;

Data receiving unit 2, which is used to control each channel to receive data frames and buffer them into corresponding buffer spaces;

A data encoding and decoding unit 3, which is used to complete the transmission and encoding and decoding of data frames in each buffer space one buffer space at a time according to a preset scheduling strategy, wherein the transmission and encoding and decoding of data frames include:

A data frame in a buffer space is read, and transmitted to the RS codec to complete the encoding and decoding work of the data frame in the buffer space, and the encoded and decoded data frame is obtained.

In the embodiment of the present invention, a plurality of independent channels are first established, each channel is used to receive data from different senders, and each channel corresponds to a buffer space, that is, each channel is configured with its own dedicated cache space;

Further, each channel receives the transmitted data frame, and stores the respectively received data frame in the corresponding buffer space;

Finally, start the data encoding and decoding work. According to the preset scheduling policy, each time a data frame is obtained from a buffer space for transmission and encoding and decoding. The transmission and encoding and decoding of the data frame include:

A data frame in a buffer space is read, and transmitted to the RS codec to complete the encoding and decoding of the data frame in the buffer space, and the encoded and decoded data frame is obtained.

In addition, it should be noted that the transmission and compilation of data frames in each buffer space are completed one buffer space at a time. Since one data frame is obtained from one buffer space for transmission and compilation at a time, the data frame obtained this time is The data frame obtained next time can come from the same cache space or from different cache spaces, and the compilation work is done after multiple extractions and compilations, when the data in each cache space has been read completely. will end.

In the embodiment of the present invention, data frames are obtained from different sources by presetting mutually independent channels, and the data frames in multiple channels are compiled in batches, thereby realizing multi-channel encoding and decoding work and satisfying various work requirements. .

It should be noted that the coding and decoding work is mainly performed by the RS codec. The processing bandwidth of the RS codec must be greater than the sum of the bandwidths of each channel. Otherwise, if the bandwidth of each channel is greater than the processing bandwidth of the RS codec, data will be lost. lost.

In another implementation manner in the embodiment of the present invention, the scheduling strategy includes the following steps:

Poll the number of readable addresses in each buffer space, locate the channel with the largest readable address and a length greater than 1 codeword, and authorize the corresponding channel to obtain the next read operation permission.

In the specific operation, a read operation will continuously read the length of one RS codeword from one channel, because the RS code is a block code, and a codeword is an associated whole. If the encoding and decoding are not processed continuously, the intermediate operation state Staging processing would be too complicated.

In addition, this scheduling method with codewords as the basic unit will also bring additional benefits: because a read operation continues for multiple shots, the scheduling strategy for judging the next permission allocation operation can be completed in multiple shots. Conducive to the high-speed realization of digital circuits;

The scheduling policy is specifically: during a read operation, compare the number of readable addresses in the cache space of each channel, and the channel with the largest readable address and greater than a codeword length obtains the permission for the next read operation, or all channels are not When the authorization conditions are met, it enters the idle state.

In another implementation manner in the embodiment of the present invention, the system further includes a data preprocessing unit 4, which is configured to perform data shaping on each data frame before the data receiving unit receives the data frame of the data receiving unit;

Data preprocessing unit 4, which is specifically used to compare the data length of the data frame with the preset standard data length;

Data preprocessing unit 4, which is specifically used for normal transmission of the data frame when the data length of the data frame is consistent with the standard data length;

The data preprocessing unit 4 is specifically used to transmit the part of the data frame that meets the standard data length when the data length of the data frame is greater than the standard data length, and does not transmit the part of the data frame that exceeds the standard data length, and then, the next data The data length of the frame is compared with the preset standard data length;

Data preprocessing unit 4, which is specifically used to adjust the data length of the data frame to the standard data length according to the preset compensation rule when the data length of the data frame is less than the standard data length, and transmit the adjusted data frame;

The preset compensation rule may be such that the length of the data frame conforms to the standard data length without affecting the functional data in the data frame.

In another implementation manner in the embodiment of the present invention, the system further includes a time delay compensation unit 5, which is used for performing a data compensation process;

The delay compensation unit 5 is used to obtain the first delay value of the encoded and decoded data frame during the first delay processing, which is denoted as T1;

The delay compensation unit 5 is also used to obtain the transmission delay value of the data frame corresponding to the encoded and decoded data frame, which is stored in the buffer space at the beginning and the encoded and decoded data frame is passed into the corresponding output channel, which is denoted as T2;

The delay compensation unit 5 is also used to calculate the inherent delay value of the incoming channel corresponding to the encoded and decoded data frame, denoted as T3, T3=T2-T1;

The delay compensation unit 5 is further configured to perform delay compensation according to the inherent delay value corresponding to the encoded and decoded data frame.

Based on the same inventive concept, the present application provides an embodiment of the storage medium corresponding to Embodiment 1. For details, please refer to Embodiment 3

Embodiment 3

A third embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements all or part of the method steps in the first embodiment.

The present invention realizes all or part of the flow in the above-mentioned first embodiment, and can also be completed by instructing relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor , the steps of each of the foregoing method embodiments can be implemented. Wherein, the computer program includes computer program code, and the computer program code may be in the form of source code, object code, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying computer program code, recording medium, U disk, removable hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access Memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable media may be appropriately increased or decreased as required by the legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to the legislation and patent practice, the computer-readable media does not include Electrical carrier signals and telecommunication signals.

Based on the same inventive concept, the present application provides an embodiment of the device corresponding to the first embodiment. For details, please refer to the fourth embodiment.

Embodiment 4

A fourth embodiment of the present invention also provides a device, including a memory and a processor, the memory stores a computer program running on the processor, and when the processor executes the computer program, all the method steps or part of the method in the first embodiment are implemented step.

The so-called processor may be a central processing unit (Central Processing Unit, CPU), and may also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC) , Off-the-shelf programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The processor is the control center of the computer device, and uses various interfaces and lines to connect various parts of the entire computer device.

The memory can be used to store computer programs and/or modules, and the processor implements various functions of the computer device by running or executing the computer programs and/or modules stored in the memory and calling data stored in the memory. The memory can mainly include a stored program area and a stored data area, wherein the stored program area can store an operating system, an application program (such as a sound playback function, an image playback function, etc.) required for at least one function; The use of created data (such as audio data, video data, etc.) and so on. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, internal memory, plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, server or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein, including but not limited to disk storage, optical storage, and the like.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), servers and computer program products according to embodiments of the invention. It will be understood that each flow and/or block in the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce Means for implementing the functions specified in a flow or flow of a flowchart and/or a block or blocks of a block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions The apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.

These computer program instructions can also be loaded on a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that The instructions provide steps for implementing the functions specified in the flow or blocks of the flowcharts and/or the block or blocks of the block diagrams.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Thus, provided that these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims (10)

1. A method of coding and decoding, the method comprising the steps of:

establishing a plurality of independent channels, wherein each channel corresponds to a cache space;

each channel receives a data frame and caches the data frame to a corresponding cache space;

according to a preset scheduling strategy, completing the transmission and coding of data frames in each buffer space one buffer space at a time; wherein, the transmission and coding and decoding of the data frame comprises:

and reading a data frame in the cache space, transmitting the data frame to an RS codec, finishing the coding and decoding work of the data frame in the cache space, and obtaining a coded data frame.

2. The method of claim 1, wherein the scheduling policy comprises the steps of:

polling the number of the readable addresses in each cache space, positioning the channel with the maximum readable address and the length larger than 1 code word, and authorizing the corresponding channel to obtain the next read operation permission.

3. The method of claim 1, wherein before each of the lanes receives the data frame and buffers it to the corresponding buffer space, the method further comprises a data shaping process, the data grooming process comprising the steps of:

comparing the data length of the data frame with a preset standard data length;

when the data length of the data frame is consistent with the standard data length, the data frame is normally transmitted;

when the data length of the data frame is larger than the standard data length, only transmitting the part of the data frame conforming to the standard data length;

and when the data length of the data frame is smaller than the standard data length, adjusting the data length of the data frame to the standard data length according to a preset compensation rule, and transmitting the adjusted data frame.

4. The method of claim 3, wherein:

and when the data length of the data frame is greater than the standard data length, only transmitting the part of the data frame conforming to the standard data length, detecting a frame start indicating signal, and when the frame start indicating signal appears, comparing the data length of the next data frame with the preset standard data length.

5. The method of claim 3, wherein:

and when the data length of the data frame is smaller than the standard data length, deleting the acquired frame start indication signal according to a preset compensation rule, adjusting the data length of the data frame to the standard data length, and transmitting the adjusted data frame.

6. The method of claim 1, further comprising the steps of:

and carrying out first time delay processing on the data frame in the buffer space.

7. The method of claim 6, wherein prior to transmitting said compiled code data frames to a corresponding output channel, said method further comprises a data compensation process, said data compensation process comprising the steps of:

acquiring a first delay value of the compiled code data frame during the first delay processing, and recording the first delay value as T1;

acquiring a transmission delay value of the data frame corresponding to the compiled code data frame, which is stored in the cache space at the beginning and is transmitted into the corresponding output channel by the compiled code data frame, and recording the transmission delay value as T2;

calculating an inherent delay value of the incoming channel corresponding to the compiled code data frame, and recording the inherent delay value as T3, wherein T3 is T2-T1;

and performing delay compensation according to the inherent delay value corresponding to the coding and decoding data frame.

8. A coding system, the system comprising:

the channel configuration unit is used for establishing a plurality of independent channels, and each channel corresponds to a cache space;

the data receiving unit is used for controlling each channel to receive the data frame and buffer the data frame to the corresponding buffer space;

a data coding and decoding unit, configured to complete transmission and coding and decoding of data frames in each buffer space one buffer space at a time according to a preset scheduling policy, where the transmission and coding and decoding of the data frames include:

and reading a data frame in the cache space, transmitting the data frame to an RS codec, finishing the coding and decoding work of the data frame in the cache space, and obtaining a coded data frame.

9. The system of claim 8, wherein the scheduling policy comprises the steps of:

polling the number of the readable addresses in each cache space, positioning the channel with the maximum readable address and the length larger than 1 code word, and authorizing the corresponding channel to obtain the next read operation permission.

10. The system of claim 8, further comprising a data pre-processing unit for data shaping each data frame prior to the data receiving unit receiving the data frame;

the data preprocessing unit is specifically configured to compare the data length of the data frame with a preset standard data length;

the data preprocessing unit is specifically configured to, when the data length of the data frame is consistent with the standard data length, normally transmit the data frame;

the data preprocessing unit is specifically configured to transmit only a portion of the data frame that conforms to the standard data length when the data length of the data frame is greater than the standard data length;

the data preprocessing unit is specifically configured to, when the data length of the data frame is smaller than the standard data length, adjust the data length of the data frame to the standard data length according to a preset compensation rule, and transmit the adjusted data frame.

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