CN105793969A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

A semiconductor device, which is a semiconductor device having a source, a drain, a gate, and an amorphous silicon layer, characterized in that, between one or both of the source and the drain and the amorphous silicon layer In between, there is a thin film of electronic compound of amorphous oxide containing calcium atoms and aluminum atoms.

Description

Semiconductor device and method for manufacturing semiconductor device

technical field

The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background technique

In recent years, attention has been paid to semiconductor devices such as thin film transistors formed by forming electrodes such as a source, a drain, and a gate, and a semiconductor layer on an insulating substrate (for example, Patent Document 1). Such a semiconductor device can be applied to, for example, various electronic devices such as electro-optical devices.

prior art literature

patent documents

Patent Document 1: Japanese Patent Laid-Open No. 2007-123861

Contents of the invention

The problem to be solved by the invention

In the semiconductor device as described above, further reduction in contact resistance between the source and the semiconductor layer and between the drain and the semiconductor layer is required for further improvement in performance and functionality.

The present invention has been made in view of such a background, and an object of the present invention is to provide a semiconductor device that achieves higher performance and higher functionality than conventional ones. In addition, an object of the present invention is to provide a method of manufacturing such a semiconductor device.

means of solving problems

In the present invention, a semiconductor device is provided, which is a semiconductor device having a source, a drain, a gate and an amorphous silicon layer, characterized in that,

Between one or both of the source electrode and the drain electrode and the amorphous silicon layer, there is a thin film of an electron compound of an amorphous oxide containing calcium atoms and aluminum atoms.

Here, in the semiconductor device of the present invention, in the thin film of the electronic compound, the molar ratio (Ca/Al) of aluminum atoms to calcium atoms may be within a range of 0.3 to 5.0.

In addition, in the semiconductor device of the present invention, the thin film of the above-mentioned electronic compound may have an electron density of 2.0×10 ¹⁷ cm ⁻³ or more.

In addition, in the semiconductor device of the present invention, the thin film of the electronic compound may have a thickness of 100 nm or less.

In addition, in the semiconductor device of the present invention, the amorphous silicon layer may be disposed between the source and the gate, or

The amorphous silicon layer may be arranged on a side farther from the gate than the source.

In addition, in the present invention, a method for manufacturing a semiconductor device is provided, which is a method for manufacturing a semiconductor device having a source, a drain, a gate and an amorphous silicon layer, characterized in that it has:

(1) A step of forming a thin film of an electron compound of an amorphous oxide containing calcium atoms and aluminum atoms between one or both of the source electrode and the drain electrode and the amorphous silicon layer.

Here, the manufacturing method of the present invention also has

(a) the step of forming an amorphous silicon layer on the substrate,

(b) the step of forming source and drain electrodes, and

(c) the step of forming a gate, and

The above (1) step may be carried out between the above (a) step and the above (b) step.

In addition, the manufacturing method of the present invention also has

(a) a step of forming a source electrode and a drain electrode on a substrate,

(b) a step of forming an amorphous silicon layer, and

(c) the step of forming a gate, and

The above (1) step may be carried out between the above (a) step and the above (b) step.

In addition, the manufacturing method of the present invention also has

(a) a step of forming a gate on a substrate,

(b) a step of forming an amorphous silicon layer, and

(c) the step of forming source and drain electrodes, and

The above (1) step may be carried out between the above (b) step and the above (c) step.

In addition, the manufacturing method of the present invention also has

(a) a step of forming a gate on a substrate,

(b) the step of forming source and drain electrodes, and

(c) the step of forming an amorphous silicon layer, and

The above (1) step may be carried out between the above (b) step and the above (c) step.

In addition, in the production method of the present invention, in the thin film of the electronic compound, the molar ratio (Ca/Al) of aluminum atoms to calcium atoms may be within a range of 0.3 to 5.0.

In addition, in the production method of the present invention, the thin film of the above-mentioned electronic compound may have an electron density of 2.0×10 ¹⁷ cm ⁻³ or more.

In addition, in the production method of the present invention, the thickness of the thin film of the electronic compound may be 100 nm or less.

It should be noted that, in this application, "the electronic compound of amorphous oxide containing calcium atoms and aluminum atoms" is also referred to simply as "the electronic compound of amorphous oxide", and "the electronic compound containing calcium atoms and aluminum atoms" is also referred to as "the electronic compound of amorphous oxide". "Thin film of electronic compound of amorphous oxide" is simply referred to as "thin film of electronic compound".

Invention effect

In the present invention, it is possible to provide a semiconductor device that achieves higher performance and higher functionality than conventional ones. In addition, in the present invention, a method of manufacturing such a semiconductor device can be provided.

Description of drawings

FIG. 1 is a cross-sectional view schematically showing the configuration of a conventional semiconductor device.

FIG. 2 is a schematic diagram showing a conceptual structure of an electron compound of an amorphous oxide.

3 is a cross-sectional view schematically showing the structure of a semiconductor device according to an embodiment of the present invention.

4 is a cross-sectional view schematically showing an example of a semiconductor device of the present invention configured in a top-gate structure-bottom contact system.

5 is a cross-sectional view schematically showing an example of a semiconductor device of the present invention configured in a bottom gate structure-top contact system.

6 is a cross-sectional view schematically showing an example of a semiconductor device of the present invention configured in a bottom-gate structure-bottom contact system.

FIG. 7 is a diagram schematically showing an example of a flow for manufacturing a semiconductor device according to an embodiment of the present invention.

detailed description

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

First, in order to better understand the features of the present invention, the configuration of a conventional semiconductor device will be briefly described with reference to FIG. 1 .

FIG. 1 shows a schematic cross section of a conventional semiconductor device.

As shown in FIG. 1 , a conventional semiconductor device 1 has a substrate 10 , an amorphous silicon layer 5 , a source 20 , a drain 22 and a gate 24 .

The amorphous silicon layer 5 is disposed on the upper portion of the substrate 10 , and the source 20 and the drain 22 are disposed on the upper portion of the amorphous silicon layer 5 . A gate 24 is disposed on top of the source 20 and the drain 22 via a gate insulating layer 30 .

Such a semiconductor device 1 can be used, for example, in electro-optical devices such as liquid crystal panels and electronic paper, light-emitting display devices, and the like.

Here, in the conventional semiconductor device 1, in order to further improve performance and functionality, it is required to reduce the contact resistance at the interface between the source electrode 20 and the amorphous silicon layer 5 and the contact resistance between the drain electrode 11 and the amorphous silicon layer 5. The contact resistance at the interface. This is because when the contact resistance at this interface increases, the operating characteristics of the semiconductor device 1 deteriorate.

Usually, it is effective to use an ohmic contact to suppress the contact resistance at the interface between the metal source 20 /drain 22 and the amorphous silicon layer 5 . Ohmic contact refers to the state where the metal and semiconductor are joined without forming a space charge layer on the side of the amorphous silicon layer. In this case, rectification does not occur at the metal/semiconductor interface (that is, electrons flow in two directions) .

However, in order to exhibit such an ohmic contact at the interface between the metal source 20/drain 22 and the amorphous silicon layer 5, it is necessary to make the work function of the source 20/drain 22 smaller than the work function of the amorphous silicon layer 5. . However, generally, there are not many metallic materials having such a work function. In addition, a metal with a low work function is active, has high reactivity, and easily forms a reaction layer with other components, so it is difficult to directly bond a metal with a low work function to an amorphous silicon layer. Therefore, in such countermeasures, there arises a problem that the materials of the source electrode 20 and the drain electrode 22 are greatly limited.

On the other hand, when the work function of the metal source 20 and drain 22 is larger than that of the amorphous silicon layer 5 , a Schottky barrier is formed at the metal/amorphous silicon interface. In this case, it is considered to make the space charge layer generated on the amorphous silicon side as thin as possible, and to suppress the contact resistance through the tunnel effect. However, in order to thin the space charge layer, it is necessary to significantly increase the carrier density in the amorphous silicon layer. Therefore, this method sometimes cannot be a realistic coping strategy.

In contrast, the present invention provides a semiconductor device having a source, a drain, a gate, and an amorphous silicon layer, characterized in that

Between one or both of the source electrode and the drain electrode and the amorphous silicon layer, there is a thin film of an electron compound of an amorphous oxide containing calcium atoms and aluminum atoms.

The semiconductor device of the present invention is characterized in that a thin film of an electron compound of an amorphous oxide containing calcium atoms and aluminum atoms is disposed between one or both of the source electrode and the drain electrode and the amorphous silicon layer.

Here, a thin film of an electronic compound of an amorphous oxide containing calcium atoms and aluminum atoms has the characteristics of exhibiting the electrical characteristics of a semiconductor and having a low work function. For example, the work function of the film is in the range of 2.4 eV to 4.5 eV (eg, 2.8 eV to 3.2 eV). In addition, this thin film is characterized by high electron density. The electron density of the thin film is, for example, in the range of 2.0×10 ¹⁷ cm ⁻³ to 2.3×10 ²¹ cm ⁻³ .

In the semiconductor device of the present invention, the contact resistance between one or both of the source electrode and the drain electrode and the amorphous silicon layer can be significantly reduced due to the presence of such a thin film. Therefore, in the present invention, it is possible to provide a semiconductor device having higher operating characteristics than conventional ones.

The present invention is more effective when the work function of the source and the drain are larger than the work function of the amorphous silicon layer.

As described above, by making the work function of the source and drain lower than that of the amorphous silicon layer, an ohmic contact can be exhibited. However, a metal with a low work function is active, has high reactivity, and easily forms a reaction layer with other components, so it is difficult to express an ohmic contact. The thin film of the electronic compound of the present invention has high chemical durability despite having a low work function, and also has a high carrier density (electron density). Therefore, an ohmic contact can be expressed between the amorphous silicon layer and the thin film of the electronic compound, and a tunnel effect can be expressed between the source and drain (metal). As a result, the contact resistance between one or both of the source and the drain and the amorphous silicon layer can be significantly reduced, thereby providing a higher-performance semiconductor device than before.

The work function of the thin film of the electron compound is preferably smaller than that of the amorphous silicon layer. The difference between the work function of the amorphous silicon layer and the work function of the thin film of the electron compound is preferably greater than 0 eV and less than or equal to 3.0 eV, more preferably 0.1 eV to 2.5 eV, and still more preferably 0.5 eV to 2.0 eV. By having such a difference in work function, ohmic contact can be easily expressed, and contact resistance can be significantly reduced.

For example, the work function of the amorphous silicon layer is 4.2eV. When aluminum (Al) is used as the source and drain, the work function of the source and drain including Al is 4.1 eV. In this case, when one or both of the source electrode and the drain electrode are directly bonded to the amorphous silicon layer, a reaction layer is generated and ohmic contact is not easily expressed. In contrast, in the present invention, a thin film of an electron compound of an amorphous oxide containing calcium atoms and aluminum atoms is disposed between one or both of the source and drain electrodes and the amorphous silicon layer. The work function of the electron compound thin film is in the range of 2.4 eV to 4.5 eV, for example, can be set in the range of 2.8 eV to 3.2 eV, and can be sufficiently lower than the work function of the amorphous silicon layer. Also, the thin film of the electron compound is chemically stable, so it is not easy to form a reactive layer. In addition, at the interface between the source electrode and the drain electrode (metal) and the thin film of the electronic compound, the electron density of the thin film of the electronic compound is high, so the contact resistance is reduced by utilizing the tunneling effect. Therefore, ohmic contact is easily expressed, and the contact resistance between one or both of the source and the drain and the amorphous silicon layer can be reduced. As a result, semiconductor devices with higher performance than before can be provided.

In addition, when the difference between the electron affinity and the work function of the thin film of the electronic compound is ΔF, and the difference between the electron affinity and the work function of the amorphous silicon layer is ΔB, the difference between ΔF and ΔB is preferably close to 0. For example, the absolute value of the difference between ΔF and ΔB is preferably 0.5 or less, more preferably 0.3 or less, and still more preferably 0. By reducing the absolute value of the difference between ΔF and ΔB as much as possible, when the amorphous silicon layer and the thin film of the electronic compound are bonded, the energy levels at the bottom of the respective conduction bands are aligned, so the interaction between the amorphous silicon layer and the electronic compound can be reduced. Contact resistance between films. When the electron affinity of the thin film of the electron compound is about 2.5 eV and the work function is about 3.0 eV, ΔF is about 0.5 eV. When the electron affinity of the amorphous silicon layer is about 3.9 eV and the work function is about 4.2 eV to about 4.8 eV, ΔB is 0.3 eV to 0.9 eV. In this case, the difference between ΔF and ΔB is about 0.4 or less, and very low contact resistance can be formed. By reducing the contact resistance between the amorphous silicon layer and the electron compound thin film, the contact resistance between one or both of the source and drain electrodes and the amorphous silicon layer can be reduced. As a result, semiconductor devices with higher performance than before can be provided.

Thin films of electronic compounds can have high ionization potentials. The ionization potential of the thin film of the electronic compound may be 7.0 eV to 9.0 eV, or may be 7.5 eV to 8.5 eV.

In addition, it is preferable that the ionization potential of the thin film of the electron compound is higher than that of the amorphous silicon layer. The ionization potential difference between the thin film of the electron compound and the amorphous silicon layer may be 1.1 eV to 3.5 eV, or may be 1.3 eV to 3.3 eV, or may be 1.6 eV to 3.0 eV.

In addition, it is more preferable that the difference between the ionization potential and the work function of the thin film of the electronic compound is larger than the difference between the ionization potential and the work function of the amorphous silicon layer. For example, let the difference (IP-WF) between the ionization potential (IP) and the work function (WF) of the thin film of the electronic compound be ΔE. Let the difference between the ionization potential (IP) and the work function (WF) of the amorphous silicon layer be ΔA. The difference (ΔE−ΔA) between the two is preferably 1.3 eV to 5.8 eV, more preferably 2.0 eV to 5.0 eV, particularly preferably 2.5 eV to 4.5 eV.

For example, when the semiconductor device of the present invention is a thin-film field-effect transistor, when the transistor is turned off (when the gate voltage is 0 or a negative voltage is applied as the gate voltage), holes are conducted to the source, sometimes generating cut-off current (leakage current). The generation of cut-off current may cause an increase in power consumption or the like.

However, as described above, the thin film of the electron compound has a high ionization potential, and the ionization potential is sufficiently large compared to the amorphous silicon layer, especially when the difference between the ionization potential and the work function is sufficiently large compared to the amorphous silicon layer, excellent performance can be obtained. hole blocking effect. This is because the difference (ΔE-ΔA) between the ionization potential difference (ΔE) of the thin film of the electron compound and the difference (ΔA) between the ionization potential and the work function of the amorphous silicon layer becomes an energy barrier in hole conduction. . By having a sufficiently high energy barrier, hole conduction can be blocked, so that off-current can be suppressed.

It should be noted that the following configuration is known: in the conventional semiconductor device 1 shown in FIG. An amorphous silicon layer (n ⁺ amorphous silicon layer) doped with a high concentration of n-type impurity elements. For the n ⁺ amorphous silicon layer, depending on the doping concentration of the impurity element, the work function becomes smaller than that of the amorphous silicon layer not doped with the impurity element, but the ionization potential itself does not change. Therefore, the energy barrier (the difference between the ionization potential and the work function of the n ⁺ amorphous silicon layer and the difference between the ionization potential and the work function of the amorphous silicon layer) can only be about 0.5 eV at most.

On the other hand, by providing a thin film of an electronic compound having a high ionization potential as described above between one or both of the source and the drain and the amorphous silicon layer, the off-state current can be further reduced.

(Definition of terms)

Here, terms related to the "thin film of an electronic compound of an amorphous oxide containing calcium atoms and aluminum atoms" included in the semiconductor device of the present invention will be described in advance.

(Electronic Compound of Amorphous Oxide)

In this application, "an electronic compound of an amorphous oxide containing calcium atoms and aluminum atoms", that is, "an electronic compound of an amorphous oxide" refers to an amorphous compound composed of calcium atoms, aluminum atoms and oxygen atoms as a solvent , A solvated amorphous solid substance with electrons as the solute. The electrons in the amorphous oxide function as anions. Electrons can also exist as bipolarons.

The structure of the electronic compound of the amorphous oxide is conceptually shown in FIG. 2 .

As shown in FIG. 2 , the electron compound 70 of an amorphous oxide has a characteristic partial structure called a bipolaron 74 dispersed in a solvent 72 including an amorphous structure composed of calcium atoms, aluminum atoms, and oxygen atoms. status exists. The bipolaron 74 is constituted by two adjacent cages 76 and electrons (solute) 78 contained in each cage 76 . However, the state of the amorphous oxide is not limited to the above, and two electrons (solutes) 78 may be included in one cage 76 . In addition, a plurality of these cages may be aggregated, and aggregated cages may also be regarded as microcrystals, so a state in which crystallites are included in amorphous is also regarded as amorphous in the present invention.

In the present invention, the electronic compound of the amorphous oxide may contain a compound selected from Sr, Mg, Ba, Si, Ge, Ga, in addition to calcium atoms, aluminum atoms, and oxygen atoms within the range of maintaining the cage structure of the bipolaron. One or more atoms in the group consisting of , In and B. In addition, one or more atoms selected from the group consisting of Ti, V, Cr, Mn, Fe, Co, Ni, and Cu, and one or more atoms selected from the group consisting of Li, Na, and K may be contained. , or one or more atoms selected from the group consisting of Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, and Yb.

In addition, in the present invention, the electron compound of the amorphous oxide may be a compound in which two electrons contained in two cages are replaced by other anions. Examples of other anions include one or more anions selected from the group consisting of H ^- , H ₂ ^- , H ^2- , O ^- , O ₂ ^- , OH ^- , F ^- , Cl ^- and S ^2- .

(thin films of electronic compounds)

A thin film of an electronic compound exhibits electrical characteristics of a semiconductor and has a low work function. The work function may be 2.4eV-4.5eV, preferably 2.8eV-3.2eV. In addition, thin films of electronic compounds have high ionization potentials. The ionization potential may be 7.0 eV to 9.0 eV, or may be 7.5 eV to 8.5 eV.

The bipolaron hardly absorbs light in the range of visible light with photon energy of 1.55 eV to 3.10 eV, and exhibits light absorption near 4.6 eV. Therefore, the thin film of the electronic compound of the present invention is transparent under visible light. In addition, by measuring the light absorption characteristics of the thin film sample, by measuring the light absorption coefficient around 4.6eV, it can be confirmed whether there are bipolarons in the thin film sample, that is, whether the thin film sample has electron compounds of amorphous oxide.

In the present invention, the molar ratio (Ca/Al) of aluminum atoms to calcium atoms in the thin film of the electronic compound is preferably in the range of 0.3 to 5.0. When it is 0.3 or more, a high electron density can be maintained. Moreover, when it is 5.0 or less, the durability of a film is excellent. More preferably, it exists in the range of 0.55-1.2, Especially preferably, it exists in the range of 0.6-1.00. The composition analysis of the thin film can be performed by XPS method, EPMA method, or EDX method. When the film thickness is less than 100nm, it can be analyzed by the XPS method, when it is more than 50nm, it can be analyzed by the EPMA method, and when it is more than 3μm, it can be analyzed by the EDX method.

When the thin film of the electronic compound in the present invention is measured by X-ray diffraction, no peak is observed, and only a halo is observed. In the present invention, the thin film of the electronic compound may contain microcrystals. Whether or not microcrystals are contained in the thin film can be judged from, for example, a cross-sectional TEM (transmission electron microscope) photograph of the thin film. The composition in the crystal state is represented by 12CaO.7Al ₂ O ₃ , CaO.Al ₂ O ₃ , 3CaO.Al ₂ O ₃ and the like.

In the present invention, in the thin film of the electronic compound, the light absorption value at the position of 4.6 eV may be 100 cm ^-1 or more, and may be 200 cm ^-1 or more.

In the present invention, the thin film of the electron compound preferably contains electrons with an electron density in the range of 2.0×10 ¹⁷ cm ⁻³ to 2.3×10 ²¹ cm ⁻³ . The electron density is more preferably 1.0×10 ¹⁸ cm ⁻³ or higher, still more preferably 1×10 ¹⁹ cm ⁻³ or higher, particularly preferably 1×10 ²⁰ cm ⁻³ or higher.

In addition, the electron density of the thin film of an electron compound can be measured by the iodine titration method. In addition, the density of bipolarons in the thin film of the electron compound can be calculated by multiplying the measured electron density by 1/2.

This iodine titration method is a method of immersing a sample of a thin film of an electronic compound in a 5 mol/l iodine aqueous solution, adding hydrochloric acid to dissolve it, and then measuring the amount of unreacted iodine contained in the solution with sodium thiosulfate. Perform a titration test. In this case, by the dissolution of the sample, the iodine in the iodine aqueous solution is ionized by the following reaction:

I ₂ +2e ^- →2I ^- (1) formula

In addition, when titrating an aqueous solution of iodine with sodium thiosulfate,

pass

2Na ₂ S ₂ O ₃ +I ₂ →2NaI+Na ₂ S ₄ O ₆ (2) formula

The unreacted iodine is converted into sodium iodide. The amount of iodine consumed in the reaction of the formula (1) was calculated by subtracting the amount of iodine detected by the titration of the formula (2) from the amount of iodine present in the initial solution. Thereby, the electron density in the sample of the thin film of the electron compound can be measured.

In the present invention, the thickness of the thin film of the electron compound is not limited thereto, and may be, for example, 100 nm or less, preferably 10 nm or less, more preferably 5 nm or less. It may be 0.5 nm or more.

Thin films of electronic compounds are electrically conductive by hopping conduction of electrons in cages. The direct current conductivity of the thin film of the electronic compound of the present invention at room temperature may be 10 ^-11 S·cm ^-1 to 10 ^-1 S·cm ^-1 , and may also be 10 ^-7 S·cm ^-1 to 10 ^{- 3} S·cm ^-1 .

A thin film of an electron compound may have, in addition to bipolarons 74 , an F ⁺ center in which one electron is trapped in an oxygen vacancy as a local structure. The F ⁺ center is composed of multiple Ca ²⁺ ions surrounding one electron and does not have a cage. The F ⁺ center is centered at 3.3eV, and has light absorption in the range of visible light from 1.55eV to 3.10eV.

When the concentration of F ⁺ centers is less than 5×10 ¹⁸ cm ^-3 , the transparency of the film is improved, which is preferable. The concentration of F ⁺ centers is more preferably 1×10 ¹⁸ cm ⁻³ or less, still more preferably 1×10 ¹⁷ cm ⁻³ or less. It should be noted that the concentration of F ⁺ centers can be measured from the signal intensity of g value 1.998 in ESR.

In the thin film of the electron compound, the ratio of the light absorption coefficient at the photon energy position of 3.3 eV to the light absorption coefficient at the photon energy position of 4.6 eV may be 0.35 or less.

Compared with polycrystalline thin films, thin films of electronic compounds have excellent flatness because they do not have grain boundaries. The root-mean-square roughness (RMS) of the surface of the thin film of the electronic compound of the present invention may be 0.1 nm to 10 nm, or may be 0.2 nm to 5 nm. When the RMS is 2 nm or less, the characteristics of the device are improved, which is more preferable. In addition, when the RMS is 10 nm or more, there is a possibility that the characteristics of the device may be degraded, so that an additional polishing step or the like may be required. The above RMS can be measured, for example, using an atomic force microscope.

The composition of the electron compound thin film may be different from the stoichiometric ratio of 12CaO·7Al ₂ O ₃ , or may be different from the composition ratio of the target used in the production.

(Regarding the semiconductor device of one embodiment of the present invention)

Next, a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 3 . FIG. 3 schematically shows a cross section of a semiconductor device (first semiconductor device) 100 according to an embodiment of the present invention.

As shown in FIG. 3 , the first semiconductor device 100 has a substrate 110 , an amorphous silicon layer 105 , a source 120 , a drain 122 and a gate 124 .

The amorphous silicon layer 105 is disposed on the upper portion of the substrate 110 , and the source 120 and the drain 122 are disposed on the upper portion of the amorphous silicon layer 105 . A gate 124 is disposed on top of the source 120 and the drain 122 via a gate insulating layer 130 .

Here, the first semiconductor device 100 has the following characteristics: Between the source electrode 120 and the amorphous silicon layer 105, and/or between the drain electrode 122 and the amorphous silicon layer 105, an amorphous layer containing calcium atoms and aluminum atoms is arranged. The thin film of the electron compound of the oxide (thin film of the electron compound) 150 .

For example, in the example of FIG. 3, the thin film 150a of the first electron compound is arranged between the source electrode 120 and the amorphous silicon layer 105, and the thin film 150b of the second electron compound is arranged between the drain electrode 122 and the amorphous silicon layer 105. .

As described above, the thin films 150a and 150b of such electronic compounds have characteristics such as small work function and high electron density.

Therefore, when the thin film 150a of the first electron compound is arranged between the source electrode 120 and the amorphous silicon layer 105, the effect of significantly suppressing the contact resistance at the interface between the source electrode 120 and the amorphous silicon layer 105 can be obtained. Similarly, when the thin film 150b of the second electron compound is arranged between the drain electrode 122 and the amorphous silicon layer 105, the contact resistance at the interface between the drain electrode 122 and the amorphous silicon layer 105 can be significantly suppressed.

Therefore, the first semiconductor device 100 can exhibit significantly higher operating characteristics than conventional ones.

(Constituent Members of Semiconductor Device 100)

Next, each member constituting the semiconductor device 100 will be briefly described.

(Substrate 110)

The material of the substrate 110 is not particularly limited. The substrate 110 may be an insulating substrate such as a glass substrate, a ceramic substrate, a plastic substrate, and a resin substrate.

Alternatively, the substrate 110 may be a semiconductor substrate or a metal substrate with an insulating layer formed on the surface.

(amorphous silicon layer 105)

The amorphous silicon layer 105 may be made of ordinary amorphous silicon. The amorphous silicon layer 105 can be made of, for example, hydrogenated amorphous silicon. In addition, the amorphous silicon layer 105 is preferably an intrinsic semiconductor.

(source 120, drain 122)

The material of the source electrode 120 and the drain electrode 122 is not particularly limited as long as it has conductivity. The source 120 and the drain 122 can be made of metal, for example.

The source electrode 120 and the drain electrode 122 may be, for example, an alloy containing at least one element selected from Al, Ag, Au, Cr, Cu, Ta, Ti, Mo, and W. The source electrode 120 and the drain electrode 122 can also be made of, for example, ITO, antimony oxide (Sb ₂ O ₃ ), zirconium oxide (ZrO ₂ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), IZO (IndiumZincOxide) , AZO (ZnO-Al ₂ O ₃ : zinc oxide doped with aluminum), GZO (ZnO-Ga ₂ O ₃ : zinc oxide doped with gallium), Nb-doped TiO ₂ , Ta-doped TiO ₂ And IWZO (In ₂ O ₃ -WO ₃ -ZnO: indium oxide doped with tungsten trioxide and zinc oxide) and other metal oxide materials.

The work function of the amorphous silicon layer 105 may be 3.5eV˜4.8eV, or may be 3.9eV˜4.5eV.

The carrier density of the amorphous silicon layer 105 may be 10 ⁹ cm ^-3 to 10 ¹⁹ cm ^-3 , preferably 10 ¹⁵ cm ^-3 to 10 ¹⁸ cm ^-3 .

(gate 124)

The material of the gate 124 is not particularly limited as long as it has conductivity.

The gate 124 may be, for example, an element selected from Al, Ag, Au, Cr, Cu, Ta, Ti, Mo, and W, or a metal or an alloy composed of these elements, or an alloy combining the above elements. The gate 124 can be made of, for example, ITO, antimony oxide (Sb ₂ O ₃ ), zirconium oxide (ZrO ₂ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), IZO (IndiumZincOxide), AZO (ZnO- Al ₂ O ₃ : zinc oxide doped with aluminum), GZO (ZnO-Ga ₂ O ₃ : zinc oxide doped with gallium), Nb-doped TiO ₂ , Ta-doped TiO ₂ and IWZO (In ₂ O ₃ -WO ₃ -ZnO: Indium oxide doped with tungsten trioxide and zinc oxide) and other metal oxide materials.

The gate insulating layer 130 may be made of inorganic insulating materials such as silicon oxide, silicon nitride, nitrogen-containing silicon oxide, and oxygen-containing silicon nitride, or organic insulating materials such as acrylic or polyimide.

Alternatively, the gate insulating layer 130 may also be made of the following material: a skeleton structure is formed by the bonding of silicon and oxygen, and at least an organic group containing hydrogen (such as an alkyl group, an aryl group) and a fluorine group are used as substituents, That is, it is composed of so-called siloxane-based materials.

The gate insulating layer 130 may be a single layer, or may be composed of two or more layers.

(About the structure of semiconductor device)

The first semiconductor device 100 shown in FIG. 3 has a so-called top-gate structure-top-contact structure. However, the arrangement structure of each member constituting the semiconductor device is not limited to this.

Here, there are, for example, (i) top gate structure-top contact system, (ii) top gate structure-bottom contact system, (iii) bottom gate structure-top contact system, and (iii) bottom gate structure-top contact system among the arrangement structures of the constituent members of the semiconductor device. ) Bottom gate structure - bottom contact method, etc.

Hereinafter, these arrangement structures will be briefly described.

An example of a semiconductor device 100 configured in a top gate structure-top contact system is shown in FIG. 3 described above.

As shown in FIG. 3 , in the semiconductor device 100, the gate 124 is disposed on the top of the amorphous silicon layer 105 (top gate structure), and the source 120 and the drain 122 are also disposed on the top of the amorphous silicon layer 105 (top gate structure). way of contact). It should be noted that, in the semiconductor device 100 , the amorphous silicon layer 105 may be of a channel etching type or of a channel protection type.

Next, FIG. 4 shows an example of a semiconductor device configured in a top gate structure-bottom contact system.

As shown in FIG. 4 , the semiconductor device 400 has an amorphous silicon layer 405 formed on a substrate 410 , a source 420 and a drain 422 , a gate insulating layer 430 and a gate 424 .

In this example, the gate 424 is arranged on the upper portion of the amorphous silicon layer 405 (top gate structure). On the other hand, the source electrode 420 and the drain electrode 422 are arranged on the lower side of the amorphous silicon layer 405 (bottom contact method).

It should be noted that, in the example of the semiconductor device 400 shown in FIG. 4 , the thin film 450a of the first electronic compound is disposed between the source electrode 420 and the amorphous silicon layer 405, and the thin film 450a of the first electron compound is disposed between the drain electrode 422 and the amorphous silicon layer. A thin film 450b of the second electron compound is disposed between 405 . Wherein, one of the thin film 450a of the first electronic compound and the thin film 450b of the second electronic compound may be omitted.

Next, FIG. 5 shows an example of a semiconductor element configured in a bottom gate structure-top contact system.

As shown in FIG. 5 , the semiconductor device 500 has an amorphous silicon layer 505 , a source 520 and a drain 522 , a gate insulating layer 530 and a gate 524 on a substrate 510 .

In this example, the gate electrode 524 is arranged on the lower side of the amorphous silicon layer 505 (bottom gate structure). On the other hand, the source electrode 520 and the drain electrode 522 are arranged on the upper side of the amorphous silicon layer 505 (top contact method). It should be noted that, in the semiconductor device 500, the amorphous silicon layer 505 may be of a channel etching type or of a channel protection type.

It should be noted that, in the example of semiconductor device 500 shown in FIG. A thin film 550b of the second electron compound is disposed therebetween. Wherein, one of the thin film 550a of the first electronic compound and the thin film 550b of the second electronic compound may be omitted.

Next, FIG. 6 shows an example of a semiconductor element configured by a bottom gate structure-bottom contact system.

As shown in FIG. 6 , the semiconductor device 600 has an amorphous silicon layer 605 , a source 620 and a drain 622 , a gate insulating layer 630 and a gate 624 on a substrate 610 .

In this example, the gate 624 is arranged on the lower side of the amorphous silicon layer 605 (bottom gate structure). On the other hand, the source electrode 620 and the drain electrode 622 are also arranged on the lower side of the amorphous silicon layer 605 (bottom contact method).

In the example of the semiconductor device 600 shown in FIG. 6, the thin film 650a of the first electron compound is arranged between the source electrode 620 and the amorphous silicon layer 605, and the second electron compound thin film 650a is arranged between the drain electrode 622 and the amorphous silicon layer 605. Thin film 650b of electronic compound. Wherein, one of the thin film 650a of the first electronic compound and the thin film 650b of the second electronic compound may be omitted.

It can be seen that there are various modes in the structure of the semiconductor device. The semiconductor device of the present invention can be configured in these modes. In the semiconductor device of the present invention, it is apparent that in any of these constitutions, the contact resistance can be significantly suppressed at the interface between the source electrode and the amorphous silicon layer and/or the interface between the drain electrode and the amorphous silicon layer. Effect.

In addition, in the present invention, the type of semiconductor device is not particularly limited. The semiconductor device may be, for example, a field effect transistor such as a thin film transistor shown in FIGS. 3 to 6 .

(About the manufacturing method of the semiconductor device of the present invention)

Next, an example of a method of manufacturing the first semiconductor device 100 shown in FIG. 3 will be described with reference to FIG. 7 .

An example of the flow at the time of manufacturing the first semiconductor device is schematically shown in FIG. 7 . As shown in Figure 7, the manufacturing method has:

The step of forming an amorphous silicon layer on the substrate (step S110),

A step of forming a thin film of an electronic compound of an amorphous oxide containing calcium atoms and aluminum atoms (step S120),

the step of forming source and drain (step S130), and

A step of forming a gate (step S140).

Each step will be described below. In addition, in the following description, the reference numerals shown in FIG. 3 are used for each member for clarification.

(step S110)

First, an amorphous silicon layer 105 is formed on a substrate 110 .

The film-forming method of the amorphous silicon layer 105 is not particularly limited, and the amorphous silicon layer 105 can be formed on the substrate 110 by a conventionally practiced method.

The amorphous silicon layer 105 is formed on the substrate 110 by, for example, a general CVD method (plasma CVD method, etc.), a sputtering method, or the like.

The formed amorphous silicon layer 105 is patterned into a desired pattern. For example, the amorphous silicon layer 105 can be patterned into a desired pattern by performing photolithography or the like.

(step S120)

Next, a thin film of an electron compound is formed on the amorphous silicon layer 105 . The thin film of the electronic compound then becomes the thin film 150a of the first electronic compound and/or the thin film 150b of the second electronic compound.

As an example, as a film-forming method of a thin film of an electronic compound, a film-forming method having the following steps will be described:

a step of preparing a target of a crystalline C12A7 electron compound having an electron density of 2.0×10 ¹⁷ cm ^-3 to 2.3×10 ²¹ cm ^-3 (S121), and

A step of forming a film on the amorphous silicon layer by vapor deposition in an atmosphere having an oxygen partial pressure of less than 0.1 Pa using the target ( S122 ).

(step S121)

First, a target for film formation to be used in the subsequent step S120 is prepared.

The target consists of a crystalline C12A7 electron compound.

(Crystalline C12A7)

In the present application, "crystalline C12A7" means a crystal of 12CaO·7Al ₂ O ₃ and an isotype compound having a crystal structure equivalent thereto. The mineral name of this compound is "Mayenite".

The crystalline C12A7 in the present invention may be a compound in which a part or all of the Ca atoms and/or Al atoms of the C12A7 crystal skeleton are replaced by other atoms within the scope of maintaining the cage structure formed by the skeleton of the crystal lattice, and the compound in the cage. A compound of the same type in which some or all of the free oxygen ions are replaced by other anions. In addition, C12A7 is sometimes expressed as Ca ₁₂ Al ₁₄ O ₃₃ or Ca ₂₄ Al ₂₈ O ₆₆ .

The compound of the same type is not limited thereto, and the following compounds (1) to (5) can be illustrated, for example.

(1) An isotype compound in which a part or all of Ca atoms in a crystal are replaced by one or more metal atoms selected from the group consisting of Sr, Mg and Ba. For example, strontium aluminate Sr ₁₂ Al ₁₄ O ₃₃ is a compound in which part or all of Ca atoms are replaced by Sr, and calcium strontium aluminate Ca _12-x Sr _X is a mixed crystal in which the mixing ratio of Ca and Sr can be changed arbitrarily. Al ₁₄ O ₃₃ (x is an integer of 1 to 11; in the case of an average value, a number greater than 0 and less than 12) and the like.

(2) An isotype compound in which part or all of the Al atoms in the crystal are replaced by one or more atoms selected from the group consisting of Si, Ge, Ga, In, and B. For example, _{Ca12Al10Si4O35 etc.} are _{mentioned .}

(3) Part of the metal atoms and/or non-metal atoms (excluding oxygen atoms) in the crystal of 12CaO·7Al ₂ O ₃ (comprising the compounds of (1) and (2) above) and a part selected from Ti, V, One or more atoms selected from the group consisting of Cr, Mn, Fe, Co, Ni, and Cu, one or more alkali metal atoms selected from the group consisting of Li, Na, and K, or one or more atoms selected from the group consisting of Ce, Pr, Nd, An isotype compound obtained by substituting one or more rare earth atoms in the group consisting of Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, and Yb.

(4) A compound in which a part or all of the free oxygen ions included in the cage are replaced by other anions. As other anions, there are, for example, one or more anions selected from the group consisting of H ^- , H ₂ ^- , H ^2- , O ^- , O ₂ ^- , OH ^- , F ^- , Cl ^- and S ² , nitrogen ( N) anions, etc.

(5) A compound in which part of the oxygen in the skeleton of the cage is replaced by nitrogen (N) or the like.

(crystalline C12A7 electron compound)

In the present application, "crystalline C12A7 electronic compound" refers to, in the above-mentioned "crystalline C12A7", free oxygen ions contained in cages (in the case of other anions contained in cages, this anion) in which part or all of the electrons are replaced.

In crystalline C12A7 electron compounds, clathrate electrons are loosely bound in cages, allowing them to move freely in the crystal. Therefore, the crystalline C12A7 electronic compound exhibits electrical conductivity. In particular, crystalline C12A7 in which all free oxygen ions are replaced by electrons is sometimes expressed as [Ca ₂₄ Al ₂₈ O ₆₄ ] ⁴⁺ (4e ^- ).

The crystalline C12A7 electron compound contains Ca atoms, Al atoms and O atoms, the molar ratio of Ca:Al is in the range of 13:13 to 11:15, and the molar ratio of Ca:Al is preferably in the range of 12.5:13.5 to 11.5:14.5 , more preferably within the range of 12.2:13.8 to 11.8:14.2.

The method of producing the target made of crystalline C12A7 electronic compound is not particularly limited. The target can be produced, for example, using a conventional method for producing a bulk crystalline C12A7 electron compound. For example, crystalline C12A7 can be produced by heating a sintered body of crystalline C12A7 to about 1150 to about 1460°C, preferably about 1200 to about 1400°C in the presence of a reducing agent such as Ti, Al, Ca, or C. Targets made of electronic compounds. A green compact obtained by compressing a powder of a crystalline C12A7 electronic compound may also be used as a target. By heating the sintered body of crystalline C12A7 at 1230 to 1415°C in the presence of carbon and metallic aluminum while keeping the sintered body and the metallic aluminum in a non-contact state, it is possible to efficiently produce large-area crystalline C12A7 electrons. compound targets.

Here, the electron density of the crystalline C12A7 electron compound which is the target is in the range of 2.0×10 ¹⁷ cm ⁻³ to 2.3×10 ²¹ cm ⁻³ . The electron density of the crystalline C12A7 electron compound is preferably 1×10 ¹⁸ cm ^-3 or more, preferably 1×10 ¹⁹ cm ^-3 or more, more preferably 1×10 ²⁰ cm ^-3 or more, and even more preferably 5×10 ²⁰ cm ^-3 or more, particularly preferably 1×10 ²¹ cm ^-3 or more. The higher the electron density of the crystalline C12A7 electron compound constituting the target, the easier it is to obtain a thin film of the electron compound having a lower work function. In particular, in order to obtain a thin film of an electron compound having a work function of 3.0 eV or less, the electron density of the crystalline C12A7 electron compound is more preferably 1.4×10 ²¹ cm ^-3 or more, still more preferably 1.7×10 ²¹ cm ^-3 or more, especially Preferably it is 2×10 ²¹ cm ^-3 or more. In particular, the electron density of the crystalline C12A7 electron compound reaches 2.3×10 ²¹ cm ^-3 when all free oxygen ions (the anions in the case of other anions) are replaced by electrons. When the electron density of the crystalline C12A7 electron compound is lower than 2.0×10 ¹⁷ cm ⁻³ , the electron density of the thin film of the electron compound obtained by film formation decreases.

The electron density of the crystalline C12A7 electron compound can be measured by light absorptiometry. The crystalline C12A7 electron compound has a unique light absorption around 2.8eV, so by measuring its absorption coefficient, the electron density can be obtained. In particular, when the sample is a sintered body, it is convenient to use the diffuse reflection method after pulverizing the sintered body into powder.

The obtained target is used as a raw material source when forming a thin film of an electronic compound in a subsequent step.

It should be noted that the surface of the target may be polished by mechanical means or the like before use. In general, a bulk body of a crystalline C12A7 electron compound obtained by a conventional method may have an extremely thin film (foreign substance) on the surface. When the film-forming process is performed using a target having such a film formed on the surface as it is, there is a possibility that the composition of the obtained thin film deviates from the desired composition ratio. However, such problems can be remarkably suppressed by performing polishing treatment on the target surface in advance.

(step S122)

Next, a film is formed on the amorphous silicon layer by vapor deposition using the target produced in the above-mentioned step S121.

In this application, the "vapor deposition method" refers to a method of vaporizing a target raw material and depositing the raw material on a substrate, including physical vapor deposition (PVD) method, PLD method, sputtering method, and vacuum evaporation method. General term for membrane methods.

Among the "vapor-phase vapor deposition methods", the sputtering method is particularly preferable. A relatively uniform thin film can be formed over a large area by sputtering. It should be noted that the sputtering method includes: DC (direct current) sputtering method, high frequency sputtering method, helicon wave sputtering method, ion beam sputtering method, magnetron sputtering method and the like.

Hereinafter, step S122 will be described by taking the case of forming a film by sputtering as an example.

The temperature of the substrate to be filmed when forming the thin film of the electronic compound is not particularly limited, and any temperature in the range of room temperature to 700° C., for example, can be employed. It should be noted that when forming a thin film of an electronic compound, it is necessary to pay attention that it is not necessarily necessary to "actively" heat the substrate. However, the temperature of the substrate to be filmed may sometimes rise "accidentally" due to radiant heat from the vapor deposition source. For example, the temperature of the substrate to be filmed may be 500°C or lower, or may be 200°C or lower.

When the substrate to be filmed is not "actively" heated, materials such as glass and plastic whose heat resistance decreases at high temperatures exceeding 700° C. can be used as the substrate material.

The oxygen partial pressure during film formation (oxygen partial pressure in the chamber) is preferably less than 0.1 Pa. The oxygen partial pressure is preferably 0.01 Pa or less, more preferably 1×10 ^-3 Pa or less, still more preferably 1×10 ^-4 Pa or less, particularly preferably 1×10 ^-5 Pa or less. When the oxygen partial pressure is 0.1 Pa or more, there is a possibility that oxygen enters the thin film after film formation, thereby reducing the electron density.

On the other hand, the hydrogen partial pressure during film formation is preferably less than 0.004 Pa. When it is 0.004 Pa or more, there is a possibility that hydrogen or OH components enter into the thin film after film formation, thereby reducing the electron density of the thin film of the electron compound.

The sputtering gas used is not particularly limited. The sputtering gas can be an inert gas or a rare gas. As an inert gas, _N2 gas is mentioned, for example. In addition, examples of the rare gas include He (helium), Ne (neon), Ar (argon), Kr (krypton), and Xe (xenon). These can be used alone or in combination with other gases. Alternatively, the sputtering gas may be a reducing gas such as NO (nitrogen monoxide).

The pressure of the sputtering gas (pressure in the chamber) is not particularly limited, and can be freely selected to obtain a desired thin film. In particular, when the distance between the substrate and the target is t (m) and the diameter of the gas molecule is d (m), the pressure P (Pa) of the sputtering gas (pressure in the chamber)

can satisfy

8.9×10 ^-22 /(td ² )＜P＜4.5×10 ^-20 /(td ² )(3) formula

way to choose. In this case, the mean free path of the sputtered particles is substantially equal to the distance between the target and the film-forming substrate, and the reaction between the sputtered particles and the residual oxygen is suppressed. Also, in this case, an inexpensive and simple vacuum device with a relatively high back pressure can be used as the device for the sputtering method.

In the above, the method of forming a thin film of an electronic compound has been briefly described by taking the sputtering method as an example. However, the film-forming method of the electronic compound thin film is not limited to this, and it is obvious that the above-mentioned two steps (steps S121 and S122 ) can be appropriately changed or various steps can be added.

For example, in the above-mentioned step S122, the target may be subjected to pre-sputtering treatment (dry etching treatment of the target) by the sputtering method before starting the formation of the thin film of the electron compound.

By performing the pre-sputtering treatment, the surface of the target is cleaned, and a thin film having a desired composition can be easily formed in the subsequent film formation treatment (main film formation).

For example, when the target is used for a long time, oxygen may enter the surface of the target, and the electron density of the crystalline C12A7 electron compound constituting the target may decrease. When such a target is used, there is a possibility that the electron density may decrease even in the formed thin film. In addition, when the target is used for a long time, the composition of the target may deviate from the original composition due to the difference in the sputtering speed of each component constituting the target (that is, the crystalline C12A7 electron compound). When such a target is used, there is a possibility that the composition may deviate from the desired value even in the formed thin film. However, such problems can be suppressed by performing pre-sputtering treatment.

It should be noted that the gas used in the pre-sputtering treatment may be the same as or different from the sputtering gas used in the actual film formation. In particular, the gas used in the pre-sputtering treatment is preferably He (helium), Ne (neon), N ₂ (nitrogen), Ar (argon), and/or NO (nitrogen monoxide).

In this way, a thin film of an electron compound is formed on the patterned amorphous silicon layer 105 .

Thereafter, the thin film of the electron compound is patterned into a desired pattern by photolithography or the like, whereby the first and/or second thin film of the electron compound 150a, 150b can be formed.

The thin film of the electronic compound is preferably heat-treated after patterning. The heat treatment temperature is preferably 300°C or higher, more preferably 500°C or higher. The temperature is set to be lower than the tolerable temperature of the coating film and the film-forming substrate, preferably 700° C. or lower. The retention time at the predetermined temperature may be 1 minute to 2 hours, or may be 10 minutes to 1 hour. In addition, the timing of the heat treatment can be after patterning the thin film of the electronic compound, or after forming the source and drain electrodes on the thin film of the electronic compound (such as the example in Figure 3), or forming an amorphous layer on the thin film of the electronic compound. After the silicon layer (such as the example in Figure 4)). By performing heat treatment, recovery can be achieved when the thin film of the neutral electron compound is damaged during patterning or the like.

(step S130)

Next, the source electrode 120 and the drain electrode 122 are formed on the upper portions of the first and/or second electron compound thin films 150a, 150b.

For the formation of the source electrode 120 and the drain electrode 122 , various conventional methods can be used.

The source electrode 120 and the drain electrode 122 can be formed by forming a conductive layer for forming the source electrode 120 and the drain electrode 122 into a film, and then performing a film photolithography process or the like.

Here, the source electrode 120 is arranged on the thin film 150a of the first electron compound, and/or the drain electrode 122 is arranged on the thin film 150b of the second electron compound.

Thus, the contact resistance of the interface between the source electrode 120 and the amorphous silicon layer 105 and/or the interface between the drain electrode 122 and the amorphous silicon layer 105 is reduced.

In the cross-sectional view of FIG. 3 , an example of a portion of the amorphous silicon layer 105 not in direct contact with the source electrode 102 and/or the drain electrode 122 is schematically shown. However, in the present invention, as long as the contact resistance can be reduced by the presence of the electron compound thin film, there may be a portion where the amorphous silicon layer is in direct contact with the source and/or drain. For example, a thin film of an amorphous silicon layer and an electronic compound is continuously formed and patterned collectively by photolithography. The side surfaces of the pattern of the amorphous silicon layer are easily formed so that they are not covered with the thin film of the electron compound. Next, source and drain electrodes are formed on the thin film of the electron compound. At this time, the side surfaces of the pattern of the amorphous silicon layer may be formed to be in contact with the source and the drain.

(step S140)

Next, a gate insulating film 130 is formed to cover the source electrode 120 and the drain electrode 122 .

The gate insulating film 130 can be formed by a coating method such as a dipping method, a spin coating method, a droplet discharge method, a casting method, a spin method, a printing method, a CVD method, or a sputtering method.

After that, the gate electrode 124 is formed on the gate insulating film 130 . For the formation of the gate electrode 124, various methods conventionally practiced can be utilized. For example, the gate electrode 124 can be formed by a sputtering method, an evaporation method, or the like. The gate electrode 124 can be formed by forming a conductive layer for forming the gate electrode 124 into a film, and then performing a photolithography process of the film or the like.

Through the above steps, the first semiconductor device 100 can be manufactured.

It should be noted that, in the above description, an example of the method of manufacturing the semiconductor device of the present invention has been described by taking the first semiconductor device 100 shown in FIG. 3 as an example.

However, it is obvious to those skilled in the art that the semiconductor device 400 , the semiconductor device 500 , and the semiconductor device 600 can be manufactured according to the same method. That is, semiconductor devices of various structures can be manufactured by changing the order of the steps shown in FIG. 7 .

Industrial applicability

The present invention can be applied to, for example, semiconductor devices and the like used in various electronic devices such as electro-optical devices. For example, it can be used in electronic equipment such as monitors such as televisions, electrical appliances such as washing machines and refrigerators, and information processing equipment such as mobile phones and computers. In addition, the semiconductor device of the present invention can also be used in electronic equipment included in automobiles, various industrial equipment, and the like.

This application claims the priority based on the JP Patent application 2013-268342 for which it applied on December 26, 2013, The whole content of this JP application is used for this application by reference.

reference sign

1 Existing semiconductor devices

5 layer of amorphous silicon

10 substrates

20 source

22 drain

24 gates

30 gate insulating layer

70 Electron compounds of amorphous oxides

72 solvent (amorphous)

74 bipolarons

76 cages

78 electrons (solute)

100The first semiconductor device

105 amorphous silicon layer

110 substrate

120 source

122 drain

124 grid

130 grid insulating layer

Thin films of 150a, 150b electronic compounds

400, 500, 600 semiconductor devices

405, 505, 605 amorphous silicon layer

410, 510, 610 substrate

420, 520, 620 source

422, 522, 622 drain

424, 524, 624 grid

430, 530, 630 gate insulating layer

Thin films of 450a, 450b, 550a, 550b, 650a, 650b electronic compounds

Claims (13)

1. a semiconductor device, it is the semiconductor device with source electrode, drain electrode, grid and amorphous silicon layer, it is characterised in that

Between the one or both and described amorphous silicon layer of described source electrode and described drain electrode, there is the thin film containing calcium atom and the electron compound of the amorphous oxides of aluminum atom.

2. semiconductor device as claimed in claim 1, wherein, in the thin film of described electron compound, the mol ratio (Ca/Al) of aluminum atom and calcium atom is in the scope of 0.3～5.0.

3. semiconductor device as claimed in claim 1 or 2, wherein, the thin film of described electron compound has 2.0 × 10¹⁷cm^-3Above electron density.

4. the semiconductor device as according to any one of claims 1 to 3, wherein, the thickness of the thin film of described electron compound is below 100nm.

5. the semiconductor device as according to any one of Claims 1 to 4, wherein,

Described amorphous silicon layer is arranged between described source electrode and described grid, or

Described amorphous silicon layer is arranged in than the described source electrode side further from described grid.

6. a manufacture method for semiconductor device, it is the manufacture method of the semiconductor device with source electrode, drain electrode, grid and amorphous silicon layer, it is characterised in that have:

Between the one or both and described amorphous silicon layer of described source electrode and described drain electrode, form the step containing calcium atom and the thin film of the electron compound of the amorphous oxides of aluminum atom.

7. manufacture method as claimed in claim 6, wherein, described manufacture method also has:

(a) formed on substrate amorphous silicon layer step,

(b) formed source electrode and drain electrode step and

C () forms the step of grid；And

Between described (a) step and described (b) step, it is implemented between the one or both of described source electrode and described drain electrode and described amorphous silicon layer and forms the step containing calcium atom and the thin film of the electron compound of the amorphous oxides of aluminum atom.

8. manufacture method as claimed in claim 6, wherein, described manufacture method also has:

(a) formed on substrate source electrode and drain electrode step,

(b) formed amorphous silicon layer step and

C () forms the step of grid；And

Between described (a) step and described (b) step, it is implemented between the one or both of described source electrode and described drain electrode and described amorphous silicon layer and forms the step containing calcium atom and the thin film of the electron compound of the amorphous oxides of aluminum atom.

9. manufacture method as claimed in claim 6, wherein, described manufacture method also has:

(a) formed on substrate grid step,

(b) formed amorphous silicon layer step and

C () forms the step of source electrode and drain electrode；And

Between described (b) step and described (c) step, it is implemented between the one or both of described source electrode and described drain electrode and described amorphous silicon layer and forms the step containing calcium atom and the thin film of the electron compound of the amorphous oxides of aluminum atom.

10. manufacture method as claimed in claim 6, wherein, described manufacture method also has:

(a) formed on substrate grid step,

(b) formed source electrode and drain electrode step and

C () forms the step of amorphous silicon layer；And

Between described (b) step and described (c) step, it is implemented between the one or both of described source electrode and described drain electrode and described amorphous silicon layer and forms the step containing calcium atom and the thin film of the electron compound of the amorphous oxides of aluminum atom.

11. the manufacture method as according to any one of claim 6～10, wherein, in the thin film of described electron compound, the mol ratio (Ca/Al) of aluminum atom and calcium atom is in the scope of 0.3～5.0.

12. the manufacture method as according to any one of claim 6～11, wherein, the thin film of described electron compound has 2.0 × 10¹⁷cm^-3Above electron density.

13. the manufacture method as according to any one of claim 6～12, wherein, the thickness of the thin film of described electron compound is below 100nm.