JP6517535B2 - Silicon-based thin film semiconductor device and method of manufacturing silicon-based thin film semiconductor device - Google Patents

Description

  The present invention relates to a thin film semiconductor device which realizes a reduction in leakage current and a reduction in power consumption, and a method of manufacturing a silicon-based thin film semiconductor device.

  A so-called n + Si layer is used for the source and drain electrodes of a silicon-based thin film transistor (TFT) that performs n-ch operation. Here, the n + Si layer is manufactured by adding a large amount of phosphorus (P) or arsenic (As) which is an n-type impurity to silicon (Si).

  For example, in the case of amorphous Si, it refers to a low-resistance silicon layer (n + a-Si: H) manufactured by adding (doping) a large amount of n-type impurities (doping) during the plasma CVD film formation step. In addition, in the case of polycrystalline Si, it refers to a low resistance silicon layer (n + poly Si) manufactured by adding a large amount of phosphorus using an ion doping apparatus.

  In these n + Si layers, the barrier for the electrons of carriers during n-ch operation is extremely small and exhibits good ohmic junction characteristics (see, for example, Non-Patent Document 1).

Patent 4245608 gazette

SID Information Display, 2014 March / April, Vol. 30, No. 2 pp26-29 by John Wager

However, the prior art has the following problems.
As described above, the n + Si layer exhibits good ohmic contact characteristics with respect to electrons of carriers during n-ch operation. On the other hand, for holes induced in the channel layer of a TFT under negative gate bias, the n + Si layer is amorphous silicon, microcrystalline silicon, or polycrystalline silicon, so the barrier to holes is Low, "hole current" will flow.

  The "leakage current" caused by the "hole current" is a major obstacle to improving the performance of the TFT liquid crystal display. However, with the current technology, there is no method that can reduce the hole current.

  FIG. 17 is a schematic vertical sectional view of an amorphous silicon semiconductor thin film transistor (a-Si: H.TFT) which is a typical silicon type thin film semiconductor field effect transistor in the related art. Here, the amorphous Si layer (n + a-Si: H) of the source electrode and the drain electrode must be in contact with the a-Si: H layer.

  Also in the microcrystalline Si TFT, the same structure in which the channel layer Si and the n + Si layer are in contact is employed.

  Ion doping is used in low temperature polycrystalline Si (so-called LTPS) TFTs that are typical of polycrystalline Si. Because of this, the n + LTPS layer is embedded in the channel layer, but the principle for the inflow and outflow of electrons is exactly the same.

  FIG. 18 is a diagram showing comparison of leak current under negative gate bias at the time of n-ch operation of each semiconductor TFT. As a well-known phenomenon, as shown in FIG. 18, the leakage current is the largest in the LTPS-TFT, and in the order of a-Si: H.TFT and then IGZO (In-Ga-Zn-O) -TFT.

  The characteristic of the oxide semiconductor TFT typified by IGZO lies in this small leak current, and Sharp Co. claims that the performance of the liquid crystal display can be improved by adopting this IGZO-TFT. For example, performance can be realized such that the storage capacity can be reduced, as a result, the aperture ratio can be increased, or the refresh rate can be reduced.

  The problem of the prior art is that the leak current is large, and reducing the leak current of LTPS-TFT or a-Si: H.TFT by one digit or two digits contributes to the improvement of the performance of the TFT liquid crystal display. .

  Here, the cause of the occurrence of the problem of the prior art that the leak current is large is known. Specifically, the leak current represented by the amorphous silicon semiconductor TFT is caused by the hole current induced in the channel layer in the semiconductor under negative gate bias. And, in the present n + Si layer, this hole current can not be blocked completely.

  The reason for the generation of holes is related to the size and physical properties of the band gap of the semiconductor. And, in the semiconductor typified by IGZO, this gap is as large as about 3.3 eV and no hole is induced.

  On the other hand, the silicon-based semiconductor a-Si: H has a gap of 1.7 eV, and the LTPS has a gap of about 1.1 eV, which is a relatively small band gap. Therefore, under positive and negative gate voltages, electrons and holes are easily induced in the semiconductor film, resulting in a phenomenon that the hole current can not be completely blocked. FIG. 19 is an explanatory view showing two generation paths of the leak current. Among these phenomena, the channel leak current is the physical property of the semiconductor itself, and there is no means to avoid it. On the other hand, the leak current flowing through the insulating layer is reduced to a value that is not problematic due to the minimization technology of the overlapping area of the electrodes and the improvement of the film quality.

  In summary, in a-Si: H.TFT and LTPS-TFT, holes are induced under negative gate bias. However, in the prior art, the hole-induced current, that is, the leak current can not be completely blocked in the n + a-Si: H layer or the n + LTPS layer.

  FIG. 20 is a schematic vertical cross-sectional view of a specific amorphous silicon semiconductor thin film transistor for explaining the problem that a hole current flows due to other factors. As shown in FIG. 20, depending on the electrode material and the etching material used at the time of fabrication, for example, when the etching rate of Mo in the barrier layer is high, the top Al is directly n + Si, depending on the electrode material and the etching material used during fabrication. It happens to touch the layer.

  When Al directly contacts the n + Si layer, Al and Si react with each other through the heat treatment step, and the n + Si layer is replaced with the p + Si layer. The reason is that Al is an acceptor impurity for Si. When a part of the electrode is a p + Si layer, the “hole current” generated under negative gate bias flows, and the leakage current further increases.

  Therefore, in manufacturing, advanced techniques are required for the combination of electrode material selection and etching techniques.

  The present invention has been made to solve the problems as described above, and it is an object of the present invention to provide a silicon-based thin film semiconductor device and an silicon-based thin film semiconductor device provided with an electrode structure that realizes reduction of leakage current and reduction of power consumption. The purpose is to obtain a manufacturing method.

  A silicon-based thin film semiconductor device according to the present invention has a band gap equal to or more than three times the band gap of crystalline silicon, and a material having electrical conductivity by the movement of electrons or holes, with a source electrode and a drain electrode, respectively. And the silicon-based thin film.

In the method of manufacturing a silicon-based thin film semiconductor device according to the present invention, a source electrode having a band gap equal to or more than three times the band gap of crystalline silicon and having electrical conductivity due to movement of electrons or holes is provided. A method of manufacturing a silicon-based thin film semiconductor device provided between each of a drain electrode and a silicon-based thin film, comprising the steps of: laminating amorphous electride C12A7: e ⁻ on a silicon-based thin film; Forming a source electrode and a drain electrode while laminating the low resistance electrode wiring material on the crystalline electride C12A7: e ⁻ and preventing the low resistance electrode wiring material from contacting the silicon-based thin film It is.

According to the present invention, a substance having electron conduction, a small work function, and a large band gap, represented by amorphous electride C12A7: e ⁻ , is used as a part of the electrode material of the source-drain electrode of silicon-based TFT. By using it, the leak current caused by holes is reduced. By adopting such an electrode structure, in the a-Si: H.TFT, the process of manufacturing the n + a-Si: H layer using the PE-CVD apparatus becomes unnecessary, and in the polycrystalline Si.TFT, The process of manufacturing the n + Si layer using the ion doping apparatus is not necessary. Furthermore, by reducing the leakage current, in the TFT-LCD, the aperture ratio can be improved, in other words, the power consumption can be reduced. As a result, it is possible to realize a silicon-based thin film semiconductor device provided with an electrode structure that achieves a reduction in leakage current and a reduction in power consumption, and a method of manufacturing a silicon-based thin film semiconductor device.

It is the figure which showed the band structure of amorphous C12A7: e < ^- > used in Embodiment 1 of this invention as a comparison with another material. It is an explanatory view for showing a manufacturing method of junction at the time of verifying a diode characteristic in Embodiment 1 of the present invention, and a measuring method of electrical property. It is a figure which shows the electrical property result measured using the 1st sample and 2nd sample in P-type silicon in Embodiment 1 of this invention. It is a figure which shows the electrical property result measured using the 1st sample and the 2nd sample in N type silicon in Embodiment 1 of this invention. It is the figure which put together the specification of SOI used by the 2nd verification in Embodiment 1 of the present invention. It is an explanatory view for showing a measuring method of TFT structure and electrical property at the time of performing the 2nd inspection in Embodiment 1 of the present invention. It is a figure which shows the electrical property result measured using the 3rd sample which has a C12 A7: e < ^- > layer in Embodiment 1 of this invention. It is a figure which shows the electrical property result measured using the 4th sample which does not have a C12 A7: e < ^- > layer in Embodiment 1 of this invention. It is a longitudinal cross-section schematic diagram of typical a-Si: H * TFT in Embodiment 1 of this invention. It is a figure which shows what is called a transfer characteristic of the silicon-type thin film semiconductor device in Embodiment 1 of this invention. FIG. 1 is a schematic vertical sectional view of a silicon-based thin film semiconductor device having an electrode structure of Example 1 in Embodiment 1 of the present invention. It is a typical longitudinal cross-sectional view of the silicon system thin film semiconductor device which has an electrode structure of Example 2 in Embodiment 1 of the present invention. It is a typical longitudinal cross-sectional view of the silicon system thin film semiconductor device which has an electrode structure of Example 3 in Embodiment 1 of the present invention. FIG. 7 is an explanatory drawing showing a manufacturing step of the silicon-based thin film semiconductor device according to manufacturing method 1 in Embodiment 1 of the present invention. FIG. 7 is an explanatory drawing showing a manufacturing step of the silicon-based thin film semiconductor device according to manufacturing method 2 in Embodiment 1 of the present invention. FIG. 7 is an explanatory drawing showing a manufacturing step of the silicon-based thin film semiconductor device according to manufacturing method 3 in Embodiment 1 of the present invention. It is a typical longitudinal cross-sectional view of the amorphous silicon semiconductor thin-film transistor (a-Si: H * TFT) which is a typical of the conventional silicon-based thin film semiconductor field effect transistor. It is the figure which showed the comparison of the leakage current under negative gate bias at the time of n-ch operation | movement of each semiconductor TFT. It is explanatory drawing which showed two generation | occurrence | production paths of leakage current. It is a schematic longitudinal cross-sectional view of the specific amorphous silicon semiconductor thin-film transistor for demonstrating the problem which a hole current flows.

  Hereinafter, preferred embodiments of a silicon-based thin film semiconductor device and a method of manufacturing a silicon-based thin film semiconductor device according to the present invention will be described with reference to the drawings.

Embodiment 1
First, the gist of the present invention will be described. “Electride C12A7: e ⁻ ” (for example, see Patent Document 1) invented by Professor Hideo Hosono of Tokyo Institute of Technology is a chemically stable (inactive) ceramic. And "amorphous C12A7" formed by sputtering also has electron conduction, a small work function and a large band gap, which are physical properties of electride. Therefore, this “amorphous C12A7: e ⁻ ” is a new material having the possibility of realizing an OLED with a low driving voltage by using it as an electron injection layer of an organic EL light emitting element (OLED).

Accordingly, the present inventors, C12A7: e ^- physical structure and electrical properties of amorphous C12A7: e ^- a silicon (amorphous silicon, microcrystalline silicon, polycrystalline silicon) thin film field effect transistor ( By using it as a part of source-drain electrode material of TFT), it discovered the possibility that the leak current resulting from a hole could be reduced.

  The source of this leakage current is mainly the current due to holes induced in the channel under negative gate bias during n-ch operation of the TFT, as described above. Currently, the hole current can not be completely blocked only by the n + Si layer used for the source / drain electrode.

  The inventors of the present invention investigated and studied a junction structure of a semiconductor capable of blocking the hole current which is a problem. The candidate semiconductor material has a band gap of three times or more that of Si, and the carrier is an electron, and it is a necessary condition that a semiconductor junction with Si can be easily formed. For example, the band gap of gallium nitride (GaN) is as large as about 3.4 eV, so that n-type GaN can be formed, but a semiconductor junction can not be easily formed with Si.

And, since the present inventors have found that amorphous C12A7: e ⁻ has a small work function of 3.1 eV and a large band gap of more than 5 eV, it has an ohmic property to electrons and holes. It was found from experiments that it had a block effect against. Furthermore, the present inventors have actually produced an n-ch operation TFT using SOI (Silicon on Insulator), and confirmed that holes can be blocked by the amorphous C12A7: e ^- material. The present invention is created based on these verification results.

  Therefore, based on the above summary, a silicon-based thin film semiconductor device and a method of manufacturing the silicon-based thin film semiconductor device according to the present invention will be described in detail.

Possible wide band gap semiconductor materials that can block the hole current include, for example, GaN or β-Ga ₂ O ₃ . However, these materials are merely nitride films having lost semiconductor characteristics in a method such as sputter film formation, and are only oxide films.

FIG. 1 is a view showing the band structure of amorphous C12A7: e ⁻ used in the first embodiment of the present invention as a comparison with other materials. Electride C12A7: e ^- is be deposited by sputtering, the amorphous ^{C12A7: e - (a-C12A7} : e -) maintains the cage structure clathrate electrons, shown in FIG. 1 Likely, it is guessed to have a band structure.

Specifically, electride in the amorphous state maintains a cage structure in which electrons of the composition 12CaO · 7Al ₂ O ₃ are included, and as a result, it becomes an electroconductive substance by electrons having physical properties as electride. It is considered that the function is maintained.

Amorphous C 12 A 7: e ⁻ is smaller than Al and Mo in work function (WF), and is approximately 3.1 eV. Furthermore, if this amorphous C 12 A 7: e ⁻ is applied to Si, it should be ohmic against n-type Si having electron conduction, as inferred from semiconductor physics.

On the other hand, amorphous C12A7: e ⁻ has a high barrier (barrier) to holes because the value of work function is small and it is a wide band gap semiconductor exceeding 5 eV. It can be inferred that the flow of holes (hole current) can be blocked.

Here, a-C12A7: e ^- when the bond the Si, what phenomenon occurs, the point of the present invention. This junction forms a so-called "heterojunction" according to semiconductor physics. And, the electrical junction characteristic inferred from the work function and the band gap exhibits a low barrier against electron movement, that is, an ohmic characteristic, and a high barrier against hole movement, that is, a blocking effect. It is considered to exhibit so-called diode characteristics.

The present inventors clarified that the structure in which a-C12A7: e ^- and Si are joined has this diode characteristic from the experiment as the first verification, and applies this characteristic to a field effect thin film transistor, It has also been clarified from experiments as a second verification that it has a hole blocking effect.

Therefore, first, a C12A7: e ⁻ / Si structure that will form a heterojunction is fabricated, and a first verification that is confirmed to exhibit the hole blocking effect, that is, “diode characteristics” will be described in detail.

FIG. 2 is an explanatory view showing a method of manufacturing a junction and a method of measuring an electrical characteristic when the diode characteristic in the first embodiment of the present invention is verified. The back surface side of the P-type silicon wafer or N-type silicon wafer, by sputtering an Al-Nd, while the surface side, C12A7: e ^- a first sample having the, C12A7: e ^- no second The sample and each were produced.

  Then, the voltage Vd was changed from -5 V to +5 V in 0.2 V steps, and the current value Id at that time was measured to verify the diode characteristics. This experimental result is the origin of the present invention.

  FIG. 3 is a diagram showing the results of electrical characteristics measured using the first and second samples of P-type silicon according to the first embodiment of the present invention, and FIG. 4 is a diagram according to the first embodiment of the present invention It is a figure which shows the electrical property result measured using the 1st sample and 2nd sample in N type silicon.

Incidentally, in FIGS. 3 and 4, "CA Yes" is the surface side C12A7: e ^- means first sample is formed, "CA Mu" is the surface side C12A7: e ^- has not been formed Not mean the second sample. In FIGS. 3 and 4, the left half corresponding to the range of −5 V to 0 V on the horizontal axis shows the current flowing from the surface side to the back side on the vertical axis, and the horizontal axis in the range of 0 V to +5 V The corresponding right half shows the current flowing from the back side to the front side on the vertical axis.

As shown in FIG. 3, by providing a C12A7: e ⁻ layer on the surface side of P-type Si, good diode characteristics (rectification characteristics) were obtained. That is, it was demonstrated that C12A7: e ⁻ has a high barrier, that is, a blocking effect with respect to the inflow of holes, and has an ohmic property with respect to the inflow of electrons.

On the other hand, as shown in FIG. 4, when the C12A7: e ⁻ layer was provided on the surface side of N-type Si, it exhibited almost ohmic characteristics. The reason why the current value in FIG. 4 is smaller than that in FIG. 3 is that the resistance of C12A7: e ⁻ itself is higher than that of Al—Nd.

As described above, it was confirmed by the first verification that the amorphous C12A7: e ⁻ layer can block “holes” and has diode characteristics. Therefore, next, the second verification in which the diode characteristics are applied to a field effect thin film transistor and the hole blocking effect is confirmed will be described in detail.

  In this second verification, a so-called SOI single crystal silicon thin film wafer fabricated by SIMOX method is used to fabricate a TFT using a Si substrate as a gate electrode, a buried SiO 2 layer as a gate insulating layer, and a 50 nm SOI layer as a channel. Then, the electrical characteristics of the TFT were measured and evaluated.

  FIG. 5 is a diagram summarizing the specifications of the SOI used in the second verification in the first embodiment of the present invention. FIG. 6 is an explanatory view showing a method for measuring the TFT structure and the electrical characteristics when performing the second verification in the first embodiment of the present invention.

As the electrode structure, a third sample having a source / drain electrode in which an Al-Nd is stacked on a C12A7: e ^- layer, and a source / drain electrode formed of only an Al-Nd electrode without the C12A7: e ^- layer. The fourth sample with the drain electrode was prepared respectively

  Then, for two patterns of voltage Vds of 1.0 V and 10 V, Vgs is changed from -10 V to +20 V in 0.5 V steps, and the current value Ids at that time is measured to verify the blocking effect of the hole current. Did.

FIG. 7 is a diagram showing the results of electrical characteristics measured using a third sample having a C12A7: e ⁻ layer according to Embodiment 1 of the present invention, and FIG. 8 is a diagram showing C12A7 according to Embodiment 1 of the present invention: It is a figure which shows the electrical property result measured using the 4th sample which does not have e < ^- > layer.

When the results of FIG. 7 and FIG. 8 are compared, a large difference was observed in the drain current under negative gate bias due to the difference in the electrode structure due to the presence or absence of C12A7: e ⁻ . That is, comparing the characteristic results in which Vgs in FIG. 7 and FIG. 8 is about 5 V or less, the drain current (= leakage current) can be dramatically reduced by providing the C12A7: e ⁻ layer. Recognize.

That is, in the TFT of an Al—Nd electrode without C12A7: e ⁻ , as shown in FIG. 8, when Vgs becomes approximately 5 V or less, a hole current flows. On the other hand, in the TFT having an electrode structure with C12A7: e ⁻ , as shown in FIG. 7, it can be seen that the hole current can be blocked only by sandwiching the CA layer of about 20 nm.

In the portion indicated by the dotted circle in FIG. 7 which is the measurement result of the third sample having the C12A7: e ⁻ layer, the electrode area is as large as 1 mm × 3 mm, so most of the current flows from the drain electrode 40 to the gate electrode. D → G leakage current. On the other hand, in the portion shown by the dotted circle in FIG. 8 which is the measurement result in the fourth sample having no C12A7: e ⁻ layer, the electrode area is as large as 1 mm × 3 mm, so most of the current is from the gate electrode to the drain electrode G → D leakage current to 40

  Based on the results of the first verification and the second verification as described above, the silicon-based thin film semiconductor device according to the first embodiment will be described next, taking application to a silicon-based thin film semiconductor field effect transistor as an example.

FIG. 9 is a schematic cross-sectional view of a typical a-Si: H.TFT in the first embodiment of the present invention. In the silicon-based thin film semiconductor device according to the first embodiment, a C12A7: e ⁻ layer 20 is provided under Al or Cu which is the source electrode 30 and the drain electrode 40. That is, the C12A7: e ⁻ layer 20 is provided between the silicon-based thin film 10 and each of the source electrode 30 and the drain electrode 40.

Here, since the C12A7: e ⁻ layer 20 is as thin as 10 to 30 nm and has a relatively high resistance, even if the C12A7: e ⁻ layer 20 is left on the entire surface, it has no influence on the electrical characteristics of the TFT. Absent. The C12A7: e ^- layer 20 is a layer that replaces the so-called n + a-Si: H layer, and functions to block holes, as is apparent from the first and second verifications described above.

FIG. 10 is a diagram showing so-called transfer characteristics of the silicon-based thin film semiconductor device according to the first embodiment of the present invention. As in the prior art, when the amorphous electride C12A7: e ⁻ layer 20 is not provided, the leak current reaches 1 × 10 ⁻¹² under negative gate bias.

On the other hand, the effect of the present invention is that the provision of the amorphous electride C12A7: e ^- layer 20 can block the "inflow of holes" which is the cause of the leak current. Then, as indicated by the arrows in FIG. 10, the leakage current can be dramatically reduced to the extent that it approaches 1 × 10 ⁻¹⁴ .

It is apparent that the provision of the amorphous electride C12A7: e ⁻ layer in the microcrystalline silicon TFT and the LTPS TFT can similarly reduce the leak current caused by the holes.

The electride C12A7: e ^- layer 20 is a chemically stable ceramic, and several improvements can be proposed as the structure of the source electrode 30 and the drain electrode 40 in the TFT manufacturing process. So, below, a concrete electrode structure is demonstrated in detail as Example 1- Example 3 using drawing.

<Example 1: C12A7: Electrode structure for leaving e < ^- > layer on the entire surface>
FIG. 11 is a schematic vertical sectional view of a silicon-based thin film semiconductor device having the electrode structure of Example 1 in the first embodiment of the present invention. As shown in FIG. 11, this example 1 has an electrode structure in which the C12A7: e ⁻ layer 20 is left on the entire surface, that is, an electrode structure in which the C12A7: e ⁻ layer 20 is not etched away.

Such a structure is less likely to cause so-called side etching because the C12A7: e ⁻ layer 20 is less likely to be etched by plasma dry etching, ie, the etching rate is slow. By using this property, it is possible to obtain a structure in which the upper Al electrode material does not directly contact the Si layer. The source and drain electrodes may be formed by so-called lift-off.

<Example 2: C12A7: Electrode structure for leaving e < ^- > layer only in the electrode part>
FIG. 12 is a schematic vertical sectional view of a silicon-based thin film semiconductor device having the electrode structure of Example 2 in the first embodiment of the present invention. As shown in FIG. 12, this embodiment 2 has an electrode structure in which the C12A7: e ⁻ layer 20 is left only in the electrode portions 30, 40, and is a structure which can be applied to all silicon-based TFTs.

Incidentally, the amorphous electride electrode portion C12A7: e ^- width of the layer 20 (breadth), the amorphous electride C12A7: e ^- than the electrode wiring material to be laminated on the layer 20, to be larger Make it Then, for example, when a general Al-Nd alloy is laminated as an electrode material, an electrode structure as shown in FIG. 12 can be realized by using dry etching using chlorine plasma for etching.

The etching rate of the electrode material is as follows, for example, when chlorine is used as the etching gas.
Amorphous ^C12A7: e ^-: 0.1nm / sec Al-Nd: 0.54 nm / sec That is, the etching rate of the Al-based material, five times faster than the C12A7. Therefore, by performing chlorine plasma dry etching, the C12A7 layer 20 can be formed in a state in which no side etch hole is generated.

Example 3 Electrode Structure Applied to a General Self-Aligned LTPS-TFT
FIG. 13 is a schematic vertical sectional view of a silicon-based thin film semiconductor device having the electrode structure of Example 3 in the first embodiment of the present invention. The third embodiment shows an application example of the C12A7: e ⁻ layer 20 to a general self-aligned LTPS-TFT, as shown in FIG.

Specifically, in the source / drain contact formation step, for example, a C12A7: e ⁻ layer 20 is deposited instead of the conventional barrier metal Mo. The feature of this structure is that the C12A7: e ⁻ layer 20 is provided on the n + LTPS layer formed by ion doping to prevent the inflow of holes.

The source / drain electrode may be formed by general wet etching or chlorine plasma etching. Then, in FIG. 13, the C12A7: e ⁻ layer 20 is provided between the gate insulating film and each of the source electrode 30 and the drain electrode 40.

  Next, with respect to a specific manufacturing method in the case of applying the present invention to a-Si: H · TFT, which is a representative of amorphous silicon thin film transistors, as manufacturing method 1 to manufacturing method 3 using drawings explain.

<Production method 1: Application to general back channel etching type a-Si: H · TFT>
FIG. 14 is an explanatory view showing a manufacturing step of the silicon-based thin film semiconductor device according to the manufacturing method 1 in the first embodiment of the present invention. Production method 1 comprises the following three steps.

(Step 1) Formation of gate electrode → formation of gate insulating film → formation of intrinsic amorphous silicon layer (i-a-Si: H) → formation of i-a-Si: H island In the order of the prior art The process is performed to form a silicon-based thin film 10.

(Step 2) Sputter deposition (for example, thickness 20 nm) of the amorphous C12A7 layer 20, which is a technical feature of the present invention, is performed, and subsequently Al layer sputter deposition (for example, thickness 400 nm) for electrode wiring ) To form an electrode material.

The C12A7: e ⁻ layer 20 is formed by sputtering using crystalline C12A7: e ⁻ as a sputtering target, letting pure argon flow into the chamber evacuated, for example, while maintaining the gas pressure at 2 Pa. The film was formed by RF magnetron sputtering.

(Step 3) Resist application → mask formation of source electrode 30 and drain electrode 40 → Al layer and amorphous C12A7 layer etching (for example, chlorine plasma etching: employing selectivity Al: a-CA = 5: 1) → resist The source electrode 30 and the drain electrode 40 are formed in the order of exfoliation → completion of the source electrode 30 and the drain electrode 40. In addition, as shown in FIG. 14, it is desirable that the thickness of the a-C 12A7: e ⁻ layer 20 be several nm by using the difference in the selection ratio. The reason is to prevent damage to the silicon-based thin film 10 by chlorine plasma etching.

<Method 2: application to general etching stopper (E / S) type a-Si: H · TFT>
FIG. 15 is an explanatory view showing a manufacturing step of the silicon-based thin film semiconductor device according to the manufacturing method 2 in the first embodiment of the present invention. Production method 2 comprises the following three steps.

(Step 1) Formation of gate electrode → formation of gate insulating film → formation of intrinsic amorphous silicon layer (i-a-Si: H) → formation of etching stopper insulation layer (SiNx) → etching stopper (E / S) A process according to the prior art is performed in the order of formation → formation of i-a-Si: H island to form the silicon-based thin film 10.

(Step 2) Sputter deposition (for example, thickness 20 nm) of the amorphous C12A7 layer 20 which is a technical feature of the present invention is performed, followed by Cu layer sputtering deposition for electrode wiring (for example, thickness 400 nm) ) To form an electrode material.

The C12A7: e ⁻ layer 20 is formed by sputtering using crystalline C12A7: e ⁻ as a sputtering target, letting pure argon flow into the chamber evacuated, for example, while maintaining the gas pressure at 2 Pa. The film was formed by RF magnetron sputtering.

(Step 3) Resist application → mask formation of source electrode 30 and drain electrode 40 → Cu layer and amorphous C12A7 layer etching (for example, hydrogen peroxide based wet etching, chlorine based plasma etching are employed) → resist removal → source electrode The source electrode 30 and the drain electrode 40 are formed in the order of 30 and completion of the drain electrode 40. When using an Al layer, the etching of the Al layer and the amorphous C12A7 layer may be performed with a phosphoric acid-based chemical solution.

<Production Method 3: Application to General Self-Aligned LTPS-TFT>
FIG. 16 is an explanatory drawing showing a manufacturing step of the silicon-based thin film semiconductor device according to manufacturing method 3 in the first embodiment of the present invention. Production method 3 comprises the following two steps.

(Step 1) Formation of buffer layer → formation of intrinsic amorphous silicon layer (ia-Si: H) → dehydrogenation step → formation of LTPS layer by ELA → formation of LTPS island → formation of gate insulating layer → gate In the order of formation of electrodes → formation of contact holes for source / drain electrodes → formation of n + LTPS layer by ion doping method, the process of the prior art is performed to form a silicon-based thin film 10.

(Step 2) Sputter deposition (for example, thickness 20 nm) of the amorphous C12A7 layer 20 which is a technical feature of the present invention is performed, followed by Cu layer sputtering deposition for electrode wiring (for example, thickness 400 nm) ) To form an electrode material. After that, resist application → mask formation of source electrode 30 and drain electrode 40 → Cu layer and amorphous C12A7 layer etching (for example, hydrogen peroxide based wet etching, chlorine based plasma etching are adopted) → resist removal → source electrode The source electrode 30 and the drain electrode 40 are formed in the order of 30 and completion of the drain electrode 40.

The C12A7: e ⁻ layer 20 is formed by sputtering using crystalline C12A7: e ⁻ as a sputtering target, letting pure argon flow into the chamber evacuated, for example, while maintaining the gas pressure at 2 Pa. The film was formed by RF magnetron sputtering.

The above-described production methods 1 and 2 are innovative production processes in which the n + a-Si: H layer is omitted. The reason why this process is possible is that C12A7: e ^- has a hole blocking effect. The processing of C12A7: e ⁻ may be performed by chlorine plasma dry etching as the same process as the processing of Al and Cu.

  In the production methods 1 and 2, the n + a-Si: H layer can be omitted, so that the plasma CVD film forming step for forming the n + a-Si: H layer is not necessary, and the expensive plasma CVD apparatus is not necessary. In addition, there is an advantage that the toxic gas phosphine becomes unnecessary and the decontamination apparatus becomes unnecessary.

  Furthermore, since the manufacturing method 1 does not require a so-called back channel etching step, the thickness of the intrinsic amorphous silicon layer (i-a-Si: H) can be reduced to one third or less of the conventional thickness. This has the merit of reducing the film formation time, that is, improving the productivity.

  Therefore, the method of manufacturing a silicon-based thin film semiconductor device according to the present invention can improve the productivity of the manufacturing line and reduce the burden on safety management, and can reduce the production cost.

Although Embodiment 1 described above exemplifies the case where the amorphous electride C12A7: e ⁻ layer is used as a part of the source / drain electrode material, the present invention is limited to such a material. It is not a thing. It is considered that a hole current can be blocked if the band gap is at least three times that of crystalline silicon and has electron conduction.

As described above, in the silicon-based thin film semiconductor device according to the first embodiment, the amorphous electride C12A7: e ⁻ having electron conduction and a small work function and a large band gap is used as a source / drain electrode of a silicon-based TFT. A structure provided between the metal material and the silicon-based thin film is provided. As a result, it is possible to reduce the leak current caused by the holes, to improve the aperture ratio, to reduce the power consumption, and to improve the performance of the TFT liquid crystal display.

  Furthermore, as a manufacturing process, in the case of an a-Si: H.TFT, the process of manufacturing an n + a-Si: H layer using a PE-CVD apparatus becomes unnecessary, and the film forming time can be reduced. In a polycrystalline Si TFT, the process of manufacturing an n + Si layer using an ion doping apparatus is not necessary. As a result, simplification of the manufacturing process can also reduce the product cost.

  10 silicon-based thin film, 20 amorphous electride, 30 source electrode, 40 drain electrode.

Claims (10)

A material having a band gap of at least three times the band gap of crystalline silicon and having an electrical conductivity by the movement of electrons is provided between each of the source electrode and the drain electrode and the silicon-based thin film ,
The substance is amorphous electride C12A7: e ⁻ formed on the entire surface of the silicon-based thin film ,
Silicon-based thin film semiconductor device. The silicon according to claim 1 , wherein the amorphous electride C12A7: e ^- is an electrically conductive substance having physical properties as an electride, maintaining a cage structure in which electrons of the composition 12CaO · 7Al ₂ O ₃ are included. Thin film semiconductor device. The amorphous electride C12A7: e ^- are silicon-based thin film semiconductor device according to claim 1 or 2 having a band gap greater than 5 eV. The amorphous electride C12A7: e ^- a work function of a 2.5EV～3.3EV, according to any one of claims 1 3 having a small work function as compared with aluminum or molybdenum Silicon-based thin film semiconductor device. The silicon-based thin film semiconductor device according to any one of claims 1 to 4 , wherein the amorphous electride C12A7: e ^- is formed to have a thickness of 10 nm to 30 nm. The silicon-based thin film semiconductor device according to any one of claims 1 to 5 , wherein the silicon-based thin film is any of amorphous silicon, microcrystalline silicon, or polycrystalline silicon. A silicon-based thin film semiconductor provided with a material having a band gap of three or more times the band gap of crystalline silicon and having electrical conductivity by electron transfer, between each of a source electrode and a drain electrode and a silicon-based thin film A method of manufacturing the device,
A first step of laminating amorphous electride C12A7: e ⁻ as the substance on the entire surface of the silicon-based thin film;
A low resistance electrode wiring material is laminated on the amorphous electride C12A7: e ⁻ , and the source electrode and the drain electrode are formed so that the low resistance electrode wiring material is not in contact with the silicon-based thin film. A second method for manufacturing a silicon-based thin film semiconductor device. 8. The method according to claim 7 , wherein the source electrode and the drain electrode are formed by chlorine plasma dry etching using an Al-based material as the low resistance electrode wiring material in the second step. .   The amorphous electride C12A7: e between the source electrode and the drain electrode ^- The film thickness of the first portion of the amorphous electride C12A7: e under each of the source electrode and the drain electrode ^- The silicon-based thin film semiconductor device according to claim 1, wherein the film thickness of the second portion is smaller than that of the second portion.   The amorphous electride C12A7: e between the source electrode and the drain electrode ^- The film thickness of the first portion of the amorphous electride C12A7: e under each of the source electrode and the drain electrode ^- The method for manufacturing a silicon-based thin film semiconductor device according to claim 7, wherein the film thickness of the second portion of the semiconductor device is smaller than that of the second portion.

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