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WO2015115330A1 - Thin-film transistor, oxide semiconductor, and method for producing same - Google Patents

Thin-film transistor, oxide semiconductor, and method for producing same Download PDF

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Publication number
WO2015115330A1
WO2015115330A1 PCT/JP2015/051845 JP2015051845W WO2015115330A1 WO 2015115330 A1 WO2015115330 A1 WO 2015115330A1 JP 2015051845 W JP2015051845 W JP 2015051845W WO 2015115330 A1 WO2015115330 A1 WO 2015115330A1
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Prior art keywords
oxide
semiconductor layer
film transistor
thin film
semiconductor
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PCT/JP2015/051845
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French (fr)
Japanese (ja)
Inventor
一仁 塚越
慎也 相川
たきお 木津
麻希 清水
伸彦 三苫
生田目 俊秀
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独立行政法人物質・材料研究機構
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Priority claimed from JP2014016630A external-priority patent/JP6261125B2/en
Priority claimed from JP2014016273A external-priority patent/JP6252903B2/en
Priority claimed from JP2014016631A external-priority patent/JP6252904B2/en
Application filed by 独立行政法人物質・材料研究機構 filed Critical 独立行政法人物質・材料研究機構
Publication of WO2015115330A1 publication Critical patent/WO2015115330A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02631Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02551Group 12/16 materials
    • H01L21/02554Oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02565Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H10D30/6756Amorphous oxide semiconductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass

Definitions

  • the first to third inventions of the present application relate to an oxide thin film transistor and a method for manufacturing the same.
  • the fourth invention of the present application also relates to a thin film transistor and a method for manufacturing the same.
  • the fifth invention of the present application relates to an oxide semiconductor, a manufacturing method thereof, a thin film transistor using the same, and a semiconductor device.
  • TFTs Thin film transistors
  • EL organic electroluminescence
  • the TFT As the TFT, a semiconductor layer (channel layer) using amorphous silicon or polysilicon is known. In recent years, in order to improve various characteristics, the semiconductor layer has an In (indium) -Zn (zinc) -O (IZO) system, an In-Ga (gallium) -Zn-O (IGZO) system, or Sn (tin).
  • IZO In (indium) -Zn (zinc) -O
  • IGZO In-Ga (gallium) -Zn-O
  • Sn Tin
  • Such a thin film transistor has n-type conductivity and exhibits higher channel mobility than amorphous silicon or polysilicon, it can be suitably used as a switching element for a high-definition display or a large-screen display.
  • oxygen vacancies are mainly introduced by desorption of oxygen to the indium oxide structure, and as a result, charge is generated to serve as a semiconductor layer.
  • a semiconductor layer made of a metal oxide does not exhibit p-type conduction in principle and has a very small off current, the use of a thin film transistor has an advantage that power consumption can be reduced.
  • the thin film transistor is preferably used as a switching element of a liquid crystal display or an organic electroluminescence display as described above, a relatively high-intensity visible light is irradiated in its use.
  • characteristics of relatively short wavelength (high energy) components for example, light irradiation with a wavelength of 420 nm (2.95 eV) may deteriorate characteristics such as a shift in threshold voltage of a thin film transistor.
  • it is desirable that the contact resistance at the interface between the source electrode and / or drain electrode and the semiconductor layer is low, that the electron mobility is high, and that the gate controllability is excellent, and that these characteristics are also excellent. It has been.
  • the IZO, IGZO, and SZO metal oxides which are metal oxides described in Patent Document 1, can easily react with the water in the Zn, Ga, and Sn contained therein. As a physical structure, unstable suboxide is formed, and the amount of oxygen vacancies cannot be adjusted, resulting in a problem of greatly degrading transistor characteristics.
  • Patent Document 7 discloses, as a metal oxide, a material containing at least one element of zinc and tin, yttrium, niobium, tantalum, hafnium, lanthanum, scandium, vanadium, titanium, magnesium. It is disclosed that at least one of aluminum, gallium and silicon is used. In addition, in order to suppress fluctuations in threshold voltage caused by the destruction effect due to plasma damage and the increase in carriers due to radiation effects in the thin film transistor manufacturing stage, at least one of gallium, indium, tin, zirconium, hafnium, and vanadium is added to zinc oxide. It is disclosed to dope one ion (Patent Document 8).
  • Non-Patent Document 1 electrical characteristics of an oxide film transistor of an IZO metal oxide doped with tantalum have been reported.
  • Non-Patent Document 1 since zinc is contained as a main element, there is a serious problem that a considerable limitation is imposed on the process in order to suppress the formation of suboxides in the thin film transistor manufacturing stage.
  • Patent Document 2 there is a report that indium oxide doped with either tin, titanium, or tungsten is used instead of IZO or IGZO as a metal oxide.
  • Patent Document 2 the oxide film transistor using indium oxide doped with either titanium or tungsten described in the above document as the metal oxide, the amount of oxygen vacancies introduced into the main structure indium oxide is adjusted at the metal oxide production stage. There is a big problem that the manufacturing process is limited because it is very difficult to do.
  • the inventors of the present invention have described that the oxygen separation energy of the metal (Me) -O bond or nonmetal-O bond to the first metal oxide such as indium oxide is 200 kJ / mol than the oxygen separation energy of the first metal oxide.
  • a thin film transistor in which the amount of oxygen vacancies in the above problem was controlled by adding a large oxide as described above and a method for manufacturing the same were filed (Japanese Patent Application No. 2013-099284).
  • Japanese Patent Application No. 2013-099284 Japanese Patent Application No. 2013-099284
  • a semiconductor layer (channel layer) using amorphous silicon or polysilicon used for a TFT is known.
  • various metals are used for a semiconductor layer in order to improve various characteristics.
  • a TFT using an oxide has been studied (for example, see Patent Document 1).
  • Patent Document 9 discloses a semiconductor device including a transistor in which a source electrode layer and a drain electrode layer are provided in contact with an oxide semiconductor film.
  • Patent Document 10 in a method for manufacturing a semiconductor device using an oxide semiconductor, an oxide semiconductor film, a gate insulating film provided over the oxide semiconductor film, a gate electrode in contact with the gate insulating film, and a gate A step of forming a sidewall insulating film in contact with the electrode and a source electrode and a drain electrode in contact with the oxide semiconductor film, and the gate insulating film and the sidewall insulating film release oxygen contained in the oxide semiconductor film.
  • a method of forming at a temperature lower than the temperature at which separation is suppressed is disclosed.
  • Patent Document 11 discloses a gate electrode on an insulating substrate, a gate insulating film on the gate electrode, an oxide semiconductor film containing indium on the gate insulating film, and a source / drain on the oxide semiconductor film.
  • the XPS spectrum in the oxide semiconductor region where the peak position due to the indium 3d orbit of the XPS spectrum in the surface layer of the oxide semiconductor film where the source / drain electrodes do not overlap is present in the lower part of the surface layer.
  • a TFT that is shifted to a higher energy side than the peak position due to the indium 3d orbital is disclosed.
  • the first to third inventions of the present application have been made in view of such circumstances, and the first metal oxide capable of generating electron carriers by introducing oxygen vacancies into the semiconductor layer (channel layer), A thin film transistor using a composite metal oxide to which a second oxide having a larger oxygen dissociation energy than that of the first metal oxide is added at least 200 kJ / mol and having a specific element distribution.
  • An object of the present invention is to provide a thin film transistor and a method for manufacturing the same, which are compatible with suppression of characteristic deterioration due to light irradiation, low contact resistance, and excellent gate controllability.
  • the subject of the 4th invention of this application is providing the thin-film transistor which solves the said problem on composition conditions other than having shown by the prior patent application mentioned above, and its manufacturing method.
  • a light emitting layer is used for an organic EL display or a liquid crystal display.
  • light emission from the blue light emitting layer having the highest energy that is, light emitted at a short wavelength has a peak at 450 nm, and the bottom of the emission spectrum extends to 420 nm on the short wavelength side.
  • the thin film transistors constituting the organic EL display and the liquid crystal display are irradiated with light from the light emitting layer, it is desired that the thin film transistor be highly resistant to deterioration with respect to light irradiation having the above wavelength. It is rare. Here, it is difficult to deteriorate against light irradiation from the light emitting layer.
  • the oxide semiconductor constituting the thin film transistor emits light from the light emitting layer (specifically, a wavelength of 420 nm to 600 nm).
  • “Threshold voltage shift” induced by light irradiation (where “threshold voltage shift” refers to a phenomenon in which the threshold voltage shifts to the negative side due to light emission from the light emitting layer). .) Can be suppressed. Therefore, in order to provide a highly reliable thin film transistor, an oxide semiconductor that can sufficiently suppress this “threshold voltage shift” is desired.
  • any of the oxide semiconductor films disclosed in the above-mentioned patent documents has a problem that the “threshold voltage shift” induced by light emission from the light emitting layer cannot be sufficiently suppressed.
  • an oxide semiconductor used for a thin film transistor constituting an organic EL display or a liquid crystal display is desired to be able to sufficiently suppress a “threshold voltage shift” induced by light emission from a light emitting layer.
  • the fifth invention of the present application was made in view of such circumstances, and an oxide semiconductor capable of sufficiently suppressing a “threshold voltage shift” induced by light emission from the light emitting layer, a manufacturing method thereof, and It is an object to provide a thin film transistor and a semiconductor device using the thin film transistor.
  • the semiconductor device in this specification includes all devices using a transistor made of a semiconductor. Therefore, for example, an organic EL display and a liquid crystal display are also included in this.
  • the present inventor has at least one element X selected from the group consisting of silicon, tantalum, zirconium, hafnium, aluminum, yttrium and rare earth elements among the elements X constituting the second oxide (XOx). It has been found that a thin film transistor in which the concentration of 1 exhibits a maximum value in the central portion in the thickness direction of the semiconductor layer solves the above problems, and has led to the first to third inventions of the present application.
  • the first invention of the present application is [1] a source electrode and a drain electrode; A semiconductor layer provided in contact with the source electrode and the drain electrode; A gate electrode provided corresponding to a channel between the source electrode and the drain electrode; A thin film transistor having an insulator layer provided between the gate electrode and the semiconductor layer,
  • the semiconductor layer has a second metal oxide that can generate electron carriers by introducing oxygen vacancies, and the second energy of oxygen is 200 kJ / mol or more higher than that of the first metal oxide.
  • the concentration of at least one element X 1 selected from the group consisting of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements is in the thickness direction of the semiconductor layer.
  • the present invention relates to the above-described thin film transistor, which exhibits a maximum value at the center.
  • the concentration of the element X 1 shows a maximum value in the central portion in the thickness direction of the semiconductor layer.
  • the second invention of the present application is [3] a source electrode and a drain electrode; A semiconductor layer provided in contact with the source electrode and the drain electrode; A gate electrode provided corresponding to a channel between the source electrode and the drain electrode; A thin film transistor having an insulator layer provided between the gate electrode and the semiconductor layer,
  • the semiconductor layer has a second metal oxide that can generate electron carriers by introducing oxygen vacancies, and the second energy of oxygen is 200 kJ / mol or more higher than that of the first metal oxide.
  • the concentration of at least one element X 2 that does not correspond to any of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements is in the thickness direction of the semiconductor layer.
  • the present invention relates to the above-described thin film transistor that exhibits a minimum value in the center.
  • the following [4] is a preferred embodiment of the second invention of the present application [4]
  • the concentration of the element X 2 shows a minimum value in the central portion in the thickness direction of the semiconductor layer.
  • the third invention of the present application is [5] a source electrode and a drain electrode; A semiconductor layer provided in contact with the source electrode and the drain electrode; A gate electrode provided corresponding to a channel between the source electrode and the drain electrode; A thin film transistor having an insulator layer provided between the gate electrode and the semiconductor layer,
  • the semiconductor layer has a second metal oxide that can generate electron carriers by introducing oxygen vacancies, and the second energy of oxygen is 200 kJ / mol or more higher than that of the first metal oxide.
  • the said thin film transistor is related with the said thin-film transistor in which the said semiconductor layer contains nitrogen further, and the density
  • [6] to [17] are preferred embodiments of the first to third inventions of the present application [6].
  • Zr zirconium
  • Pr praseodymium
  • the thin film transistor according to any one of [1] to [12], wherein the thickness of the semiconductor layer is in the range of 5 nm to 20 nm.
  • the semiconductor layer is formed at a temperature of 10 ° C. or higher and 400 ° C. or lower; The method for producing a thin film transistor according to any one of [1] to [15] above.
  • [17] The method for producing a thin film transistor according to [16], wherein the semiconductor layer is formed at a temperature of 10 ° C. or higher and 200 ° C. or lower.
  • the apparatus which has a thin-film transistor of any one of said [1] to [15].
  • a source electrode and a drain electrode, a semiconductor layer provided in contact with the source electrode and the drain electrode, and a channel between the source electrode and the drain electrode are supported. And an insulating layer provided between the gate electrode and the semiconductor layer.
  • the semiconductor layer has tin oxide, an oxygen separation energy larger than that of tin oxide, and an oxide layer.
  • a thin film transistor which is a composite metal oxide to which a metal oxide having a difference from the separation energy of oxygen of tin of less than 200 kJ / mol is added is provided.
  • the semiconductor layer may include an additional oxide whose oxygen dissociation energy is smaller than that of tin oxide in an amount smaller than that of the metal oxide.
  • the content of the additional oxide in the semiconductor layer may be 20% by weight or less.
  • the content of the additional oxide in the semiconductor layer may be 4% by weight or less.
  • the semiconductor layer may be amorphous.
  • the semiconductor layer may have a thickness of 5 nm to 20 nm.
  • the additional oxide may be at least one oxide selected from the group consisting of lead, palladium, platinum, sulfur, antimony, strontium, thallium, and ytterbium.
  • the metal oxide may be at least one oxide selected from the group consisting of samarium, tungsten, neodymium, and gadolinium.
  • the content of the metal oxide in the semiconductor layer may be greater than 0 and 50% by weight or less. [29] Further, the content of the metal oxide in the semiconductor layer may be 5% by weight or less. [30] According to another aspect of the fourth invention of the present application, there is provided a method for producing any one of the above thin film transistors, wherein the semiconductor layer is formed at 10 ° C. or more and 500 ° C. or less. [31] Here, you may form the said semiconductor layer at 10 degreeC or more and 300 degrees C or less.
  • the present inventor has found that the first metal oxide made of a metal oxide capable of generating electron carriers by introducing oxygen vacancies and the oxygen separation energy are the first.
  • An oxide semiconductor into which oxygen vacancies are introduced is formed, which includes a second oxide that is 200 kJ / mol or more larger than the oxygen separation energy of one metal oxide, and further has OH as a substituent in the oxygen vacancies.
  • the oxide semiconductor in which at least one selected from the group consisting of a group, an H group, an F group, a Cl group, or a B group is introduced and bonded to the metal of the first metal oxide is used as a thin film transistor, It has been found for the first time that the “threshold voltage shift” induced by light emission from the light emitting layer can be sufficiently suppressed.
  • the fifth invention of the present application has a configuration shown in the following [32] to [57].
  • a first metal oxide made of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and an oxygen separation energy of 200 kJ / mol or more than the oxygen separation energy of the first metal oxide.
  • An oxide semiconductor comprising a large second oxide, wherein the metal of the first metal oxide is at least selected from the group consisting of an OH group, an H group, an F group, a Cl group, or a B group The oxide semiconductor having a bond with one.
  • the oxide semiconductor according to [32] wherein the oxygen separation energy of the second oxide is greater than or equal to 255 kJ / mol than the oxygen separation energy of the first metal oxide.
  • the second oxide includes silicon (Si), titanium (Ti), tungsten (W), tantalum (Ta), lanthanum (La), hafnium (Hf), zirconium (Zr), and praseodymium (Pr).
  • the second oxide is at least one selected from the group consisting of silicon (Si), titanium (Ti), tungsten (W), tantalum (Ta), lanthanum (La), and hafnium (Hf).
  • the oxide semiconductor according to [35] The oxide semiconductor according to [35].
  • [37] The oxide semiconductor according to any one of [32] to [36], wherein the content of the second oxide is greater than 0 and equal to or less than 50% by weight.
  • [38] The oxide semiconductor according to [37], wherein the content of the second oxide is greater than 0 and 5% by weight or less.
  • the content of at least one selected from the group consisting of the F group, the Cl group, or the B group is more than 5 ⁇ 10 18 atoms / cm 3 and not more than 1 ⁇ 10 21 atoms / cm 3
  • a thin film transistor comprising the oxide semiconductor according to any one of [32] to [49].
  • a source electrode and a drain electrode A semiconductor layer provided in contact with the source electrode and the drain electrode; A gate electrode provided corresponding to a channel between the source electrode and the drain electrode; Providing an insulator layer provided between the gate electrode and the semiconductor layer; A thin film transistor, wherein the semiconductor layer is formed of the oxide semiconductor according to any one of [32] to [49].
  • a semiconductor device comprising the thin film transistor according to [51].
  • the first metal oxide powder made of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and the oxygen separation energy of the first metal oxide is 200 kJ / day higher than the oxygen separation energy of the first metal oxide.
  • the first metal oxide powder made of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and the oxygen separation energy of the first metal oxide is 200 kJ / day higher than the oxygen separation energy of the first metal oxide.
  • the first metal oxide powder made of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and the oxygen separation energy of the first metal oxide is 200 kJ / day higher than the oxygen separation energy of the first metal oxide.
  • characteristic deterioration such as threshold current shift due to light irradiation is suppressed, contact resistance at the interface between the source electrode and / or drain electrode and the semiconductor layer is low, and electron transfer is suppressed.
  • a thin film transistor having a high level of practically preferable characteristics of high degree and excellent gate controllability, and a method for manufacturing the same are realized.
  • the metal oxide added thereto is in addition, the composite metal oxidation in which the oxygen separation energy of the added metal oxide is larger than the oxygen separation energy of tin oxide and the difference from the oxygen separation energy of tin oxide is less than 200 kJ / mol.
  • a thin film transistor with excellent transistor characteristics can be provided by using a semiconductor layer.
  • an oxide having an oxygen separation energy smaller than that of tin oxide is added in an amount smaller than that of the metal oxide to be added.
  • the fifth invention of the present application it is possible to provide an oxide semiconductor capable of sufficiently suppressing “threshold voltage shift” induced by light emission from the light emitting layer. Therefore, a thin film transistor using the oxide semiconductor, an organic EL display using the thin film transistor, and a liquid crystal display can have high reliability that the light emission from the light emitting layer hardly deteriorates.
  • Patent Document 9 discloses that the above oxide processed into an island shape in a semiconductor device having a transistor in which a source electrode layer and a drain electrode layer are provided in contact with an oxide semiconductor film such as an IZO or IGZO system.
  • concentration of fluorine, chlorine, and boron in a region not overlapping with the source electrode layer and the drain electrode layer on the side surface portion of the semiconductor film is disclosed.
  • this fluorine, chlorine, and boron are impurities contained in the etching gas, and must be removed as much as possible by the impurity removal treatment by solution cleaning in order to prevent the formation of parasitic channels due to their contamination. (See paragraphs 0184 and 0185, for example).
  • Patent Document 10 discloses that in a method for manufacturing a semiconductor device using an oxide semiconductor, one or more elements selected from boron, a rare gas element, and the like are used as a dopant.
  • this patent document does not describe the amount of dopant.
  • this dopant is implanted only to reduce the resistance of the oxide semiconductor in contact with the source electrode and the drain electrode, the amount of this dopant is very small, 5 ⁇ 10 18 atoms. / Cm 3 is presumed not to exceed. Therefore, even in Patent Document 10, it is not recognized that the metal constituting the oxide semiconductor film is bonded to such an extremely low concentration of boron or a rare gas element.
  • a region of the oxide semiconductor film located in a portion masked with the gate electrode contains boron or a rare gas element.
  • a metal that forms the oxide semiconductor film is boron used as a dopant. It does not combine with noble gas elements. Due to such differences, the oxide semiconductor film described in Patent Document 10 cannot obtain the above-described effect of the fifth invention of the present application.
  • Patent Document 11 a surface layer is formed as a separate layer different from the oxide semiconductor film in a portion where the source / drain electrodes of the oxide semiconductor film do not overlap with each other, and chemicals of indium and fluorine are formed only on the surface layer.
  • a TFT providing a bond is disclosed.
  • the TFT described in Patent Document 11 does not introduce fluorine into the oxide semiconductor film existing under the surface layer as a separate layer different from the surface layer.
  • a region mainly on the gate electrode side of the oxide semiconductor film functions as a channel region.
  • the dopant exists in at least the interface region with the gate electrode in the oxide semiconductor film (of course, the dopant may also exist in other regions). Therefore, in the oxide semiconductor film described in Patent Document 11, the above effect according to the fifth invention of the present application cannot be obtained.
  • FIG. 1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the first invention of the present application.
  • 1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the first invention of the present application.
  • FIG. 6 shows a relationship between the composition of an In—Si—O film and a band gap.
  • the figure which shows the X-ray-diffraction pattern for confirming that the semiconductor film used by 2nd Example (Example B2) of this invention 4th invention is amorphous.
  • the figure which shows the Id-Vd characteristic of the thin-film transistor of 2nd Example (Example B2) of this-application 4th invention is amorphous.
  • In-Si-O semiconductor of Example C and In-Si-O semiconductor having In-OH bond ((a) In3dXPS spectrum of In-Si-O semiconductor, (b) In-Si having In-OH bond) -In3dXPS spectrum of -O semiconductor).
  • the thin film transistor of the first invention of this application is: A source electrode and a drain electrode; A semiconductor layer provided in contact with the source electrode and the drain electrode; A gate electrode provided corresponding to a channel between the source electrode and the drain electrode; A thin film transistor having an insulator layer provided between the gate electrode and the semiconductor layer,
  • the semiconductor layer has a second metal oxide that can generate electron carriers by introducing oxygen vacancies, and the second energy of oxygen is 200 kJ / mol or more higher than that of the first metal oxide.
  • the concentration of at least one element X 1 selected from the group consisting of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements is in the thickness direction of the semiconductor layer.
  • the thin film transistor having a maximum value in the center.
  • the concentration of the specific element X 1 is in the thickness direction of the semiconductor layer is continuously and substantially change, that is, the element X 1 is a concentration gradient in the thickness direction of the semiconductor layer ing. More specifically, the concentration of the element X 1 shows a maximum value, that is, at least one peak in the central portion in the thickness direction of the semiconductor layer.
  • the “central portion” refers to both the interfaces of the semiconductor layer (usually, the interface in contact with the interlayer insulating film on the source electrode and drain electrode side and the interface in contact with the insulator layer on the gate electrode side). It refers to a location 2 nm or more, or 5% or more of the thickness of the semiconductor layer.
  • the at least one concentration of the element X 1 represents the maximum value in the central portion in the thickness direction of the semiconductor layer. That is, the concentration of the element X 1 in any location of the central portion in the thickness direction of the semiconductor layer is preferably higher than the concentration of the element X 1 in any position of the semiconductor layer.
  • the concentration of the element X 1 is, by indicating a maximum value in the central portion in the thickness direction of the semiconductor layer, characteristic deterioration such as a shift in the threshold current due to light irradiation can be suppressed, the source electrode And / or a remarkable technical effect that the contact resistance at the interface between the drain electrode and the semiconductor layer is low, the electron mobility is high, and the gate controllability is excellent is realized.
  • the thin film transistor of the first invention of the present application is preferably manufactured by a manufacturing method including a step of forming a semiconductor layer at 10 ° C. or higher and 400 ° C. or lower.
  • FIG. 1 is a schematic cross-sectional view of a thin film transistor 10 according to a preferred embodiment of the first invention of the present application.
  • the substrate 20 a substrate formed of a known forming material can be used, and any of those having optical transparency and those having no optical transparency can be used.
  • an inorganic substrate made of alkali silicate glass, quartz glass, silicon nitride, or the like; a silicon substrate; a metal substrate whose surface is insulated; acrylic resin, polycarbonate resin, PET (polyethylene terephthalate), or PBT (polybutylene)
  • Various substrates such as a resin substrate made of a polyester resin such as terephthalate) or a paper substrate can be used.
  • the substrate may be a composite material formed by combining a plurality of these materials.
  • the thickness of the substrate 20 can be appropriately set according to the design.
  • the thin film transistor 10 of this embodiment is a so-called bottom gate type transistor.
  • the thin film transistor 10 includes a gate electrode 30 provided on the substrate 20, an insulator layer 40 provided to cover the gate electrode 30, a semiconductor layer 50 provided on the upper surface of the insulator layer 40, A source electrode 60 and a drain electrode 70 provided in contact with the semiconductor layer 50 on the upper surface, and an interlayer insulating film 80 are provided.
  • the gate electrode 30 is provided corresponding to the channel region of the semiconductor layer 50 (at a position overlapping the channel region in a plan view).
  • the semiconductor layer 50 is composed of a composite metal oxide obtained by adding a second oxide (XOx) to a first metal oxide capable of generating electron carriers by introducing oxygen vacancies.
  • the semiconductor layer may contain components other than the second oxide and inevitable impurities as long as the adverse effects of the first invention of the present application are not adversely affected.
  • Each of the gate electrode 30, the source electrode 60, and the drain electrode 70 can be made of a generally known material.
  • the material for forming these electrodes include aluminum (Al), gold (Au), silver (Ag), copper (Cu), nickel (Ni), molybdenum (Mo), tantalum (Ta), and tungsten (W).
  • Examples thereof include metal materials such as these, alloys thereof, and conductive oxides such as indium tin oxide (ITO) and zinc oxide (ZnO).
  • these electrodes may form the laminated structure of two or more layers, for example by plating the surface with a metal material.
  • the gate electrode 30, the source electrode 60, and the drain electrode 70 may be formed of the same forming material or may be formed of different forming materials. Since manufacture becomes easy, it is preferable that the source electrode 60 and the drain electrode 70 are the same formation material.
  • the insulator layer 40 has an insulating property, and any of an inorganic material and an organic material can be used as long as it can electrically insulate the gate electrode 30 from the source electrode 60 and the drain electrode 70. It may be formed.
  • the inorganic material include normally known insulating oxides such as SiO 2 , SiN x , SiON, Al 2 O 3 , and HfO 2 , nitrides, and oxynitrides.
  • the organic material include acrylic resin, epoxy resin, silicon resin, and fluorine resin.
  • the organic material is preferably a photocurable resin material because it is easy to manufacture and process.
  • the semiconductor layer 50 includes a second metal oxide having energy greater than that of the first metal oxide that can generate electron carriers by introducing oxygen vacancies by 200 kJ / mol or more. It is formed of a complex oxide containing an oxide.
  • the first metal oxide is preferably a metal oxide including at least one selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), and tin (Sn), and the second The oxide is preferably zirconium (Zr), silicon (Si), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), scandium (Sc), yttrium (Y), lanthanum (La).
  • the element of the first oxide is In
  • the element of the second oxide is at least selected from the group consisting of Zr, Pr, Si, Ti, W, Ta, La, Hf, B, and C.
  • the element of the second oxide is at least one element selected from the group consisting of Sc, Ti, W, Nd, and Gd.
  • the oxygen separation energy of indium oxide is as small as 346 ⁇ 30 kJ / mol, so oxygen is easily desorbed from indium oxide to generate oxygen vacancies. It's easy to do. However, if the amount of oxygen vacancies becomes too large, it changes from semiconducting properties to metallic properties, making it unsuitable as a semiconductor layer.
  • a second oxide (XO x ) having an oxygen separation energy of 200 kJ / mol / greater than the oxygen separation energy of indium oxide more specifically,
  • the second metal oxide which is a metal oxide, or an equivalent nonmetallic element oxide as described later may be added.
  • the oxygen separation energy of the second oxide is preferably larger than that specified above, and an oxide having an oxygen separation energy of 725 kJ / mol or more, more preferably 780 kJ / mol or more is used as the second oxide. When used, it is preferable because the oxygen deficiency of indium oxide can be easily controlled.
  • the oxygen separation energy of the second oxide is 200 kJ / mol or more as compared with the first metal oxide.
  • a thing larger than 255 kJ / mol may be used.
  • a metal oxide is preferably used as the second oxide, but as a particularly suitable metal oxide, Table A1 in which oxides having an oxygen separation energy of 780 kJ / mol or more are summarized and oxygen As shown in Table A2, which summarizes metal oxides having a separation energy of 725 kJ / mol to 780 kJ / mol, zirconium oxide (Zr—O), praseodymium oxide (Pr—O), lanthanum oxide (La—O), Examples include, but are not limited to, tantalum oxide (Ta—O) and hafnium oxide (Hf—O). Similarly, silicon oxide (Si—O) described in Table A1 is also preferable as the second oxide.
  • the second oxide added to make the first metal oxide a semiconductor layer having an appropriate oxygen deficiency is particularly preferably a second oxide of 780 kJ / mol or more shown in Table A1. Is more preferable. Specifically, lanthanum oxide (La—O), silicon oxide (Si—O), tantalum oxide (Ta—O), and hafnium oxide (Hf—O) can be given.
  • the content of the second oxide added to the first metal oxide in order to make the first metal oxide a semiconductor layer having a suitable oxygen deficiency is not particularly limited, but is larger than 0 and 50% by weight. The following range is recommended. In particular, when the content of the second oxide added to the first metal oxide is in the range of more than 0 and 5% by weight or less, it is practically preferable in that it can be produced at a low temperature of 200 ° C. or less.
  • In-Zn-O-based and In-Ga-Zn-O-based metal oxides tend to be polycrystalline when a semiconductor layer is formed. Therefore, in a generally known thin film transistor, the surface of the semiconductor layer does not become flat due to crystal grains contained in the semiconductor layer. In addition, the normally known semiconductor layer of an oxide film transistor has a reduced electrical conductivity in the plane direction due to such crystal grains. Therefore, in order to obtain planarization of the surface of the semiconductor layer 50 and high electrical conductivity, the semiconductor layer preferably has an amorphous structure.
  • the thickness of the semiconductor layer 50 is not particularly limited, but is preferably in the range of 5 nm or more and 20 nm or less.
  • the thickness of the semiconductor layer 50 can be measured by using a crystal oscillation type film thickness meter arranged mainly for film thickness calibration in the sputtering chamber in which the semiconductor layer 5 is formed. .
  • the composite metal oxide which comprises the semiconductor layer 50 is not limited to what added the metal oxide as a 2nd oxide to the 1st metal oxide, and the separation energy is 200 kJ / in comparison with the 1st metal oxide.
  • a non-metal oxide larger than mol may be added.
  • the composite metal oxide may be, for example, an oxide of at least one element selected from boron (B) and carbon (C) (ie, “composite metal oxide” in the present application). Is used to mean "an oxide in which a metal oxide is combined with an element having an energy greater than a predetermined value for oxygen").
  • the oxygen desorption energy of the B—O bond is as large as 809 kJ / mol and the oxygen desorption energy of the C—O bond is as large as 1076.38 ⁇ 0.67 kJ / mol, so that the amount of oxygen deficiency introduced into the first metal oxide This is because it can be easily controlled.
  • the concentration of the element X 1 is selected from the group consisting of yttrium and rare earth elements, semiconductor
  • the maximum value is shown at the center in the thickness direction of the layer.
  • oxygen in the vicinity of the valence band of the In 2 O 3 band gap is caused by light absorption as a factor of the threshold voltage shift of the thin film transistor due to light irradiation with a wavelength of 420 nm. It is estimated that electrons hop from a level due to defects to a trap level near the conduction band.
  • the band gap of In 2 O 3 is about 3.7 eV, and the above-mentioned electron hopping is achieved by enlarging the conduction band of this band gap (from the vacuum level to 4.05 eV) (closer to the vacuum level side). It can be expected that the energy required for the above can be increased, and as a result, the shift of the threshold voltage due to light irradiation can be suppressed.
  • FIG. 3 shows the evaluation results of the band gap by photoelectron yield spectroscopy of an In—Si—O film having a thickness of 50 nm with SiO 2 weights of 1, 3 and 10% by weight, respectively.
  • the band gap which was about 3.7 eV when the SiO 2 content was 1% by weight, could be increased to 4.5 eV by increasing the SiO 2 content to 10% by weight.
  • candidate oxides that can have the effect of expanding the band gap like SiO 2 are Ta 2 O 5 (+0.3 eV), ZrO 2 (+1.4 eV), HfO. 2 (+1.5 eV), Al 2 O 3 (+2.8 eV), Y 2 O 3 (+1.3 eV) and rare earth oxides. Therefore, among the elements X constituting the first oxide XO x , the element X 1 added for the purpose of suppressing the threshold voltage shift is silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements.
  • Si 3 N 4 (+2.4 eV) can also have an effect of widening the band gap, and Si 3 N 4 can be used as a semiconductor together with or in place of the second oxide. It is also preferable to add to the composite metal oxide constituting the layer.
  • the concentration of the oxide of the element X 1 introduced into the In 2 O 3 film is usually 3% by weight or more and 50% by weight or less. Particularly, the concentration range of 10 to 30% by weight suppresses undesirable effects due to the addition. This is preferable from the viewpoint of expanding the gap.
  • the element X 1 of the semiconductor layer is a semiconductor layer, a high density at the central portion, having a concentration gradient of a low density at both interfaces. That is, the at least one concentration of the element X 1 represents a local maximum value, i.e. at least one peak at the center in the thickness direction of the semiconductor layer.
  • the meaning of the “central part” is as described above.
  • the concentration of oxide of the element X 1 is the maximum value in the central portion in the thickness direction of the semiconductor layer, for example, 3 wt% or more, 50 wt% or less, preferably 10 wt% As described above, it is preferably 30% by weight or less, and preferably has a concentration gradient that decreases monotonously as it approaches both interfaces.
  • the concentration of the oxide of the element X 1 at both interfaces is not particularly limited as long as it is substantially lower than the concentration at the center, and is preferably 0.1% by weight or less, for example, substantially zero. It is particularly preferred that
  • the concentration of the element X 1 in both interfaces is low, the contact resistance at the interface between the source electrode and / or drain electrode and the semiconductor layer is low and excellent in high gate controllability electron mobility That is, a practically preferable characteristic can be realized.
  • concentration of the element X 1 in the composite oxide constituting the semiconductor layer at the interface between the source electrode and / or drain electrode and the semiconductor layer is low, the composite oxide will have a tendency to release oxygen .
  • the complex oxide in the vicinity of the interface with the source electrode and / or drain electrode generates oxygen vacancies and is so-called metalized, and the contact resistance with the source electrode and / or drain electrode is reduced.
  • the thin film transistor of the second invention of the present application A source electrode and a drain electrode; A semiconductor layer provided in contact with the source electrode and the drain electrode; A gate electrode provided corresponding to a channel between the source electrode and the drain electrode; A thin film transistor having an insulator layer provided between the gate electrode and the semiconductor layer,
  • the semiconductor layer has a second metal oxide that can generate electron carriers by introducing oxygen vacancies, and the second energy of oxygen is 200 kJ / mol or more higher than that of the first metal oxide.
  • the concentration of at least one element X 2 that does not correspond to any of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements is in the thickness direction of the semiconductor layer.
  • the thin film transistor having a minimum value in the center.
  • the concentration of the at least one element X 2 continuously and substantially varies in the thickness direction of the semiconductor layer, that is, the at least one element X 2 is in the thickness direction of the semiconductor layer. It has a concentration gradient. More specifically, the concentration of the at least one element X 2 has a minimum value at the center in the thickness direction of the semiconductor layer.
  • the “central portion” refers to both the interfaces of the semiconductor layer (usually, the interface in contact with the interlayer insulating film on the source electrode and drain electrode side and the interface in contact with the insulator layer on the gate electrode side). It refers to a location 2 nm or more, or 5% or more of the thickness of the semiconductor layer.
  • the at least one element X 2 concentration shows a minimum value at the central portion in the thickness direction of the semiconductor layer. That is, the concentration of the element X 2 in any location of the central portion in the thickness direction of the semiconductor layer is preferably lower than the concentration of the element X 2 in any other portion of the semiconductor layer.
  • the at least one element X 2 is an element constituting the second oxide, that is, an element constituting the second oxide (XO x ) that is 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide.
  • X is an element that does not correspond to any of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements.
  • Element X 2 may be any element which corresponds to the above definition, but is not imposed specifically limited otherwise, preferably titanium (Ti). Further, tungsten (W) also can be used as the element X 2.
  • oxides of elements X 2 in the semiconductor layer is a semiconductor layer, a low density at the central portion, having a concentration gradient of high concentration both interfaces. That is, the at least one element X 2 concentration shows a minimum value at the central portion in the thickness direction of the semiconductor layer.
  • the concentration of the oxide of the element X 2 is preferably to have a minimum value in the central portion in the thickness direction of the semiconductor layer approaches from there to both interfaces, Each preferably has a monotonically increasing concentration gradient.
  • concentration of the oxide of the element X 2 in both interfaces from the viewpoint of for increasing the mobility is preferably 20 wt% or less 1 wt% or more.
  • concentration of the oxide of the element X 2 in the central portion is not particularly limited as long as it is substantially lower than the concentration at both interfaces, and is preferably 0.1% by weight or less, for example, substantially zero. It is particularly preferred that
  • the concentration of the element X 2 at both interfaces is high, the contact resistance at the interface between the source electrode and / or the drain electrode and the semiconductor layer is low, the electron mobility is high, and the gate controllability. It is possible to realize a practically preferable characteristic of being excellent in resistance. Due to the high concentration of element X 2 (for example, titanium) in the composite oxide constituting the semiconductor layer at the interface between the source electrode and / or drain electrode and the semiconductor layer, the composite oxide tends to release oxygen. Will have. As a result, the complex oxide in the vicinity of the interface with the source electrode and / or drain electrode generates oxygen vacancies and is so-called metalized, and the contact resistance with the source electrode and / or drain electrode is reduced.
  • element X 2 for example, titanium
  • the concentration of the element X 2 (for example, titanium) in the complex oxide constituting the semiconductor layer is high, the electron mobility tends to be improved. Effect more susceptible to the gate voltage, in the vicinity of the interface between the gate electrode side of the insulating film layer, by a high high electron mobility concentration of the element X 2 of the semiconductor layer to control a higher current at the same gate voltage In other words, an effect that gate controllability is improved can be realized.
  • the layer structure and other structures of the thin film transistor of the second invention of the present application are the same as those of the first invention of the present application.
  • the above description of the structure of the first invention of the present application also applies to the second invention of the present application as long as it does not contradict the purpose of the second invention of the present application.
  • the concentration of at least one element X 1 selected from the group consisting of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements among the elements X constituting the second oxide is the semiconductor layer.
  • at least one element that does not correspond to any of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements among the elements X constituting the second oxide is the semiconductor layer.
  • the concentration of X 2 indicates a minimum value at the central portion in the thickness direction of the semiconductor layer.
  • the concentration of silicon that corresponds to the element X 1 represents a maximum value in the central portion in the thickness direction of the semiconductor layer
  • the concentration of titanium corresponding to the element X 2 is the thickness direction of the semiconductor layer
  • a minimum value may be shown at the center.
  • the silicon concentration at the central portion of the semiconductor layer exhibits a maximum value, thereby realizing a target effect of suppressing characteristic deterioration such as a shift in threshold current due to light irradiation, and both of the semiconductor layers.
  • the high titanium concentration at the interface realizes the effect that the contact resistance at the interface between the source electrode and / or drain electrode and the semiconductor layer is low, the electron mobility is high, and the gate controllability is excellent.
  • a thin film transistor having characteristics at a high level can be realized.
  • the thin film transistor of the third invention of the present application A source electrode and a drain electrode; A semiconductor layer provided in contact with the source electrode and the drain electrode; A gate electrode provided corresponding to a channel between the source electrode and the drain electrode; A thin film transistor having an insulator layer provided between the gate electrode and the semiconductor layer,
  • the semiconductor layer has a second metal oxide that can generate electron carriers by introducing oxygen vacancies, and the second energy of oxygen is 200 kJ / mol or more higher than that of the first metal oxide.
  • the semiconductor layer further contains nitrogen, and the concentration of nitrogen shows a maximum value in a central portion in the thickness direction of the semiconductor layer.
  • the semiconductor layer further contains nitrogen, and the concentration of nitrogen exhibits a maximum value at the central portion in the thickness direction of the semiconductor layer.
  • the concentration of nitrogen exhibits a maximum value at the central portion in the thickness direction of the semiconductor layer.
  • the said semiconductor layer contains nitrogen further, and the density
  • the concentration of Si 3 N 4 (+2.4 eV) that can have the effect of expanding the band gap in addition to the above-described effect on the nitrogen concentration distribution has a maximum value in the central portion in the thickness direction of the semiconductor layer. Therefore, as in the first invention of the present application, a technical effect that characteristic deterioration such as shift of threshold current due to light irradiation is suppressed can be realized.
  • the addition of the second oxide to the semiconductor layers of the first to third inventions of the present application can be appropriately performed by employing a conventionally known method.
  • the second oxide is an oxide of a nonmetallic element such as boron or carbon
  • the specific example of the case where the first metal oxide is indium oxide (In 2 O 3 ) is described below. explain.
  • the first metal oxide is indium oxide (In 2 O 3 ) and the second oxide is boron (B) oxide
  • the boron oxide is added to the indium oxide, for example, by ion implantation.
  • the addition amount and depth can be controlled by changing the acceleration voltage.
  • the content is more preferably greater than 0 and 10% by weight or less.
  • ion implantation is performed by implanting boron ions instead of boron oxide into the first metal oxide.
  • This boron ion becomes a boron oxide in the first metal oxide.
  • the oxide can also be formed inside the first metal oxide.
  • the addition in the form of the oxide in the first metal oxide may be referred to as “adding the oxide”. Please be careful.
  • the addition of carbon oxide to indium oxide is, for example, In 2 O 3. It can be carried out by a co-sputtering method using a target and a graphite target. By changing the ratio of each sputtering power, the amount of carbon oxide added can be controlled, and the content is more preferably greater than 0 and not more than 10% by weight.
  • both the first metal oxide described first and the non-metal oxide described here were simultaneously used. It is also possible to form the semiconductor layer 50 with a composite metal oxide.
  • the second metal oxide and the non-metal oxide of the second type are included in the semiconductor layer made of the composite metal oxide. Two oxides may inevitably coexist. For example, when a thin film of such a semiconductor layer is manufactured by a solution method such as a sol-gel method, there is a high possibility that carbon remains in the thin film. It should be noted that such a case is also included in the first to third inventions of the present application.
  • examples of physical vapor deposition include vapor deposition and sputtering.
  • Examples of the vapor deposition method include vacuum vapor deposition, molecular beam vapor deposition (MBE), ion plating, and ion beam vapor deposition.
  • Examples of the sputtering method include conventional sputtering, magnetron sputtering, ion beam sputtering, ECR (electron cyclotron resonance) sputtering, and reactive sputtering.
  • a film forming method such as a reactive sputtering method, a DC (direct current) sputtering method, or a radio frequency (RF) sputtering method can be used.
  • the gate electrode 30 and the insulator layer 40 are formed on the substrate 20 by a generally known method, and then the semiconductor layer 50 is formed.
  • the semiconductor layer 50 includes the first metal oxide powder and the second oxide powder having an oxygen separation energy of 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide. Is produced by a physical vapor deposition method using a target that is a sintered body including a mixed gas of a rare gas and oxygen. Here, it demonstrates as using sputtering method as a physical vapor deposition method.
  • a sintered body of indium oxide powder and silicon oxide powder may be employed as the target.
  • the target may be mixed with impurities such as an additive (metal oxide or the like) at a weight percent or less of silicon oxide.
  • impurities such as an additive (metal oxide or the like) at a weight percent or less of silicon oxide.
  • metal oxides such as zinc oxide
  • indium oxide and silicon oxide may be mixed into the target at a ratio (weight ratio) equal to or lower than the silicon oxide content in the entire target as unintended impurities. Absent.
  • the content of silicon oxide contained in the sintered body is preferably more than 0% by weight and 50% by weight or less. Moreover, it is more preferable that the content of silicon oxide is more than 0 wt% and not more than 5 wt%.
  • In-Zn-O-based and In-Ga-Zn-O-based metal oxides which are generally known oxide semiconductors, if indium oxide is the "host material” and zinc oxide or gallium oxide is the “guest material” In general, 20 to 30% of guest material (zinc oxide or gallium oxide) is mixed with the host material (indium oxide).
  • the semiconductor layer 50 of the thin film transistor 10 of the present embodiment is formed into a thin film using the sintered body as described above as a target.
  • the silicon oxide content is more preferably more than 0 wt% and 5 wt% or less. Therefore, the semiconductor layer 50 in this preferable composition is used.
  • the oxide semiconductor can have an extremely small content of the guest material (silicon oxide) with respect to the host material (indium oxide) as compared with a conventionally known oxide semiconductor.
  • a mixed gas of a rare gas and oxygen may be used as a process gas.
  • the rare gas include helium, neon, argon, krypton, and xenon.
  • the process gas preferably does not contain a compound having a hydrogen atom.
  • an amorphous semiconductor layer can be formed by performing a step of forming a semiconductor layer at 10 ° C. or higher and 200 ° C. or lower. Further, by performing the treatment at a temperature higher than 200 ° C. and lower than or equal to 400 ° C., a suitable crystallized semiconductor layer can be formed. Further, the step of forming the semiconductor layer may be performed at room temperature.
  • “implemented at room temperature” means that the semiconductor layer is not heated for the step of forming the semiconductor layer, and the temperature adjustment of the working environment is unnecessary.
  • sputtering method employed in the method for manufacturing the thin film transistor of the present embodiment known methods such as RF sputtering and DC sputtering can be used.
  • the target may be indium oxide powder and silicon oxide powder, and a mixture of these powders may be sintered.
  • a sintered body of each powder may be sufficient. The latter is preferable from the viewpoint of controllability of the concentration distribution of silicon oxide as the second oxide.
  • the semiconductor layer can be formed by co-sputtering using a plurality of sintered bodies.
  • the concentration distribution of elements X 1 in the first invention, the concentration distribution of elements X 2 in the present second invention also, it is possible to preferably control by co sputtering.
  • the concentration distribution of Si and Ti in the In—Si—Ti—O semiconductor layer is expressed by the In—Si—O target and the In—Ti—O target.
  • both targets are installed in the same chamber, and the sputtering power for each target is preferably adjusted by preferably changing continuously.
  • the semiconductor layer can be formed in a process range corresponding to the magnitude of the separation energy of oxygen.
  • the effects of the first to third inventions of the present application are appropriately achieved by using the semiconductor layer in which the concentration distribution of the specific oxide is appropriately controlled. It is possible to realize a gate that suppresses deterioration of characteristics such as threshold current shift due to light irradiation, has low contact resistance at the interface between the source electrode and / or drain electrode and the semiconductor layer, and has high electron mobility. There is provided a thin film transistor having a practically preferable characteristic of excellent controllability at a high level.
  • the first to third inventions of the present application can also be applied to a so-called top gate type thin film transistor. Details of the structure and manufacturing method of a so-called top gate type thin film transistor are well known in the art as described in, for example, Japanese Patent Application Laid-Open No. 2013-219936, and based on these, those skilled in the art can apply the present application without undue trial and error.
  • the first to third inventions can be implemented in a top gate type embodiment.
  • a so-called top contact type thin film transistor has been described.
  • the first to third inventions of the present application can also be applied to a so-called bottom contact type thin film transistor. Details of the structure and manufacturing method of so-called bottom contact type thin film transistors are also well known in the art, and those skilled in the art can implement the first to third aspects of the present invention in a bottom contact type mode without undue trial and error. Is possible.
  • the oxygen separation energy of the metal oxide to be added is the oxygen separation energy of the tin oxide. Based on the new knowledge of the present inventors that the amount of oxygen deficiency in the above problem can be controlled by making the difference from the energy of separation of oxygen with respect to tin oxide less than 200 kJ / mol.
  • the thin film transistor of the first embodiment and the manufacturing method thereof are provided.
  • the present inventors further add an additional oxide whose oxygen separation energy is smaller than that of tin oxide, and the addition amount is less than the addition amount of the above metal oxide.
  • the present inventors have found that the amount of oxygen vacancies can be controlled and the amorphous stable formation temperature range can be expanded.
  • the fourth invention of the present application also provides a thin film transistor and a manufacturing method thereof according to the second embodiment based on this finding.
  • the thin film transistor of the first embodiment is provided corresponding to a source electrode and a drain electrode, a semiconductor layer provided in contact with the source electrode and the drain electrode, and a channel between the source electrode and the drain electrode.
  • the semiconductor layer of the thin film transistor of the first embodiment further includes an additional oxidation in which the oxygen separation energy is smaller than that of tin oxide and the addition amount is smaller than that of the above metal oxide. It is a composite metal oxide to which a product is added.
  • the method for manufacturing a thin film transistor of this embodiment includes a step of forming the semiconductor layer at 10 ° C. or higher and 500 ° C. or lower when manufacturing the thin film transistor.
  • FIG. 8 is a schematic cross-sectional view of the thin film transistor 201 according to the first embodiment.
  • the substrate 202 a substrate formed using a known forming material can be used, and any of those having light transmittance and those having no light transmittance can be used.
  • an inorganic substrate made of alkali silicate glass, quartz glass, silicon nitride, or the like; a silicon substrate; a metal substrate whose surface is insulated; acrylic resin, polycarbonate resin, PET (polyethylene terephthalate), or PBT (polybutylene)
  • Various substrates such as a resin substrate made of a polyester resin such as terephthalate) or a paper substrate can be used.
  • the substrate may be a composite material formed by combining a plurality of these materials.
  • the thickness of the substrate 202 can be appropriately set according to the design.
  • the thin film transistor 201 is a so-called bottom gate type transistor.
  • the thin film transistor 201 includes a gate electrode 203 provided over a substrate 202, an insulator layer 204 provided to cover the gate electrode 203, a semiconductor layer 205 provided on the top surface of the insulator layer 204, A source electrode 208 and a drain electrode 209 are provided in contact with the semiconductor layer 205 on the upper surface.
  • the gate electrode 203 is provided so as to correspond to the channel region of the semiconductor layer 205 (at a position overlapping the channel region in plan view).
  • the semiconductor layer 205 is composed of a composite metal oxide obtained by adding a metal oxide 207 to tin oxide 206.
  • the semiconductor layer may contain components other than the metal oxide 207 and inevitable impurities as long as the adverse effects of the fourth invention of the present application are not adversely affected.
  • the semiconductor layer 205 can be seen as if particles of the metal oxide 207 are scattered in the tin oxide 206.
  • the metal oxide is actually uniformly added to the tin oxide, that is, doped, so that the composite metal oxide becomes a uniform material.
  • the gate electrode 203, the source electrode 208, and the drain electrode 209 those formed of a generally known material can be used.
  • the material for forming these electrodes include aluminum (Al), gold (Au), silver (Ag), copper (Cu), nickel (Ni), molybdenum (Mo), tantalum (Ta), and tungsten (W).
  • the material for forming these electrodes include aluminum (Al), gold (Au), silver (Ag), copper (Cu), nickel (Ni), molybdenum (Mo), tantalum (Ta), and tungsten (W).
  • metal materials such as these, alloys thereof, and conductive oxides such as indium tin oxide (ITO) and zinc oxide (ZnO).
  • these electrodes may form the laminated structure of two or more layers, for example by plating the surface with a metal material.
  • the gate electrode 203, the source electrode 208, and the drain electrode 209 may be formed of the same forming material, or may be formed of different forming materials.
  • the source electrode 208 and the drain electrode 209 are preferably made of the same material since manufacturing is easy.
  • the insulator layer 204 has an insulating property, and can be formed using either an inorganic material or an organic material as long as the gate electrode 203 can be electrically insulated from the source electrode 208 and the drain electrode 209. It may be formed.
  • the inorganic material include normally known insulating oxides such as SiO 2 , SiN x , SiON, Al 2 O 3 , and HfO 2 , nitrides, and oxynitrides.
  • the organic material include acrylic resin, epoxy resin, silicon resin, and fluorine resin.
  • the organic material is preferably a photocurable resin material because it is easy to manufacture and process.
  • the semiconductor layer 205 is obtained by adding, to tin oxide, a metal oxide in which the dissociation energy of oxygen is larger than the separation energy of oxygen in tin oxide and the difference in separation energy between the two is smaller than 200 kJ / mol.
  • tin oxide (SnO 2 ) is used as the first metal oxide in the above-mentioned prior application of the present inventors.
  • the separation energy of oxygen of tin oxide is as small as 528 kJ / mol, oxygen from tin oxide is reduced. Almost desorbs and easily generates oxygen deficiency.
  • the amount of oxygen vacancies becomes too large, it changes from semiconducting properties to metallic properties, making it unsuitable as a semiconductor layer.
  • the inventors of the present application added a metal oxide having an oxygen separation energy larger than that of tin oxide in order to control the oxygen deficiency of tin oxide.
  • the metal oxide that can be added include samarium oxide having an oxygen separation energy of 573 kJ / mol, tungsten oxide of 720 kJ / mol, neodymium oxide of 703 kJ / mol, and gadolinium oxide of 715 KJ / mol.
  • the content of the metal oxide added to make tin oxide a semiconductor layer having an appropriate oxygen deficiency is preferably in the range of greater than 0 to 50% by weight.
  • the semiconductor layer can be manufactured at a low temperature of 300 ° C. or less.
  • In-Zn-O-based and In-Ga-Zn-O-based metal oxides tend to be polycrystalline when a semiconductor layer is formed. Therefore, in a generally known thin film transistor, the surface of the semiconductor layer does not become flat due to crystal grains contained in the semiconductor layer. In addition, the normally known semiconductor layer of an oxide film transistor has a reduced electrical conductivity in the plane direction due to such crystal grains. Therefore, in order to obtain planarization of the surface of the semiconductor layer and high electrical conductivity, the semiconductor layer preferably has an amorphous structure.
  • the thickness of the semiconductor layer 205 is more preferably in the range of 5 nm to 20 nm.
  • the thickness of the semiconductor layer 205 was measured using a crystal oscillation type film thickness meter disposed mainly for film thickness calibration in the sputtering chamber in which the semiconductor layer 205 was formed.
  • the composite metal oxide constituting the semiconductor layer 205 is obtained by adding the above-described metal oxide to tin oxide, and further having an oxygen separation energy smaller than that of tin oxide.
  • an additional oxide having an addition amount smaller than that of the metal oxide is added. The inventors of the present application have found that the semiconductor layer becomes amorphous even in a high temperature range of 500 ° C. by controlling the amount of oxygen vacancies by adding a metal oxide and adding an additional oxide.
  • lead oxide having an oxygen release energy of 382.4 ⁇ 3.3 kJ / mol
  • palladium oxide having 238.1 ⁇ 12.6 kJ / mol
  • 418.6 ⁇ 11.6 kJ / mol mol
  • platinum oxide 517.90 ⁇ 0.05 kJ / mol sulfur oxide
  • 434 ⁇ 42 kJ / mol antimony oxide
  • 426.3 ⁇ 6.3 kJ / mol strontium oxide 213 ⁇ 84 kJ / mol thallium oxide, 387 7 ⁇ 10 kJ / mol ytterbium oxide and the like.
  • the thin film transistor 201 ′ of the second embodiment of the present invention shown in FIG. 9 has basically the same structure as the thin film transistor 201 of FIG. 8, but the semiconductor layer 205 ′ corresponding to the semiconductor layer 205 of FIG. It is a composite metal oxide in which the metal oxide 207 is added to the tin 206, and an additional oxide 210 in which the oxygen separation energy is smaller than that of the tin oxide and the addition amount is smaller than that of the metal oxide. . 9 that have the same reference numerals as the elements in FIG. 8 are the same as the corresponding elements in FIG. 8, and therefore, the description thereof is omitted.
  • the semiconductor layer 205 ′ (composite metal oxide) is made of tin oxide 206 for convenience of illustration also in FIG. 9. It is drawn in a form that can be seen as interspersed with additional oxides 210, but here again, these oxides are actually uniformly added or doped in the tin oxide. Therefore, it should be noted that the composite metal oxide is a uniform material.
  • the addition of the metal oxide tungsten oxide (WO 3 ) and the additional oxide ytterbium oxide (Yb 2 O 3 ) to the tin oxide (SnO 2 ) is performed, for example, at the target preparation stage of the sputtering method.
  • the addition amount can be controlled by changing the ratio of sputtering power by co-sputtering method using Sn—W—O target and Yb 2 O 3 target, and the content is larger than 0 and 10% by weight. The following is more preferable.
  • the semiconductor layer of the thin film transistor of this embodiment can also be formed by using physical vapor deposition (or physical vapor deposition).
  • examples of physical vapor deposition include vapor deposition and sputtering.
  • Examples of the vapor deposition method include vacuum vapor deposition, molecular beam vapor deposition (MBE), ion plating, and ion beam vapor deposition.
  • Examples of the sputtering method include conventional sputtering, magnetron sputtering, ion beam sputtering, ECR (electron cyclotron resonance) sputtering, and reactive sputtering.
  • a film forming method such as a reactive sputtering method, a DC (direct current) sputtering method, or a radio frequency (RF) sputtering method can be used.
  • the gate electrode 203 and the insulator layer 204 are formed on the substrate 202 by a generally known method, and then the semiconductor layer 205 is formed.
  • the semiconductor layer 205 includes a tin oxide powder and a metal oxide having an oxygen separation energy larger than that of the tin oxide, and the oxygen of the tin oxide and the metal oxide. It is manufactured by a physical vapor deposition method using a target which is a sintered body containing a powder having a difference in separation energy of less than 200 kJ / mol and a mixed gas of a rare gas and oxygen.
  • sputtering method as a physical vapor deposition method.
  • a sintered body of a tin oxide powder and a tungsten oxide powder may be employed as the target.
  • the target may be mixed with impurities such as an additive (metal oxide or the like) at a mass% or less of tungsten oxide.
  • impurities such as an additive (metal oxide or the like) at a mass% or less of tungsten oxide.
  • a metal oxide (such as zinc oxide) other than tin oxide and tungsten oxide may be mixed into the target at a ratio (weight ratio) equal to or lower than the tungsten oxide content in the target as an unintended impurity. .
  • the content of tungsten oxide contained in the sintered body is preferably more than 0 mass% and 50 mass% or less. Further, the content of tungsten oxide is more preferably 0% by mass to 5% by mass.
  • In-Zn-O-based and In-Ga-Zn-O-based metal oxides which are generally known oxide semiconductors, if indium oxide is the "host material” and zinc oxide or gallium oxide is the “guest material”
  • the guest material zinc oxide or gallium oxide
  • the guest material is mixed with 20-30% of the host material (indium oxide).
  • the semiconductor layer 205 of the thin film transistor 201 of the present embodiment is formed into a thin film using the sintered body as described above as a target.
  • the content of tungsten oxide is more preferably 0% by mass to 5% by mass, and thus the semiconductor layer 205 in the case of this preferable composition.
  • This oxide semiconductor has an extremely small content of the guest material (tungsten oxide) with respect to the host material (tin oxide) as compared with a conventionally known oxide semiconductor.
  • a mixed gas of a rare gas and oxygen is used as a process gas.
  • the rare gas include helium, neon, argon, krypton, and xenon.
  • the process gas does not include a compound having a hydrogen atom.
  • an amorphous semiconductor layer can be formed by performing a step of forming a semiconductor layer at 10 ° C. to 300 ° C.
  • a suitable crystallized semiconductor layer can be formed by performing the process at a temperature higher than 300 ° C. and lower than or equal to 500 ° C.
  • the step of forming the semiconductor layer is preferably performed at room temperature.
  • “implemented at room temperature” means that the semiconductor layer is not heated for the step of forming the semiconductor layer, and the temperature adjustment of the working environment is unnecessary.
  • sputtering method employed in the method for manufacturing the thin film transistor of the present embodiment known methods such as RF sputtering and DC sputtering can be used.
  • the target may be a sintered body of a mixture of these powders or a sintered body of each powder as long as tin oxide powder and tungsten oxide powder are used.
  • the semiconductor layer can be formed by co-sputtering using a plurality of sintered bodies.
  • silicon oxide has been described as the metal oxide, samarium oxide (Sm—O), tungsten oxide (W—O), neodymium oxide (Nd—O), and gadolinium oxide (Gd—O) were used instead. Even in this case, the semiconductor layer can be formed in a process range corresponding to the magnitude of the separation energy of oxygen.
  • the semiconductor layer 205 is formed after the gate electrode 203 and the insulator layer 204 are formed on the substrate 202 by a generally known method.
  • the semiconductor layer 205 has a difference of 200 kJ between the tin oxide powder and the oxygen separation energy of the tin oxide, and the oxygen separation energy of the tin oxide is 200 kJ.
  • a physical vapor deposition method using a target that is a sintered body containing a noble gas and a mixed gas of oxygen and oxygen.
  • a target may be a sintered body of a tin oxide powder, a tungsten oxide powder, and a ytterbium oxide powder. Further, the amount of ytterbium oxide added to the target is always smaller than the amount of tungsten oxide added.
  • the content of tungsten oxide contained in the sintered body is more than 0% by mass and 50% by mass or less
  • the content of ytterbium oxide is more than 0% by mass and less than 20% by mass.
  • the content of ytterbium oxide is more preferably 0% by mass to 4% by mass.
  • a mixed gas of a rare gas and oxygen is used as a process gas.
  • the rare gas include helium, neon, argon, krypton, and xenon.
  • the process gas does not include a compound having a hydrogen atom.
  • the process of forming the semiconductor layer is 10 ° C. or higher, as studied by the inventors. It was found that an amorphous semiconductor layer can be formed by carrying out at 500 ° C. or lower. Further, the step of forming the semiconductor layer is preferably performed at room temperature.
  • “implemented at room temperature” means that the semiconductor layer is not heated for the step of forming the semiconductor layer, and the temperature adjustment of the working environment is unnecessary.
  • sputtering method employed in the method for manufacturing the thin film transistor of the present embodiment known methods such as RF sputtering and DC sputtering can be used.
  • the characteristic change is suppressed by using the novel composite metal oxide for the semiconductor layer.
  • the semiconductor device having the above configuration it has a thin film transistor in which the characteristic change is suppressed, and has high reliability.
  • a thin film transistor in which a change in characteristics is suppressed can be easily manufactured by using a novel composite metal oxide for a semiconductor layer.
  • the fourth invention of the present application can also be applied to a so-called top gate type thin film transistor.
  • a so-called top contact type thin film transistor has been described.
  • the fourth invention of the present application can also be applied to a so-called bottom contact type thin film transistor.
  • the thin film transistor using an oxide semiconductor according to the fifth invention of the present application corresponds to a source electrode and a drain electrode, a semiconductor layer provided in contact with the source electrode and the drain electrode, and a channel between the source electrode and the drain electrode.
  • An oxidation in which oxygen vacancies are introduced comprising: a first metal oxide made of a material; and a second oxide having an oxygen separation energy greater than that of the first metal oxide by 200 kJ / mol or more.
  • the method for manufacturing a thin film transistor using an oxide semiconductor according to the fifth aspect of the present invention includes a step of forming the semiconductor layer at 10 ° C. or higher and 400 ° C. or lower when manufacturing the thin film transistor. You may have the process of forming the said semiconductor layer at 10 degreeC or more and 200 degrees C or less.
  • FIG. 15 is a schematic cross-sectional view showing an embodiment of a thin film transistor using an oxide semiconductor according to the fifth invention.
  • a thin film transistor 310 in FIG. 15 is a so-called bottom-gate transistor.
  • the thin film transistor 310 includes a gate electrode 330 provided on a substrate 320, an insulator layer (gate insulator layer) 340 provided so as to cover the gate electrode 330, and an insulator layer.
  • a substrate formed of a known forming material can be used, and any of those having light transmittance and those having no light transmittance may be used.
  • a material for forming the substrate 320 for example, an inorganic substrate made of alkali silicate glass, quartz glass, silicon nitride, or the like; a silicon substrate; a metal substrate with an insulating surface; acrylic resin, polycarbonate resin, PET ( Various substrates such as a resin substrate made of a polyester resin such as polyethylene terephthalate) or PBT (polybutylene terephthalate); a paper substrate can be used. Further, the substrate may be a composite material formed by combining a plurality of these materials. Further, the thickness of the substrate 320 can be appropriately set according to the design.
  • the gate electrode 330 is provided so as to correspond to the channel region of the semiconductor layer 350 (at a position overlapping the channel region in plan view). That is, the channel region of the semiconductor layer 350 is in a region corresponding to the position of the gate electrode 330.
  • the semiconductor layer of the thin film transistor mainly functions as a channel on the gate electrode side.
  • MoW is used as the gate electrode 330.
  • the semiconductor layer 350 is formed of the oxide semiconductor of the fifth invention of the present application.
  • the semiconductor layer 350 includes a first metal oxide made of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and an oxygen separation energy of the first metal oxide.
  • An oxide semiconductor having an oxygen deficient portion which is formed from a second oxide greater than the energy by 200 kJ / mol or more, and the oxygen deficient portion further includes an OH group, an H group, an F group, a Cl group, Alternatively, it is formed by the oxide semiconductor in which the first metal oxide and the substituent are bonded by being substituted by at least one selected from the group consisting of B groups.
  • the semiconductor layer 350 may contain components other than these and unavoidable impurities.
  • the first metal oxide is a substance having a semiconductor property capable of generating electron carriers by introducing oxygen vacancies.
  • the first metal oxide is preferably a metal oxide containing at least one selected from the group consisting of indium, gallium, zinc, and tin
  • the second oxide is preferably zirconium (Zr). , Silicon (Si), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), scandium (Sc), yttrium (Y), lanthanum (La), praseodymium (Pr), neodymium (Nd) , Gadolinium (Gd), other rare earth elements, aluminum (Al), and carbon (C).
  • the oxide includes at least one selected from the group consisting of carbon (C).
  • the element of the second oxide is at least one selected from the group consisting of Zr, Pr, Si, Ti, W, Ta, La, Hf, and C.
  • the element of the first oxide is Sn
  • the element of the second oxide is at least one element selected from the group consisting of Sc, Ti, W, Nd, and Gd.
  • a metal oxide containing at least one of indium, zinc, and tin may be used.
  • indium that easily introduces oxygen vacancies at a low temperature may be used.
  • silicon (Si), titanium (Ti), tungsten (W), tantalum (Ta), lanthanum (La), hafnium (Hf), zirconium (Zr), and praseodymium (Pr) are used. It is also possible to use an oxide containing at least one selected from the group consisting of silicon (Si), titanium (Ti), tungsten (W), tantalum (Ta), lanthanum (La), and hafnium.
  • the second oxide it is an oxide containing at least one selected from the group consisting of (Hf).
  • an oxide containing carbon (C) can also be used.
  • the content of the second oxide may be greater than 0 and 50% by weight or less, greater than 0 and 10% by weight or less, and greater than 0 and 5% by weight or less.
  • the substituent introduced into the oxygen deficient portion is specifically selected from the group consisting of an OH group, an H group, an F group, a Cl group, or a B group. At least one is mentioned. In particular, an OH group and an H group are preferable, and an OH group is more preferable.
  • the content is preferably 0.1% or more and 10% or less, and when H groups are introduced, the content is preferably greater than 0% and 0.1% or less, F
  • the group, Cl group, or B group is introduced, the content is preferably more than 5 ⁇ 10 18 atoms / cm 3 and not more than 1 ⁇ 10 21 atoms / cm 3 .
  • the OH group content (%) is calculated by the formula [OH] / ([OH] + [O]) ⁇ 100, and the H group content (%) is [H] / ([H] + [ O]) ⁇ 100.
  • [OH], [H], and [O] represent atomic ratios of OH, H, and O in the oxide semiconductor, respectively.
  • the oxygen separation energy of indium oxide is as small as 346 ⁇ 30 kJ / mol, so oxygen is easily desorbed from indium oxide to generate oxygen vacancies. Easy to do. However, if the amount of oxygen vacancies becomes too large, it changes from semiconducting properties to metallic properties and becomes unsuitable as a semiconductor layer. As a result of repeated studies to solve this problem, the inventors of the present application added a second oxide having an oxygen separation energy larger than that of indium oxide in order to control the oxygen deficiency amount of indium oxide. I found out that I should do. Specifically, when an oxide having an oxygen separation energy of 725 kJ / mol or more, more preferably 780 kJ / mol or more is used as the second oxide, the amount of oxygen deficiency of indium oxide can be easily controlled.
  • the oxygen separation energy of the second oxide is 200 kJ / mol or more, more preferably 255 kJ / mol compared to the first metal oxide. What is larger than mol may be used. Therefore, the oxygen separation energy of the second oxide may be 255 kJ / mol or more larger than the oxygen separation energy of the first metal oxide.
  • the second oxide includes zirconium oxide (Zr—O), praseodymium oxide (Pr—O), lanthanum oxide (La—O), and silicon oxide (Si—O). Tantalum oxide (Ta—O), and hafnium oxide (Hf—O).
  • the second oxide is particularly 780 kJ / mol or more shown in Table C1.
  • the second oxide is more preferable. Specifically, lanthanum oxide (La—O), silicon oxide (Si—O), tantalum oxide (Ta—O), and hafnium oxide (Hf—O) can be given.
  • the oxygen separation energy of titanium oxide (Ti—O) is 666.5 ⁇ 5.6 kJ / mol
  • the oxygen separation energy of tungsten oxide (W—O) is 720 ⁇ 71 kJ / mol.
  • the content of the second oxide added to the first metal oxide in order to make the first metal oxide a semiconductor layer 350 having a suitable oxygen deficiency ranges from 0 to 50% by weight.
  • the content of the second oxide added to the first metal oxide is in the range of more than 0 and 5% by weight or less in terms of production at a low temperature of 200 ° C. or less.
  • the semiconductor layer 350 (that is, the oxide semiconductor forming the semiconductor layer 350) is preferably amorphous. In-Zn-O-based and In-Ga-Zn-O-based metal oxides tend to be polycrystalline when a semiconductor layer is formed. Therefore, in a generally known thin film transistor, the surface of the semiconductor layer does not become flat due to crystal grains contained in the semiconductor layer. In addition, the normally known semiconductor layer of an oxide film transistor has a reduced electrical conductivity in the plane direction due to such crystal grains. Therefore, in order to obtain planarization of the surface of the semiconductor layer and high electrical conductivity, the semiconductor layer 350 preferably has an amorphous structure.
  • the thickness of the semiconductor layer 350 (that is, the thickness of the oxide semiconductor forming the semiconductor layer 350) is preferably in the range of 5 nm to 20 nm. In the present embodiment, the thickness was measured using a crystal oscillation type film thickness meter disposed mainly for the purpose of film thickness calibration in the sputtering chamber in which the semiconductor layer 350 was formed.
  • the second oxide may include an oxide of carbon (C).
  • C an oxide of carbon
  • an element that forms an oxide having a larger separation energy than the first metal oxide may be added.
  • the oxide semiconductor into which oxygen vacancies are introduced may be one in which an oxide of carbon (C) is added to the first metal oxide. This is because the oxygen desorption energy of the C—O bond is as large as 1076.38 ⁇ 0.67 kJ / mol, so that the amount of oxygen deficiency introduced into the first metal oxide can be easily controlled.
  • the oxide When the oxide is added to the first metal oxide, it is not always necessary to add the oxide itself in the addition treatment operation itself. For example, a treatment for adding an element other than oxygen constituting the oxide is performed. An oxide can also be formed inside one metal oxide. Therefore, in the present application, regardless of the form of the addition treatment operation, the addition in the form of the oxide in the first metal oxide is referred to as “adding the oxide”. Please be careful.
  • the addition of carbon (C) to the first metal oxide indium oxide (In 2 O 3 ) is to change the ratio of the sputtering power by a co-sputtering method using an In 2 O 3 target and a graphite target.
  • the amount added can be controlled by the control, and the content is more preferably greater than 0 and 10% by weight or less. Therefore, the content of carbon (C) contained as the second oxide is preferably greater than 0 and 10% by weight or less.
  • the states of the first metal oxide and the second oxide in the semiconductor layer 350 are uniform (that is, uniform by adding or doping the second oxide into the first metal oxide uniformly). It is a substance).
  • the source electrode 360, the drain electrode 370, and a region that does not overlap with the source electrode 360 and the drain electrode 370 and corresponds to the position of the gate electrode 330 corresponds to a channel region.
  • the contact resistance is lowered by metallization.
  • the gate electrode 330 is provided so as to correspond to the channel region of the semiconductor layer 350 (at a position overlapping the channel region in a plan view).
  • the gate electrode 330, the source electrode 360, and the drain electrode 370 those formed of a generally known material can be used.
  • materials for forming these electrodes include aluminum (Al), gold (Au), silver (Ag), copper (Cu), nickel (Ni), molybdenum (Mo), tantalum (Ta), and tungsten (W).
  • metal materials such as these, alloys thereof, and conductive oxides such as indium tin oxide (ITO) and zinc oxide (ZnO).
  • these electrodes may form a laminated structure of two or more layers (for example, Ti / Al / Ti) by, for example, plating the surface with a metal material.
  • the gate electrode 330, the source electrode 360, and the drain electrode 370 may be formed of the same forming material, or may be formed of different forming materials. Since manufacture becomes easy, it is preferable that the source electrode 360 and the drain electrode 370 are the same formation material.
  • the insulator layer (gate insulator layer) 340 is an insulating material and an organic material as long as it has insulating properties and can electrically insulate the gate electrode 330 from the source electrode 360 and the drain electrode 370. Any of the materials may be used.
  • the inorganic material include normally known insulating oxides such as SiO 2 , SiN x , SiON, Al 2 O 3 , and HfO 2 , nitrides, and oxynitrides.
  • the organic material include acrylic resin, epoxy resin, silicon resin, and fluorine resin.
  • the organic material is preferably a photocurable resin material because it is easy to manufacture and process.
  • the insulator layer (gate insulator layer) 340 has a two-layer laminated structure in which a SiN layer is disposed at a contact portion of the substrate 320 and SiO 2 is disposed thereon.
  • This SiN layer can prevent the calcium, phosphorus, etc. generated from the substrate 320 from diffusing and deteriorating the semiconductor layer 350, and the SiO 2 disposed thereon is caused by the diffusion of nitrogen from the SiN layer. This is because deterioration of the semiconductor layer can be prevented.
  • the interlayer insulating film 380 has insulating properties, and can electrically insulate the source electrode 360, the drain electrode 370, and the source electrode 360 and the semiconductor layer 350 in a region not overlapping with the drain electrode 370. If so, it may be formed using either an inorganic material or an organic material.
  • the inorganic material include normally known insulating oxides such as SiO 2 , SiN x , SiON, Al 2 O 3 , and HfO 2 , nitrides, and oxynitrides.
  • the organic material include acrylic resin, epoxy resin, silicon resin, and fluorine resin. The organic material is preferably a photocurable resin material because it is easy to manufacture and process.
  • the oxide semiconductor of this embodiment can also be formed by using physical vapor deposition (or physical vapor deposition).
  • physical vapor deposition include vapor deposition and sputtering.
  • the vapor deposition method include vacuum vapor deposition, molecular beam vapor deposition (MBE), ion plating, and ion beam vapor deposition.
  • the sputtering method examples include conventional sputtering, magnetron sputtering, ion beam sputtering, ECR (electron cyclotron resonance) sputtering, and reactive sputtering.
  • a film forming method such as a reactive sputtering method, a DC (direct current) sputtering method, or a radio frequency (RF) sputtering method can be used.
  • the first metal oxide composed of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and the oxygen separation energy of the first metal oxide is greater than the oxygen separation energy of the first metal oxide.
  • an oxide semiconductor having an oxygen deficient portion which is formed from a second oxide that is greater than or equal to 200 kJ / mol, is formed.
  • a target that is a sintered body including a first metal oxide powder and an oxide powder having an oxygen separation energy of 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide; It is manufactured by a physical vapor deposition method using a mixed gas of a rare gas and oxygen.
  • sputtering method as a physical vapor deposition method.
  • a first metal oxide composed of a metal oxide capable of generating electron carriers by introducing oxygen vacancies
  • the oxygen separation energy of the first metal oxide is 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide.
  • the target is an indium oxide powder and a silicon oxide powder. It is preferable to employ a sintered body.
  • the target may be mixed with impurities such as an additive (metal oxide or the like) at a weight percent or less of silicon oxide.
  • metal oxides such as zinc oxide
  • indium oxide and silicon oxide may be mixed into the target at a ratio (weight ratio) equal to or lower than the silicon oxide content in the entire target as unintended impurities. Absent.
  • the content of silicon oxide contained in the sintered body is preferably more than 0% by weight and 50% by weight or less. Further, the content of silicon oxide is more preferably more than 0 wt% and not more than 5 wt%.
  • In-Zn-O-based and In-Ga-Zn-O-based metal oxides which are generally known oxide semiconductors, if indium oxide is the "host material” and zinc oxide or gallium oxide is the “guest material”
  • the guest material zinc oxide or gallium oxide
  • the guest material is mixed with 20-30% of the host material (indium oxide).
  • the silicon oxide content is more preferably more than 0 wt% and not more than 5 wt% as described above. Therefore, the semiconductor layer in this preferred composition
  • the 350 oxide semiconductor has an extremely small content of the guest material (silicon oxide) with respect to the host material (indium oxide) as compared with a conventionally known oxide semiconductor.
  • a mixed gas of a rare gas and oxygen is used as a process gas.
  • the rare gas include helium, neon, argon, krypton, and xenon.
  • the process gas does not include a compound having a hydrogen atom.
  • the first metal oxide composed of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and the oxygen separation energy.
  • an oxide semiconductor having an oxygen deficient portion which is formed from a second oxide having a larger oxygen dissociation energy than the first metal oxide by 200 kJ / mol or more, indium oxide and silicon oxide are used.
  • a target including the oxide semiconductor it has been found that a high temperature is not required to make the metal oxide constituting the oxide semiconductor an amorphous film.
  • an amorphous oxide semiconductor is formed by performing the step of forming an In—Si—O system into which oxygen vacancies are introduced at 10 ° C. or higher and 200 ° C. or lower. can do.
  • a suitable crystallized oxide semiconductor can be formed.
  • the step of forming the oxide semiconductor is preferably performed at room temperature.
  • “implemented at room temperature” means non-heating for the step of forming an oxide semiconductor, and does not require temperature adjustment of the working environment.
  • sputtering method employed in the method for manufacturing an oxide semiconductor according to this embodiment known methods such as RF sputtering and DC sputtering can be used.
  • the target may be a sintered body of a mixture of these powders or a sintered body of each powder, as long as the target uses indium oxide powder and silicon oxide powder.
  • a sintered body is formed for each metal oxide powder, an oxide semiconductor in which the amount of oxygen vacancies is controlled by co-sputtering using a plurality of sintered bodies can be formed.
  • Silicon oxide has been described as the second oxide, but instead zirconium oxide (Zr—O), praseodymium oxide (Pr—O), lanthanum oxide (La—O), tantalum oxide (Ta—O), and oxidation Even when hafnium (Hf—O) is used, an oxide semiconductor in which the amount of oxygen vacancies is controlled can be formed in a process range corresponding to the magnitude of the separation energy of oxygen.
  • a substituent is introduced into the oxygen deficient portion of the oxide semiconductor having the oxygen deficient portion thus manufactured.
  • the substituent to be introduced at least one selected from the group consisting of OH group, H group, F group, Cl group, or B group can be used.
  • an OH group is introduced into the oxygen deficient part, it is introduced by heat treatment under high humidity. For example, it sealed 80% or more high humidity of introducing H 2 O gas into the quartz reaction vessel, at a temperature range of 300 ° C. from 0.99 ° C., introduced by heat treatment.
  • H group into the oxygen deficient portion it is introduced by heat treatment in an H 2 atmosphere gas. For example, it is introduced by annealing at 300 to 400 ° C. under H 2 atmosphere gas.
  • an F group, a Cl group, or a B group is introduced into the oxygen deficient portion, it is introduced by ion implantation (ion implantation) or a plasma treatment method.
  • the gate electrode 330 and the insulator layer (gate insulator layer) 340 are formed on the substrate 320 by a generally known method, and then the semiconductor is formed on the upper surface of the insulator layer 340.
  • Layer 350 is formed.
  • the semiconductor layer 350 is formed using an oxide semiconductor manufactured by the above-described manufacturing method.
  • the gate electrode 330 is provided so as to correspond to the channel region of the semiconductor layer 350 (at a position overlapping the channel region in a plan view).
  • the source electrode 360 and the drain electrode 370 are provided on the semiconductor layer 350 so that a part of the semiconductor layer 350 overlaps the source electrode 360 and the drain electrode 370 by a generally known method, and further, the whole (specifically, Covers the source electrode 360, the drain electrode 370, and the semiconductor layer 350 in a region not overlapping with the source electrode 360 and the drain electrode 370, with the interlayer insulating film 380. In this manner, the thin film transistor 310 with high reliability with respect to light irradiation from the light emitting layer can be manufactured.
  • the change in characteristics is suppressed by using a novel oxide semiconductor for the semiconductor layer.
  • the semiconductor device using the thin film transistor having such a structure has high reliability because it has a thin film transistor in which the characteristic change is suppressed.
  • a thin film transistor in which a change in characteristics is suppressed by using a novel oxide semiconductor for a semiconductor layer can be easily manufactured.
  • Example A1 In this example, the thin film transistor shown in FIG. 2 was manufactured and the operation was confirmed.
  • the thin film transistor shown in the figure has substantially the same configuration as that of the thin film transistor 10 shown in FIG. 1, and instead of the gate electrode 30 included in the thin film transistor 10 shown in FIG. Is used.
  • the thin film transistor of the example uses a Si substrate doped with a p-type impurity, forms the insulator layer 24 by oxidizing the surface, and then forms the semiconductor layer 25 on the surface of the insulator layer 24 using a method described later. It was manufactured by doing.
  • the source electrode 26 and the drain electrode 27 were formed by mask vapor deposition on the surface of the semiconductor layer 25.
  • the source electrode 26 and the drain electrode 27 were made of gold (Au) as a forming material and had a thickness of 50 nm. Further, the separation distance (gate length) between the source electrode 26 and the drain electrode 27 was 350 ⁇ m, and the length of the facing portion was 940 ⁇ m.
  • the oxide semiconductor layer 25 uses an In—Si—O target with a SiO 2 concentration of 10% by weight and an In—Ti—O target with a Ti concentration of 10% by weight.
  • Flow rate: O 2 / Ar 3 sccm / 20 sccm, degree of vacuum 0.25 Pa, without heating, as shown in Table A3, continuously changing the sputtering power for each target according to the film thickness formed, An In—Ti—Si—O film with a thickness of 60 nm was formed.
  • FIG. 4 shows the results obtained by depth resolution XPS measurement of the concentration distribution of Ti and Si elements in the fabricated In—Ti—Si—O film while Ar etching.
  • An In—Ti—Si—O film having a high Ti concentration, a low Si concentration, and a reverse concentration gradient in the central portion was formed on the side close to the gate insulating film 24 and the source / drain electrode 26/27 side.
  • the Id—Vg characteristics after an evaluation environment of 25 ° C. and light irradiation for 1000 seconds were measured.
  • FIG. 7 also shows the Id—Vg characteristics of an In—Ti—O thin film transistor. It can be seen that by irradiation with light having a wavelength of 420 to 600 nm, the I-off value of In—Ti—O increases and the threshold voltage also shifts to the negative side. On the other hand, the In—Si—O—N thin film transistor had almost the same characteristics after light irradiation as before light irradiation, and hardly deteriorated. Note that the Id-Vg characteristics of the In—Si—O—N thin film transistor and the In—Ti—O thin film transistor before light irradiation were substantially the same as those indicated by the broken line in FIG.
  • IGZO In—Ga—Zn—O
  • the thin film transistor using IGZO has a large threshold voltage shift of about 2 V due to light irradiation, and the electron mobility is as small as 5 cm 2 / Vs.
  • the thin film transistor using In—Ti—Si—O of Example A1 showed a high threshold voltage shift smaller than 1 V and an electron mobility close to 10 cm 2 / Vs.
  • the thin film transistor using In—Ti—Si—O of Example A1 has low contact resistance at the interface between the source electrode 26 / drain electrode 27 and the semiconductor layer 25, and has excellent gate controllability. It was.
  • Example B1 In this example corresponding to the first embodiment, the thin film transistor shown in FIG. 10 was manufactured and the operation was confirmed.
  • the thin film transistor shown in the figure has the same structure as that of the thin film transistor 201 shown in FIG. 8, and uses a Si layer 211 doped with a large amount of p-type impurities in place of the gate electrode 203 included in the thin film transistor 201 shown in FIG. It has become.
  • the thin film transistor of the example uses a Si substrate doped with a p-type impurity, forms the insulator layer 204 by oxidizing the surface, and then forms the semiconductor layer 205 on the surface of the insulator layer 204 using a method described later. It was manufactured by doing.
  • the source electrode 208 and the drain electrode 209 were formed by mask vapor deposition on the surface of the semiconductor layer 205.
  • the source electrode 208 and the drain electrode 209 are made of gold (Au) and have a thickness of 50 nm. Further, the separation distance (gate length) between the source electrode 208 and the drain electrode 209 was 350 ⁇ m, and the length of the facing portion was 940 ⁇ m.
  • the semiconductor layer 205 was formed by a sputtering method (DC sputtering) using a sputtering apparatus and using a Sn—W—O target as a target material under the following sputtering conditions.
  • a Sn—W—O target a 20% W-added Sn-based sample product was used.
  • the thickness of the deposited semiconductor layer 205 was 20 nm.
  • FIG. 11 shows the measurement results of the transfer characteristics of this thin film transistor.
  • FIG. 12 shows the electrical conduction characteristics of Sn—O and Sn—W—O thin film transistors when the ratio of O 2 / (Ar + O 2 ) is changed in the range of 5 to 25% under the above sputtering conditions.
  • Sn—W—O exhibits superior electrical conductivity compared to Sn—O at all oxygen ratios in FIG. This is suitable from tin oxide (Sn—O) with high accuracy because the oxygen dissociation energy of W—O bond (720 ⁇ 71 kJ / mol) is larger than that of Sn—O (528 kJ / mol). This is the effect of controlling the amount of oxygen deficiency by desorbing oxygen.
  • Sn—W—O indicates that the change in electrical conduction characteristics is smaller than the change in the ratio of O 2 / (Ar + O 2 ). From this result, it can be seen that Sn—W—O has a larger process margin.
  • the semiconductor layer 205 was formed by a sputtering method (DC sputtering) using a sputtering apparatus and using a Sn—W—Yb—O target as a target material under the following sputtering conditions.
  • Sn—W—O target 20% W and 2% Yb-added Sn-based sample products were used.
  • the thickness of the deposited semiconductor layer 205 was 20 nm.
  • FIG. 14 shows the results of measuring the characteristics of the thin film transistor of the fourth invention.
  • Example C the fifth invention of the present application will be described by Example C, but the fifth invention of the present application is not limited to these Examples.
  • Example C the thin film transistor 400 shown in FIG. 16 was manufactured and the operation was confirmed.
  • a substrate 450 that is a Si layer doped with a large amount of p-type impurities is used as the gate electrode instead of the gate electrode 330 shown in FIG.
  • the thin film transistor of Example C uses a Si substrate 450 doped with a p-type impurity, forms an insulator layer 410 by oxidizing the surface, and then forms an oxide semiconductor on the surface of the insulator layer 410 using a method described later.
  • the semiconductor layer 420 was formed.
  • the source electrode 430 and the drain electrode 440 were formed by mask vapor deposition on the surface of the semiconductor layer 420 of an oxide semiconductor.
  • the source electrode 430 and the drain electrode 440 are made of gold (Au) and have a thickness of 50 nm. Further, the distance (gate length) between the source electrode 430 and the drain electrode 440 was 350 ⁇ m, and the length of the facing portion was 940 ⁇ m.
  • an oxide semiconductor layer 420 was fabricated as follows.
  • FIG. 17 shows the results of In3d XPS spectra of the In—Si—O film before and after the heat treatment at 150 ° C.
  • FIG. 17 shows the results of In3d XPS spectra of the In—Si—O film before and after the heat treatment at 150 ° C.
  • (a) is an In3dXPS spectrum of an In—Si—O semiconductor before the heat treatment
  • (b) is an In3dXPS spectrum of an In—Si—O semiconductor having an In—OH bond after the heat treatment.
  • the peak position due to the In—OH bond in the In—Si—O semiconductor into which the —OH group was introduced after the heat treatment was found at 444 eV, and the In—Si—O semiconductor before the heat treatment was observed.
  • the peak position due to the In—O bond in is observed at 443.5 eV.
  • the peak position due to the In—OH bond in the In—Si—O semiconductor into which the —OH group is introduced after the heat treatment is the peak position due to the In—O bond in the In—Si—O semiconductor before the heat treatment.
  • the content of OH groups to be introduced is preferably 0.1% or more and 10% or less. If it becomes 10% or less, it is possible to avoid a source of mobile ions (herein, “mobile ions” means ions localized in the oxide corresponding to the application of positive and negative voltages). This is because the metal behavior can be prevented from being more than the property of the semiconductor.
  • FIG. 18 shows the result of showing the I d -V g characteristics after irradiation with light having a wavelength of 420 nm or more and 600 nm or less for 100 seconds.
  • FIG. 18A shows the I d -V g characteristics of an In—Si—O semiconductor into which OH groups have not been introduced before light irradiation and an In—Si—O semiconductor having an In—OH bond before light irradiation.
  • (B) shows the I d -V g characteristics of an In—Si—O semiconductor having an In—OH bond after light irradiation
  • (c) shows an In group in which no OH group has been introduced after light irradiation.
  • the I d -V g characteristic of the —Si—O semiconductor is shown. As shown in FIG. 18, the I d -V g characteristics of the thin film transistor using the In—Si—O semiconductor having In—OH bonds before and after the light irradiation were almost the same. On the other hand, the I d -V g characteristics before and after the light irradiation of the thin film transistor using an In—Si—O semiconductor into which no OH group is introduced show that the I d curve shifts to the negative side compared to before the light irradiation, and is off. The current (I off ) value also tended to increase.
  • a thin film transistor using an In—Si—O semiconductor into which no OH group has been introduced cannot sufficiently suppress “threshold voltage shift” with respect to light irradiation having a wavelength of 420 nm to 600 nm. It was found that the “threshold voltage shift” can be sufficiently suppressed by introducing a group.
  • characteristic deterioration such as shift of threshold current due to light irradiation is suppressed, contact resistance at the interface between the source electrode and / or drain electrode and the semiconductor layer is low, and electron mobility is low. It is possible to provide thin film transistors that have high practical value, such as high gate control, and can be used in various industrial fields including liquid crystal displays and organic EL displays. Have sex.
  • the present invention can be applied to a semiconductor device such as a semiconductor element such as a thin film transistor and an electronic device such as an organic EL display or a liquid crystal display for which improvement in reliability with respect to light irradiation from a layer is desired.

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Abstract

The present invention addresses the problem of providing: a thin-film transistor that achieves a good balance between suppressing property deterioration due to light irradiation, low contact resistance, and excellent gate controllability; and a method for producing the same. The problem is solved by this thin-film transistor comprising a source electrode, a drain electrode, a semiconductor layer that is provided so as to be in contact with the source electrode and the drain electrode, a gate electrode that is provided so as to correspond to a channel between the source electrode and the drain electrode, and an insulator layer that is provided between the gate electrode and the semiconductor layer. The semiconductor layer is formed from a composite metal oxide obtained by adding, to a first metal oxide capable of generating electron carriers by means of introduction of oxygen defects, a second oxide having an oxygen dissociation energy larger than the oxygen dissociation energy of the first metal oxide by 200 kJ/mol or more; and the concentration of a specific element among the elements constituting the second oxide is the maximum value or the minimum value in the center portion of the semiconductor layer in the thickness direction.

Description

薄膜トランジスタ、酸化物半導体、およびその製造方法Thin film transistor, oxide semiconductor, and manufacturing method thereof

 本願第1~第3発明は、酸化物薄膜トランジスタおよびその製造方法に関するものである。
 また本願第4発明は、薄膜トランジスタおよびその製造方法に関するものである。
 さらに本願第5発明は、酸化物半導体及びその製法、並びにそれを用いる薄膜トランジスタおよび半導体装置に関するものである。
The first to third inventions of the present application relate to an oxide thin film transistor and a method for manufacturing the same.
The fourth invention of the present application also relates to a thin film transistor and a method for manufacturing the same.
Further, the fifth invention of the present application relates to an oxide semiconductor, a manufacturing method thereof, a thin film transistor using the same, and a semiconductor device.

 薄膜トランジスタ(Thin Film Transistor(TFT))は、アクティブマトリクス駆動方式を採用する液晶ディスプレイや有機エレクトロルミネッセンス(Electro Luminescence(EL))ディスプレイのスイッチング素子として数多く利用されている。 Thin film transistors (TFTs) are widely used as switching elements for liquid crystal displays and organic electroluminescence (EL) displays that employ an active matrix drive system.

 TFTとしては、半導体層(チャネル層)にアモルファスシリコンやポリシリコンを用いたものが知られている。近年では、種々の特性向上を図るため、半導体層にIn(インジウム)-Zn(亜鉛)-O(IZO)系、In-Ga(ガリウム)-Zn-O(IGZO)系、あるいはSn(錫)-Zn-O(SZO)系の金属酸化物を用いたTFTが検討されている(例えば、特許文献1参照)。 As the TFT, a semiconductor layer (channel layer) using amorphous silicon or polysilicon is known. In recent years, in order to improve various characteristics, the semiconductor layer has an In (indium) -Zn (zinc) -O (IZO) system, an In-Ga (gallium) -Zn-O (IGZO) system, or Sn (tin). A TFT using a —Zn—O (SZO) -based metal oxide has been studied (for example, see Patent Document 1).

 このような薄膜トランジスタはn型伝導であり、アモルファスシリコンやポリシリコンよりも高いチャネル移動度を示すことから、高精細なディスプレイや大画面のディスプレイのスイッチング素子として好適に用いることができる。n型伝導のメカニズムは諸説あるが、主に、酸化インジウム構造への酸素脱離により酸素欠損が導入され、その結果、電荷を生成して半導体層として働くと言われている。また、金属酸化物を形成材料とする半導体層には、原理上p型伝導を示さないためにoff電流がきわめて小さくなることから、薄膜トランジスタを用いると消費電力を低減できるという利点を有する。 Since such a thin film transistor has n-type conductivity and exhibits higher channel mobility than amorphous silicon or polysilicon, it can be suitably used as a switching element for a high-definition display or a large-screen display. Although there are various theories about the mechanism of n-type conduction, it is said that oxygen vacancies are mainly introduced by desorption of oxygen to the indium oxide structure, and as a result, charge is generated to serve as a semiconductor layer. In addition, since a semiconductor layer made of a metal oxide does not exhibit p-type conduction in principle and has a very small off current, the use of a thin film transistor has an advantage that power consumption can be reduced.

 また、薄膜トランジスタの半導体層を構成する金属酸化物としてIZOやIGZOに代わって、錫、チタン、タングステンのいずれかをドープした酸化インジウムを用いることが提案されている(例えば、特許文献2参照)。 Further, it has been proposed to use indium oxide doped with either tin, titanium, or tungsten in place of IZO or IGZO as a metal oxide constituting the semiconductor layer of the thin film transistor (see, for example, Patent Document 2).

 さらに、これらの薄膜トランジスタの半導体層において、各種金属や窒素等の元素に厚み方向の濃度勾配を持たせることも提案されている(例えば、特許文献3から6参照)。 Furthermore, it has also been proposed to give concentration gradients in the thickness direction to elements such as various metals and nitrogen in the semiconductor layers of these thin film transistors (see, for example, Patent Documents 3 to 6).

 薄膜トランジスタは、上述のように液晶ディスプレイや有機エレクトロルミネッセンスディスプレイのスイッチング素子として好ましく用いられることから、その使用において比較的高強度の可視光が照射される。そのうち比較的短波長(高エネルギー)の成分、例えば波長420nm(2.95eV)の光照射によって、薄膜トランジスタのしきい値電圧がシフトするなど特性が劣化する場合があり、実用上その抑制が求められている。さらに、薄膜トランジスタにおいては、ソース電極及び/又はドレイン電極と半導体層との界面におけるコンタクト抵抗が低いこと、並びに電子移動度が高く、ゲート制御性に優れることが望ましく、これらの特性に優れることも求められている。 Since the thin film transistor is preferably used as a switching element of a liquid crystal display or an organic electroluminescence display as described above, a relatively high-intensity visible light is irradiated in its use. Among them, characteristics of relatively short wavelength (high energy) components, for example, light irradiation with a wavelength of 420 nm (2.95 eV) may deteriorate characteristics such as a shift in threshold voltage of a thin film transistor. ing. Further, in the thin film transistor, it is desirable that the contact resistance at the interface between the source electrode and / or drain electrode and the semiconductor layer is low, that the electron mobility is high, and that the gate controllability is excellent, and that these characteristics are also excellent. It has been.

 また、特許文献1に記載された金属酸化物であるIZO系やIGZO系やSZO系金属酸化物は、含有するZn、GaおよびSnが空気中の水分と反応しやすく、その結果、各々の酸化物構造としては不安定なサブオキサイドを形成して、酸素欠損量を調整できず、トランジスタ特性を大きく劣化させる問題があった。 Further, the IZO, IGZO, and SZO metal oxides, which are metal oxides described in Patent Document 1, can easily react with the water in the Zn, Ga, and Sn contained therein. As a physical structure, unstable suboxide is formed, and the amount of oxygen vacancies cannot be adjusted, resulting in a problem of greatly degrading transistor characteristics.

 これらを解決するために、特許文献7には、金属酸化物として、亜鉛および錫のうちの少なくとも一つの元素を含む物質へ、イットリウム、ニオビウム、タンタル、ハフニウム、ランタン、スカンジウム、バナジウム、チタニウム、マグネシウム、アルミニウム、ガリウム及びシリコンの少なくとも一つを添加したものを使用することが開示されている。また、薄膜トランジスタの作製段階で、プラズマダメージによる破壊効果や放射効果によるキャリア増加がもたらすしきい値電圧の変動を抑制するために、酸化亜鉛にガリウム、インジウム、スズ、ジルコニウム、ハフニウムおよびバナジウムのうち少なくとも一つのイオンをドープすることが開示されている(特許文献8)。さらに、タンタルをドープしたIZO系金属酸化物の酸化膜トランジスタの電気特性が報告されている(非特許文献1)。しかしながら、上記いずれの場合にも主な元素として亜鉛を含むために、薄膜トランジスタの作製段階でのサブオキサイドの形成を抑えるためにプロセスにかなりの制限が課せられるという大きな問題を含んでいる。 In order to solve these problems, Patent Document 7 discloses, as a metal oxide, a material containing at least one element of zinc and tin, yttrium, niobium, tantalum, hafnium, lanthanum, scandium, vanadium, titanium, magnesium. It is disclosed that at least one of aluminum, gallium and silicon is used. In addition, in order to suppress fluctuations in threshold voltage caused by the destruction effect due to plasma damage and the increase in carriers due to radiation effects in the thin film transistor manufacturing stage, at least one of gallium, indium, tin, zirconium, hafnium, and vanadium is added to zinc oxide. It is disclosed to dope one ion (Patent Document 8). Furthermore, electrical characteristics of an oxide film transistor of an IZO metal oxide doped with tantalum have been reported (Non-Patent Document 1). However, in any of the above cases, since zinc is contained as a main element, there is a serious problem that a considerable limitation is imposed on the process in order to suppress the formation of suboxides in the thin film transistor manufacturing stage.

 さらに、金属酸化物としてIZOやIGZOに代わって、錫、チタン、タングステンのいずれかをドープした酸化インジウムを用いるという報告もある(特許文献2)。しかしながら、上記文献に記載のチタン、タングステンのいずれかをドープした酸化インジウムを金属酸化物として用いた酸化膜トランジスタでは、金属酸化物の作製段階で主構造の酸化インジウムへ導入する酸素欠損量を調整することが非常に難しいために、製造プロセスに制限が課せられるという大きな問題がある。 Furthermore, there is a report that indium oxide doped with either tin, titanium, or tungsten is used instead of IZO or IGZO as a metal oxide (Patent Document 2). However, in the oxide film transistor using indium oxide doped with either titanium or tungsten described in the above document as the metal oxide, the amount of oxygen vacancies introduced into the main structure indium oxide is adjusted at the metal oxide production stage. There is a big problem that the manufacturing process is limited because it is very difficult to do.

 本発明者らは、酸化インジウム等の第1金属酸化物へ金属(Me)-O結合あるいは非金属-O結合の酸素のかい離エネルギーが第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな酸化物を添加することで、上記の問題の酸素欠損の量を制御した薄膜トランジスタおよびその製造方法を出願した(特願2013-099284号)。しかし、上記の問題を解決しつつ他の多様な要件をも満たすためには、上述の先行特許出願に記載した条件以外で上記問題を解決する手段を見出すことにより、この問題を解決した薄膜トランジスタの設計の自由度をできるだけ大きくすることが依然として望まれている。 The inventors of the present invention have described that the oxygen separation energy of the metal (Me) -O bond or nonmetal-O bond to the first metal oxide such as indium oxide is 200 kJ / mol than the oxygen separation energy of the first metal oxide. A thin film transistor in which the amount of oxygen vacancies in the above problem was controlled by adding a large oxide as described above and a method for manufacturing the same were filed (Japanese Patent Application No. 2013-099284). However, in order to satisfy other various requirements while solving the above-mentioned problem, by finding a means for solving the above-mentioned problem other than the conditions described in the above-mentioned prior patent application, It remains desirable to have as much design freedom as possible.

 また上述のように、TFTに用いられる、半導体層(チャネル層)にアモルファスシリコンやポリシリコンを用いたものが知られており、近年では、種々の特性向上を図るため、半導体層に種々の金属酸化物を用いたTFTが検討されている(例えば、特許文献1参照)。 In addition, as described above, a semiconductor layer (channel layer) using amorphous silicon or polysilicon used for a TFT is known. In recent years, various metals are used for a semiconductor layer in order to improve various characteristics. A TFT using an oxide has been studied (for example, see Patent Document 1).

 更に、特許文献9には、酸化物半導体膜上に接してソース電極層及びドレイン電極層を設けたトランジスタを有する半導体装置が開示されている。
 また、特許文献10には、酸化物半導体を用いた半導体装置の作製方法において、酸化物半導体膜と、酸化物半導体膜上に設けられるゲート絶縁膜と、ゲート絶縁膜に接するゲート電極と、ゲート電極に接するサイドウォール絶縁膜と、酸化物半導体膜に接するソース電極及びドレイン電極と、を形成する工程を有し、ゲート絶縁膜及びサイドウォール絶縁膜が、酸化物半導体膜に含まれる酸素の脱離を抑制する温度よりも低い温度で形成する方法が開示されている。
Further, Patent Document 9 discloses a semiconductor device including a transistor in which a source electrode layer and a drain electrode layer are provided in contact with an oxide semiconductor film.
In Patent Document 10, in a method for manufacturing a semiconductor device using an oxide semiconductor, an oxide semiconductor film, a gate insulating film provided over the oxide semiconductor film, a gate electrode in contact with the gate insulating film, and a gate A step of forming a sidewall insulating film in contact with the electrode and a source electrode and a drain electrode in contact with the oxide semiconductor film, and the gate insulating film and the sidewall insulating film release oxygen contained in the oxide semiconductor film. A method of forming at a temperature lower than the temperature at which separation is suppressed is disclosed.

 また、特許文献11には、絶縁性基板上のゲート電極、該ゲート電極上のゲート絶縁膜、該ゲート絶縁膜上のインジウムを含む酸化物半導体膜、及び該酸化物半導体膜上のソース・ドレイン電極を有し、該酸化物半導体膜のソース・ドレイン電極が重ならない部分の表面層におけるXPSスペクトルのインジウム3d軌道起因のピーク位置が、該表面層の下部に存在する酸化物半導体領域におけるXPSスペクトルのインジウム3d軌道起因のピーク位置よりも高エネルギー側にシフトしているTFTが開示されている。 Patent Document 11 discloses a gate electrode on an insulating substrate, a gate insulating film on the gate electrode, an oxide semiconductor film containing indium on the gate insulating film, and a source / drain on the oxide semiconductor film. The XPS spectrum in the oxide semiconductor region where the peak position due to the indium 3d orbit of the XPS spectrum in the surface layer of the oxide semiconductor film where the source / drain electrodes do not overlap is present in the lower part of the surface layer. A TFT that is shifted to a higher energy side than the peak position due to the indium 3d orbital is disclosed.

特開2011―4425号公報JP 2011-4425 A 特開2008―192721号公報JP 2008-192721 A 特開2013-105814号公報JP 2013-105814 A 特開2012-134472号公報JP 2012-134472 A 特開2011-129926号公報JP2011-129926A 特開2010-156994号公報JP 2010-156994 A 特開2013―70052号公報JP 2013-70052 A 特開2010―21520号公報JP 2010-21520 A 特開2013―138188号公報JP 2013-138188 A 特開2013―219336号公報JP 2013-219336 A 特開2013―41968号公報JP 2013-41968 A

APPLIED PHYSICS LETTERS 102, 102102(2013).APPLIED PHYSICS LETTERS 102, 102102 (2013).

 本願第1~第3発明は、このような事情に鑑みてなされたものであって、半導体層(チャネル層)に酸素欠損が導入されることで電子キャリアを生成できる第1金属酸化物に、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物を添加した複合金属酸化物を用いた薄膜トランジスタであって、特定の元素分布を有することで、光照射による特性劣化の抑制と、低コンタクト抵抗、及び優れたゲート制御性とを両立した薄膜トランジスタおよびその製造方法を提供することを目的とする。 The first to third inventions of the present application have been made in view of such circumstances, and the first metal oxide capable of generating electron carriers by introducing oxygen vacancies into the semiconductor layer (channel layer), A thin film transistor using a composite metal oxide to which a second oxide having a larger oxygen dissociation energy than that of the first metal oxide is added at least 200 kJ / mol and having a specific element distribution. An object of the present invention is to provide a thin film transistor and a method for manufacturing the same, which are compatible with suppression of characteristic deterioration due to light irradiation, low contact resistance, and excellent gate controllability.

 本願第4発明の課題は上記問題を、上述した先行特許出願で示した以外の組成条件で解決する薄膜トランジスタ及びその製造方法を提供することにある。 The subject of the 4th invention of this application is providing the thin-film transistor which solves the said problem on composition conditions other than having shown by the prior patent application mentioned above, and its manufacturing method.

 他方、有機ELディスプレイや液晶ディスプレイには発光層が使用されている。とりわけ、一番エネルギーの高い、すなわち短波長で発光する青色発光層からの発光は、450nmにピークがあり、短波長側に420nmまで発光スペクトルの裾が伸びている。そのため、有機ELディスプレイや液晶ディスプレイを構成する薄膜トランジスタは、この発光層からの光照射を受けることになるため、その特性として、上記波長を有する光照射に対して劣化しにくいという高い信頼性が望まれている。ここで、発光層からの光照射に対して劣化しにくいということは、具体的には、薄膜トランジスタを構成する酸化物半導体が、発光層からの発光(具体的には、420nm~600nmの波長を有する光照射)で誘発される「しきい値電圧のシフト」(ここで、「しきい値電圧のシフト」とは、発光層からの発光によってしきい値電圧が負側にシフトする現象を言う。)を抑制できるという特性を有することを意味する。そのため、信頼性の高い薄膜トランジスタを提供するために、この「しきい値電圧のシフト」を十分に抑制できる酸化物半導体が望まれている。 On the other hand, a light emitting layer is used for an organic EL display or a liquid crystal display. In particular, light emission from the blue light emitting layer having the highest energy, that is, light emitted at a short wavelength has a peak at 450 nm, and the bottom of the emission spectrum extends to 420 nm on the short wavelength side. For this reason, since the thin film transistors constituting the organic EL display and the liquid crystal display are irradiated with light from the light emitting layer, it is desired that the thin film transistor be highly resistant to deterioration with respect to light irradiation having the above wavelength. It is rare. Here, it is difficult to deteriorate against light irradiation from the light emitting layer. Specifically, the oxide semiconductor constituting the thin film transistor emits light from the light emitting layer (specifically, a wavelength of 420 nm to 600 nm). “Threshold voltage shift” induced by light irradiation (where “threshold voltage shift” refers to a phenomenon in which the threshold voltage shifts to the negative side due to light emission from the light emitting layer). .) Can be suppressed. Therefore, in order to provide a highly reliable thin film transistor, an oxide semiconductor that can sufficiently suppress this “threshold voltage shift” is desired.

 しかしながら、上記特許文献に開示されているいずれの酸化物半導体膜も、発光層からの発光で誘発される「しきい値電圧のシフト」を十分に抑制できるものではないという課題がある。 However, any of the oxide semiconductor films disclosed in the above-mentioned patent documents has a problem that the “threshold voltage shift” induced by light emission from the light emitting layer cannot be sufficiently suppressed.

 そこで、有機ELディスプレイや液晶ディスプレイを構成する薄膜トランジスタに用いられる酸化物半導体として、発光層からの発光で誘発される「しきい値電圧のシフト」を十分に抑制できるものが望まれている。 Therefore, an oxide semiconductor used for a thin film transistor constituting an organic EL display or a liquid crystal display is desired to be able to sufficiently suppress a “threshold voltage shift” induced by light emission from a light emitting layer.

 本願第5発明は、このような事情に鑑みてなされたものであって、発光層からの発光で誘発される「しきい値電圧のシフト」が十分に抑制できる酸化物半導体及びその製法、並びにそれを用いる薄膜トランジスタおよび半導体装置を提供することを目的とする。 The fifth invention of the present application was made in view of such circumstances, and an oxide semiconductor capable of sufficiently suppressing a “threshold voltage shift” induced by light emission from the light emitting layer, a manufacturing method thereof, and It is an object to provide a thin film transistor and a semiconductor device using the thin film transistor.

 なお、本明細書中における半導体装置とは、半導体から作られるトランジスタを利用する装置全般を含む。そのため、例えば、有機ELディスプレイや液晶ディスプレイもこの中に含まれる。 Note that the semiconductor device in this specification includes all devices using a transistor made of a semiconductor. Therefore, for example, an organic EL display and a liquid crystal display are also included in this.

 本発明者は鋭意検討の結果、上記第2酸化物(XOx)を構成する元素Xのうち、ケイ素、タンタル、ジルコニウム、ハフニウム、アルミニウム、イットリウム及び希土類元素からなる群より選ばれる少なくとも一種の元素Xの濃度が、前記半導体層の厚み方向の中央部において極大値を示す薄膜トランジスタが、上記課題を解決することを見出し、本願第1~第3発明に至った。
 すなわち本願第1発明は、
[1]ソース電極およびドレイン電極と、
 前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、
 前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、
 前記ゲート電極と前記半導体層との間に設けられた絶縁体層と
を有する薄膜トランジスタであって、
 前記半導体層が、酸素欠損が導入されることで電子キャリアを生成できる第1金属酸化物に、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物(XOx)を添加した複合金属酸化物で形成され、
 前記第2酸化物を構成する元素Xのうち、ケイ素、タンタル、ジルコニウム、ハフニウム、アルミニウム、イットリウム及び希土類元素からなる群より選ばれる少なくとも一種の元素Xの濃度が、前記半導体層の厚み方向の中央部において極大値を示す、上記薄膜トランジスタに関する。
As a result of intensive studies, the present inventor has at least one element X selected from the group consisting of silicon, tantalum, zirconium, hafnium, aluminum, yttrium and rare earth elements among the elements X constituting the second oxide (XOx). It has been found that a thin film transistor in which the concentration of 1 exhibits a maximum value in the central portion in the thickness direction of the semiconductor layer solves the above problems, and has led to the first to third inventions of the present application.
That is, the first invention of the present application is
[1] a source electrode and a drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
A thin film transistor having an insulator layer provided between the gate electrode and the semiconductor layer,
The semiconductor layer has a second metal oxide that can generate electron carriers by introducing oxygen vacancies, and the second energy of oxygen is 200 kJ / mol or more higher than that of the first metal oxide. Formed of a complex metal oxide to which an oxide (XOx) is added,
Among the elements X constituting the second oxide, the concentration of at least one element X 1 selected from the group consisting of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements is in the thickness direction of the semiconductor layer. The present invention relates to the above-described thin film transistor, which exhibits a maximum value at the center.

 また、下記[2]は、本願第1発明の好ましい一実施形態である
[2]前記元素Xの濃度が、前記半導体層の厚み方向の中央部において最大値を示す、上記[1]に記載の薄膜トランジスタ。
The following [2] is a preferred embodiment of the first invention of the present application. [2] In the above [1], the concentration of the element X 1 shows a maximum value in the central portion in the thickness direction of the semiconductor layer. The thin film transistor described.

 本願第2発明は、
[3]ソース電極およびドレイン電極と、
 前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、
 前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、
 前記ゲート電極と前記半導体層との間に設けられた絶縁体層と
を有する薄膜トランジスタであって、
 前記半導体層が、酸素欠損が導入されることで電子キャリアを生成できる第1金属酸化物に、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物(XOx)を添加した複合金属酸化物で形成され、
 前記第2酸化物を構成する元素Xのうち、ケイ素、タンタル、ジルコニウム、ハフニウム、アルミニウム、イットリウム及び希土類元素のいずれにも該当しない少なくとも一種の元素Xの濃度が、前記半導体層の厚み方向の中央部において極小値を示す、上記薄膜トランジスタに関する。
The second invention of the present application is
[3] a source electrode and a drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
A thin film transistor having an insulator layer provided between the gate electrode and the semiconductor layer,
The semiconductor layer has a second metal oxide that can generate electron carriers by introducing oxygen vacancies, and the second energy of oxygen is 200 kJ / mol or more higher than that of the first metal oxide. Formed of a complex metal oxide to which an oxide (XOx) is added,
Among the elements X constituting the second oxide, the concentration of at least one element X 2 that does not correspond to any of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements is in the thickness direction of the semiconductor layer. The present invention relates to the above-described thin film transistor that exhibits a minimum value in the center.

 また、下記[4]は、本願第2発明の好ましい一実施形態である
[4]前記元素Xの濃度が、前記半導体層の厚み方向の中央部において最小値を示す、上記[3]に記載の薄膜トランジスタ。
 本願第3発明は、
[5]ソース電極およびドレイン電極と、
 前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、
 前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、
 前記ゲート電極と前記半導体層との間に設けられた絶縁体層と
を有する薄膜トランジスタであって、
 前記半導体層が、酸素欠損が導入されることで電子キャリアを生成できる第1金属酸化物に、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物(XOx)を添加した複合金属酸化物で形成され、
 前記半導体層が、更に窒素を含有し、窒素の濃度が、前記半導体層の厚み方向の中央部において極大値を示す、上記薄膜トランジスタに関する。
 また、下記[6]から[17]は、それぞれ本願第1~第3発明の好ましい一実施形態である
[6]
 前記第2酸化物の酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも255kJ/mol以上大きい、上記[1]から[5]のいずれか一項に記載の薄膜トランジスタ。
[7]
 前記第1金属酸化物は、インジウム、ガリウム、亜鉛、および錫からなる群から選択された少なくとも一つの金属の酸化物である、上記[1]から[5]のいずれか一項に記載の薄膜トランジスタ。
[8]
 前記第2酸化物は、ジルコニウム(Zr)、およびプラセオジム(Pr)からなる群から選択された少なくとも一つの金属の酸化物である、上記[1]から[5]のいずれか一項に記載の薄膜トランジスタ。
[9]
 前記第2酸化物は、ケイ素(Si)、タンタル(Ta)、ランタン(La)、およびハフニウム(Hf)からなる群から選択された少なくとも一つの酸化物である、上記[6]に記載の薄膜トランジスタ。
[10]
 前記半導体層における前記第2酸化物の含有量が0より大きく50重量%以下である、上記[1]から[9]の何れかに記載の薄膜トランジスタ。
[11]
 前記半導体層における前記第2酸化物の含有量が0より大きく5重量%以下である、上記[1]から[10]の何れかに記載の薄膜トランジスタ。
[12]
 前記半導体層が非晶質である、上記[1]から[11]の何れかに記載の薄膜トランジスタ。
[13]
 前記半導体層の厚さが5nm以上かつ20nm以下の範囲である、上記[1]から[12]の何れかに記載の薄膜トランジスタ。
[14]
 前記第2酸化物が、ボロン(B)および炭素(C)からなる群から選択された少なくとも一つの元素の酸化物である、上記[1]から[5]のいずれか1項に記載の薄膜トランジスタ。
[15]
 前記半導体層中のボロン(B)および炭素(C)の含有量が0より大きく10重量%以下である、上記[14]に記載の薄膜トランジスタ。
[16]
 前記半導体層が10℃以上400℃以下の温度で形成される、
上記[1]から[15]の何れか1項に記載の薄膜トランジスタの製造方法。
[17]
 前記半導体層が10℃以上200℃以下の温度で形成される、上記[16]に記載の薄膜トランジスタの製造方法。
[18]
 上記[1]から[15]のいずれか1項に記載の薄膜トランジスタを有する装置。
[19]
 液晶ディスプレイ又は有機ELディスプレイである、上記[18]に記載の装置。
The following [4] is a preferred embodiment of the second invention of the present application [4] In the above [3], the concentration of the element X 2 shows a minimum value in the central portion in the thickness direction of the semiconductor layer. The thin film transistor described.
The third invention of the present application is
[5] a source electrode and a drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
A thin film transistor having an insulator layer provided between the gate electrode and the semiconductor layer,
The semiconductor layer has a second metal oxide that can generate electron carriers by introducing oxygen vacancies, and the second energy of oxygen is 200 kJ / mol or more higher than that of the first metal oxide. Formed of a complex metal oxide to which an oxide (XOx) is added,
The said thin film transistor is related with the said thin-film transistor in which the said semiconductor layer contains nitrogen further, and the density | concentration of nitrogen shows the maximum value in the center part of the thickness direction of the said semiconductor layer.
[6] to [17] are preferred embodiments of the first to third inventions of the present application [6].
The thin film transistor according to any one of [1] to [5], wherein the oxygen separation energy of the second oxide is greater than or equal to 255 kJ / mol than the oxygen separation energy of the first metal oxide.
[7]
The thin film transistor according to any one of [1] to [5], wherein the first metal oxide is an oxide of at least one metal selected from the group consisting of indium, gallium, zinc, and tin. .
[8]
The second oxide according to any one of [1] to [5], wherein the second oxide is an oxide of at least one metal selected from the group consisting of zirconium (Zr) and praseodymium (Pr). Thin film transistor.
[9]
The thin film transistor according to [6], wherein the second oxide is at least one oxide selected from the group consisting of silicon (Si), tantalum (Ta), lanthanum (La), and hafnium (Hf). .
[10]
The thin film transistor according to any one of [1] to [9], wherein the content of the second oxide in the semiconductor layer is greater than 0 and equal to or less than 50% by weight.
[11]
The thin film transistor according to any one of [1] to [10], wherein the content of the second oxide in the semiconductor layer is greater than 0 and 5% by weight or less.
[12]
The thin film transistor according to any one of [1] to [11], wherein the semiconductor layer is amorphous.
[13]
The thin film transistor according to any one of [1] to [12], wherein the thickness of the semiconductor layer is in the range of 5 nm to 20 nm.
[14]
The thin film transistor according to any one of [1] to [5], wherein the second oxide is an oxide of at least one element selected from the group consisting of boron (B) and carbon (C). .
[15]
The thin film transistor according to the above [14], wherein the content of boron (B) and carbon (C) in the semiconductor layer is greater than 0 and 10% by weight or less.
[16]
The semiconductor layer is formed at a temperature of 10 ° C. or higher and 400 ° C. or lower;
The method for producing a thin film transistor according to any one of [1] to [15] above.
[17]
The method for producing a thin film transistor according to [16], wherein the semiconductor layer is formed at a temperature of 10 ° C. or higher and 200 ° C. or lower.
[18]
The apparatus which has a thin-film transistor of any one of said [1] to [15].
[19]
The device according to [18], which is a liquid crystal display or an organic EL display.

[20]
 更に、本願第4発明の一側面によれば、ソース電極およびドレイン電極と、前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、前記ゲート電極と前記半導体層との間に設けられた絶縁体層とを設け、前記半導体層が、酸化錫に、酸素のかい離エネルギーが酸化錫より大きくかつ酸化錫の酸素のかい離エネルギーとの差が200kJ/mol未満である金属酸化物を添加した複合金属酸化物である薄膜トランジスタが与えられる。
[21]
 ここで、前記半導体層は、酸素の解離エネルギーが酸化錫よりも小さい追加の酸化物を前記金属酸化物よりも少ない量だけ含んでよい。
[22]
 また、前記半導体層中の前記追加の酸化物の含有量が20重量%以下であってよい。
[23]
 また、前記半導体層中の前記追加の酸化物の含有量が4重量%以下であってよい。
[24]
 また、前記半導体層が非晶質であってよい。
[25]
 また、前記半導体層の厚さが5nm以上かつ20nm以下であってよい。
[26]
 また、前記追加の酸化物は、鉛、パラジウム、白金、硫黄、アンチモン、ストロンチウム、タリウム、イッテルビウムからなる群から選択された少なくとも一の酸化物であってよい。
[27]
 また、前記金属酸化物はサマリウム、タングステン、ネオジウム、ガドリニウムからなる群から選択された少なくとも一の酸化物であってよい。
[28]
 また、前記半導体層中の前記金属酸化物の含有量が0より大きく50重量%以下であってよい。
[29]
 また、前記前記半導体層中の前記金属酸化物の含有量が5重量%以下であってよい。
[30]
 本願第4発明の他の側面によれば、前記半導体層を10℃以上500℃以下で形成する、上記何れかの薄膜トランジスタの製造方法が与えられる。
[31]
 ここで、前記半導体層を10℃以上300℃以下で形成してよい。
[20]
Furthermore, according to one aspect of the present invention, a source electrode and a drain electrode, a semiconductor layer provided in contact with the source electrode and the drain electrode, and a channel between the source electrode and the drain electrode are supported. And an insulating layer provided between the gate electrode and the semiconductor layer. The semiconductor layer has tin oxide, an oxygen separation energy larger than that of tin oxide, and an oxide layer. A thin film transistor which is a composite metal oxide to which a metal oxide having a difference from the separation energy of oxygen of tin of less than 200 kJ / mol is added is provided.
[21]
Here, the semiconductor layer may include an additional oxide whose oxygen dissociation energy is smaller than that of tin oxide in an amount smaller than that of the metal oxide.
[22]
The content of the additional oxide in the semiconductor layer may be 20% by weight or less.
[23]
The content of the additional oxide in the semiconductor layer may be 4% by weight or less.
[24]
The semiconductor layer may be amorphous.
[25]
The semiconductor layer may have a thickness of 5 nm to 20 nm.
[26]
The additional oxide may be at least one oxide selected from the group consisting of lead, palladium, platinum, sulfur, antimony, strontium, thallium, and ytterbium.
[27]
The metal oxide may be at least one oxide selected from the group consisting of samarium, tungsten, neodymium, and gadolinium.
[28]
The content of the metal oxide in the semiconductor layer may be greater than 0 and 50% by weight or less.
[29]
Further, the content of the metal oxide in the semiconductor layer may be 5% by weight or less.
[30]
According to another aspect of the fourth invention of the present application, there is provided a method for producing any one of the above thin film transistors, wherein the semiconductor layer is formed at 10 ° C. or more and 500 ° C. or less.
[31]
Here, you may form the said semiconductor layer at 10 degreeC or more and 300 degrees C or less.

 また、上記課題を解決すべく鋭意検討した結果、本発明者は、酸素欠損が導入されることにより電子キャリアを生成できる金属酸化物からなる第1金属酸化物と、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物とを含んでなる、酸素欠損が導入された酸化物半導体を形成し、更にその酸素欠損部分に置換基として、OH基、H基、F基、Cl基、又はB基からなる群から選択される少なくとも1つを導入して前記第1金属酸化物の金属と結合させた前記酸化物半導体を薄膜トランジスタとして用いると、発光層からの発光で誘発される「しきい値電圧のシフト」が十分に抑制可能であることを初めて見出した。 In addition, as a result of intensive studies to solve the above problems, the present inventor has found that the first metal oxide made of a metal oxide capable of generating electron carriers by introducing oxygen vacancies and the oxygen separation energy are the first. An oxide semiconductor into which oxygen vacancies are introduced is formed, which includes a second oxide that is 200 kJ / mol or more larger than the oxygen separation energy of one metal oxide, and further has OH as a substituent in the oxygen vacancies. When the oxide semiconductor in which at least one selected from the group consisting of a group, an H group, an F group, a Cl group, or a B group is introduced and bonded to the metal of the first metal oxide is used as a thin film transistor, It has been found for the first time that the “threshold voltage shift” induced by light emission from the light emitting layer can be sufficiently suppressed.

 すなわち、本願第5発明は、以下の[32]~[57]に示される構成を有する。 That is, the fifth invention of the present application has a configuration shown in the following [32] to [57].

[32] 酸素欠損が導入されることにより電子キャリアを生成できる金属酸化物からなる第1金属酸化物と、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物とを含んでなる酸化物半導体であって、前記第1金属酸化物の金属が、OH基、H基、F基、Cl基、又はB基からなる群から選択される少なくとも1つとの結合を有する、前記酸化物半導体。
[33] 前記第2酸化物の酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも255kJ/mol以上大きい、[32]に記載の酸化物半導体。
[34] 前記第1金属酸化物の金属が、インジウム、ガリウム、亜鉛、および錫からなる群から選択される少なくとも一つである、[32]に記載の酸化物半導体。
[35] 前記第2酸化物は、ケイ素(Si)、チタン(Ti)、タングステン(W)、タンタル(Ta)、ランタン(La)、ハフニウム(Hf)、ジルコニウム(Zr)、およびプラセオジム(Pr)からなる群から選択される少なくとも一つを含む酸化物である、[32]から[34]のいずれか一項に記載の酸化物半導体。
[36] 前記第2酸化物は、ケイ素(Si)、チタン(Ti)、タングステン(W)、タンタル(Ta)、ランタン(La)、およびハフニウム(Hf)からなる群から選択された少なくとも一つを含む酸化物である、[35]に記載の酸化物半導体。
[37] 前記第2酸化物の含有量が0より大きく50重量%以下である、[32]から[36]のいずれかに記載の酸化物半導体。
[38] 前記第2酸化物の含有量が0より大きく5重量%以下である、[37]に記載の酸化物半導体。
[39] 酸化物半導体の厚さが5nm以上かつ20nm以下の範囲である、[32]から[38]のいずれかに記載の酸化物半導体。
[40] 前記第2酸化物が、炭素(C)を含む酸化物である、[32]から[39]のいずれかに記載の酸化物半導体。
[41] 炭素(C)の含有量が0より大きく10重量%以下である、[40]に記載の酸化物半導体。
[42] 前記第1金属酸化物の金属がインジウムであって、前記第2酸化物の酸素のかい離エネルギーが725kJ/mol以上である、[32]に記載の酸化物半導体。
[43] 前記第1金属酸化物の金属がOH基との結合を有している、[32]から[42]のいずれかに記載の酸化物半導体。
[44] 前記OH基の含有量が0.1%以上10%以下である、[43]に記載の酸化物半導体。
[45] 前記第1金属酸化物の金属がH基との結合を有する、[32]から[42]のいずれかに記載の酸化物半導体。
[46] 前記H基の含有量が0%よりも大きく0.1%以下である、[45]に記載の酸化物半導体。
[47] 前記第1金属酸化物の金属が、F基、Cl基、又はB基からなる群から選択される少なくとも1つとの結合を有する、[32]から[42]のいずれかにのいずれか一項に記載の酸化物半導体。
[48] 前記F基、Cl基、又はB基からなる群から選択される少なくとも1つの含有量が5×1018atoms/cm超1×1021atoms/cm以下である、[47]に記載の酸化物半導体。
[49] 酸化物半導体が非晶質である、[32]から[48]のいずれかに記載の酸化物半導体。
[50] [32]から[49]のいずれかに記載の酸化物半導体を含んでなる、薄膜トランジスタ。
[51] ソース電極およびドレイン電極と、
 前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、
 前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、
 前記ゲート電極と前記半導体層との間に設けられた絶縁体層と
を設け、
 前記半導体層が[32]から[49]のいずれかに記載の酸化物半導体で形成されている、薄膜トランジスタ。
[52] [51]に記載の薄膜トランジスタを含んでなる、半導体装置。
[53] 前記半導体層が10℃以上400℃以下で形成される、[32]から[49]のいずれかに記載の酸化物半導体の製造方法。
[54] 前記半導体層が10℃以上200℃以下で形成される、[32]から[49]のいずれかに記載の酸化物半導体の製造方法。
[55] 酸素欠損が導入されることにより電子キャリアを生成できる金属酸化物からなる第1金属酸化物の粉末と、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物の粉末との焼結体からなるターゲットと、希ガスと酸素からなる混合ガスであって水素原子を有する化合物を含まないプロセスガスとを用いた物理蒸着法により、前記第1金属酸化物と、前記第2酸化物とを含む酸化物半導体を形成する工程と、
 前記酸化物半導体を大気中、150℃で熱処理することにより酸素欠損を有する前記酸化物半導体を形成する工程と、
 前記酸素欠損を有する酸化物半導体を、HOガスを導入した80%以上の高湿度下、150~300℃の温度範囲で熱処理することにより、前記第1金属酸化物の金属とOH基との結合を形成する工程とを含む、[43]又は[44]に記載の酸化物半導体の製造方法。
[56] 酸素欠損が導入されることにより電子キャリアを生成できる金属酸化物からなる第1金属酸化物の粉末と、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物の粉末との焼結体からなるターゲットと、希ガスと酸素からなる混合ガスであって水素原子を有する化合物を含まないプロセスガスとを用いた物理蒸着法により、前記第1金属酸化物と、前記第2酸化物とを含む酸化物半導体を形成する工程と、
 前記酸化物半導体を大気中、150℃で熱処理することにより酸素欠損を有する前記酸化物半導体を形成する工程と、
 前記酸素欠損を有する酸化物半導体を、H雰囲気ガス下、300~400℃の温度範囲で熱処理することにより、前記第1金属酸化物の金属とH基との結合を形成する工程とを含む、[45]又は[46]に記載の酸化物半導体の製造方法。
[57] 酸素欠損が導入されることにより電子キャリアを生成できる金属酸化物からなる第1金属酸化物の粉末と、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物の粉末との焼結体からなるターゲットと、希ガスと酸素からなる混合ガスであって水素原子を有する化合物を含まないプロセスガスとを用いた物理蒸着法により、前記第1金属酸化物と、前記第2酸化物とを含む酸化物半導体を形成する工程と、
 前記酸化物半導体を大気中、150℃で熱処理することにより酸素欠損を有する前記酸化物半導体を形成する工程と、
 前記酸素欠損を有する酸化物半導体に、フッ素イオン、塩素イオン、又はホウ素イオンからなる群から選択される少なくとも1つをイオン注入することにより、前記第1金属酸化物の金属と、前記イオン注入された基との結合を形成する工程とを含む、[47]又は[48]に記載の酸化物半導体の製造方法。
[32] A first metal oxide made of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and an oxygen separation energy of 200 kJ / mol or more than the oxygen separation energy of the first metal oxide. An oxide semiconductor comprising a large second oxide, wherein the metal of the first metal oxide is at least selected from the group consisting of an OH group, an H group, an F group, a Cl group, or a B group The oxide semiconductor having a bond with one.
[33] The oxide semiconductor according to [32], wherein the oxygen separation energy of the second oxide is greater than or equal to 255 kJ / mol than the oxygen separation energy of the first metal oxide.
[34] The oxide semiconductor according to [32], wherein the metal of the first metal oxide is at least one selected from the group consisting of indium, gallium, zinc, and tin.
[35] The second oxide includes silicon (Si), titanium (Ti), tungsten (W), tantalum (Ta), lanthanum (La), hafnium (Hf), zirconium (Zr), and praseodymium (Pr). The oxide semiconductor according to any one of [32] to [34], which is an oxide containing at least one selected from the group consisting of:
[36] The second oxide is at least one selected from the group consisting of silicon (Si), titanium (Ti), tungsten (W), tantalum (Ta), lanthanum (La), and hafnium (Hf). [35] The oxide semiconductor according to [35].
[37] The oxide semiconductor according to any one of [32] to [36], wherein the content of the second oxide is greater than 0 and equal to or less than 50% by weight.
[38] The oxide semiconductor according to [37], wherein the content of the second oxide is greater than 0 and 5% by weight or less.
[39] The oxide semiconductor according to any one of [32] to [38], wherein the thickness of the oxide semiconductor is in the range of 5 nm to 20 nm.
[40] The oxide semiconductor according to any one of [32] to [39], wherein the second oxide is an oxide containing carbon (C).
[41] The oxide semiconductor according to [40], wherein the content of carbon (C) is greater than 0 and 10% by weight or less.
[42] The oxide semiconductor according to [32], wherein the metal of the first metal oxide is indium, and the oxygen separation energy of the second oxide is 725 kJ / mol or more.
[43] The oxide semiconductor according to any one of [32] to [42], wherein the metal of the first metal oxide has a bond with an OH group.
[44] The oxide semiconductor according to [43], wherein the content of the OH group is 0.1% or more and 10% or less.
[45] The oxide semiconductor according to any one of [32] to [42], wherein the metal of the first metal oxide has a bond with an H group.
[46] The oxide semiconductor according to [45], wherein the content of the H group is greater than 0% and 0.1% or less.
[47] Any of [32] to [42], wherein the metal of the first metal oxide has a bond with at least one selected from the group consisting of an F group, a Cl group, or a B group. The oxide semiconductor according to claim 1.
[48] The content of at least one selected from the group consisting of the F group, the Cl group, or the B group is more than 5 × 10 18 atoms / cm 3 and not more than 1 × 10 21 atoms / cm 3 [47] An oxide semiconductor according to 1.
[49] The oxide semiconductor according to any one of [32] to [48], wherein the oxide semiconductor is amorphous.
[50] A thin film transistor comprising the oxide semiconductor according to any one of [32] to [49].
[51] a source electrode and a drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
Providing an insulator layer provided between the gate electrode and the semiconductor layer;
A thin film transistor, wherein the semiconductor layer is formed of the oxide semiconductor according to any one of [32] to [49].
[52] A semiconductor device comprising the thin film transistor according to [51].
[53] The method for manufacturing an oxide semiconductor according to any one of [32] to [49], wherein the semiconductor layer is formed at 10 ° C. or higher and 400 ° C. or lower.
[54] The method for manufacturing an oxide semiconductor according to any one of [32] to [49], wherein the semiconductor layer is formed at 10 ° C. or higher and 200 ° C. or lower.
[55] The first metal oxide powder made of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and the oxygen separation energy of the first metal oxide is 200 kJ / day higher than the oxygen separation energy of the first metal oxide. By a physical vapor deposition method using a target composed of a sintered body of a second oxide powder larger than mol and a mixed gas composed of a rare gas and oxygen and not containing a compound having hydrogen atoms, Forming an oxide semiconductor including a first metal oxide and the second oxide;
Forming the oxide semiconductor having oxygen vacancies by heat-treating the oxide semiconductor at 150 ° C. in the atmosphere;
By heat-treating the oxide semiconductor having oxygen vacancies in a temperature range of 150 to 300 ° C. under a high humidity of 80% or more introduced with H 2 O gas, the metal of the first metal oxide, the OH group, and The method for producing an oxide semiconductor according to [43] or [44], including a step of forming a bond.
[56] The first metal oxide powder made of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and the oxygen separation energy of the first metal oxide is 200 kJ / day higher than the oxygen separation energy of the first metal oxide. By a physical vapor deposition method using a target composed of a sintered body of a second oxide powder larger than mol and a mixed gas composed of a rare gas and oxygen and not containing a compound having hydrogen atoms, Forming an oxide semiconductor including a first metal oxide and the second oxide;
Forming the oxide semiconductor having oxygen vacancies by heat-treating the oxide semiconductor at 150 ° C. in the atmosphere;
Forming a bond between the metal of the first metal oxide and an H group by heat-treating the oxide semiconductor having oxygen vacancies in a temperature range of 300 to 400 ° C. in an H 2 atmosphere gas. [45] or [46], The manufacturing method of the oxide semiconductor.
[57] The first metal oxide powder made of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and the oxygen separation energy of the first metal oxide is 200 kJ / day higher than the oxygen separation energy of the first metal oxide. By a physical vapor deposition method using a target composed of a sintered body of a second oxide powder larger than mol and a mixed gas composed of a rare gas and oxygen and not containing a compound having hydrogen atoms, Forming an oxide semiconductor including a first metal oxide and the second oxide;
Forming the oxide semiconductor having oxygen vacancies by heat-treating the oxide semiconductor at 150 ° C. in the atmosphere;
By ion-implanting at least one selected from the group consisting of fluorine ions, chlorine ions, or boron ions into the oxide semiconductor having oxygen vacancies, the ions of the metal of the first metal oxide are implanted. A method for forming an oxide semiconductor according to [47] or [48].

 本願第1~第3発明によれば、光照射によるしきい値電流のシフト等の特性劣化が抑制され、ソース電極及び/又はドレイン電極と半導体層との界面におけるコンタクト抵抗が低く、かつ電子移動度が高くゲート制御性に優れるという、実用上好ましい特性を高いレベルで兼ね備えた薄膜トランジスタ、およびその製造方法が実現される。 According to the first to third inventions of the present application, characteristic deterioration such as threshold current shift due to light irradiation is suppressed, contact resistance at the interface between the source electrode and / or drain electrode and the semiconductor layer is low, and electron transfer is suppressed. A thin film transistor having a high level of practically preferable characteristics of high degree and excellent gate controllability, and a method for manufacturing the same are realized.

 本願第4発明によれば、酸素欠陥が導入されることで電子キャリアを生成できる金属酸化物として酸素のかい離エネルギーが528kJ/molと大きな酸化錫を用いた場合、これに添加する金属酸化物が、当該添加する金属酸化物についての酸素のかい離エネルギーが酸化錫についての酸素のかい離エネルギーより大きく、かつ酸化錫についての酸素のかい離エネルギーとの差が200kJ/mol未満であるようにした複合金属酸化物の半導体層を用いることで、トランジスタ特性に優れた薄膜トランジスタを提供することができる。
 また、本願第4発明によれば、上記の添加する金属酸化物に加えて、酸素のかい離エネルギーが酸化錫より小さな酸化物を、上記添加される金属酸化物より少ない量だけ追加して添加した複合金属酸化物の半導体層を用いることで、トランジスタ特性に優れた薄膜トランジスタを提供することができる
According to the fourth aspect of the present invention, when a tin oxide having a large oxygen separation energy of 528 kJ / mol is used as a metal oxide capable of generating electron carriers by introducing oxygen defects, the metal oxide added thereto is In addition, the composite metal oxidation in which the oxygen separation energy of the added metal oxide is larger than the oxygen separation energy of tin oxide and the difference from the oxygen separation energy of tin oxide is less than 200 kJ / mol. A thin film transistor with excellent transistor characteristics can be provided by using a semiconductor layer.
According to the fourth invention of the present application, in addition to the metal oxide to be added, an oxide having an oxygen separation energy smaller than that of tin oxide is added in an amount smaller than that of the metal oxide to be added. By using a semiconductor layer of a composite metal oxide, a thin film transistor having excellent transistor characteristics can be provided.

 本願第5発明によれば、発光層からの発光で誘発される「しきい値電圧のシフト」が十分に抑制できる酸化物半導体を提供することができる。そのため、この酸化物半導体を用いた薄膜トランジスタやこの薄膜トランジスタを用いた有機ELディスプレイや液晶ディスプレイは、発光層からの発光に対して劣化しにくいという高い信頼性を得ることができる。 According to the fifth invention of the present application, it is possible to provide an oxide semiconductor capable of sufficiently suppressing “threshold voltage shift” induced by light emission from the light emitting layer. Therefore, a thin film transistor using the oxide semiconductor, an organic EL display using the thin film transistor, and a liquid crystal display can have high reliability that the light emission from the light emitting layer hardly deteriorates.

 因みに、特許文献9には、IZO系やIGZO系のような酸化物半導体膜上に接してソース電極層及びドレイン電極層を設けたトランジスタを有する半導体装置において、島状に加工された上記酸化物半導体膜の側面部の前記ソース電極層及び前記ドレイン電極層と重畳していない領域におけるフッ素、塩素、ボロンの濃度が開示されている。しかしながら、このフッ素、塩素、ボロンは、エッチングガスに含まれる不純物であって、これらの混入による寄生チャネルの形成を防止するために、溶液洗浄による不純物除去処理によって可能な限り除去されなければならないものである(例えば、段落0184や0185参照)。事実、これらの濃度は、フッ素と塩素で5×1018atoms/cm以下、ボロンで1×1016atoms/cm以下と極めて低いことが明示されている(例えば、段落0225参照)。そのため、特許文献9において、酸化物半導体膜を構成する金属が、このような極めて低い濃度のフッ素や塩素やボロンと結合しているとは認められない。よって、特許文献9に記載の酸化物半導体膜では、本願第5発明による上記効果は得られない。 Incidentally, Patent Document 9 discloses that the above oxide processed into an island shape in a semiconductor device having a transistor in which a source electrode layer and a drain electrode layer are provided in contact with an oxide semiconductor film such as an IZO or IGZO system. The concentration of fluorine, chlorine, and boron in a region not overlapping with the source electrode layer and the drain electrode layer on the side surface portion of the semiconductor film is disclosed. However, this fluorine, chlorine, and boron are impurities contained in the etching gas, and must be removed as much as possible by the impurity removal treatment by solution cleaning in order to prevent the formation of parasitic channels due to their contamination. (See paragraphs 0184 and 0185, for example). In fact, these concentrations are clearly shown to be very low, 5 × 10 18 atoms / cm 3 or less for fluorine and chlorine and 1 × 10 16 atoms / cm 3 or less for boron (see, for example, paragraph 0225). Therefore, in Patent Document 9, it is not recognized that the metal constituting the oxide semiconductor film is bonded to such an extremely low concentration of fluorine, chlorine, or boron. Therefore, in the oxide semiconductor film described in Patent Document 9, the above effect according to the fifth invention of the present application cannot be obtained.

 特許文献10には、酸化物半導体を用いた半導体装置の作製方法において、ホウ素や希ガス元素等から選ばれた一種以上の元素をドーパントとして用いることが開示されている。しかしながら、この特許文献には、ドーパントの量に関する記載がない。ここで、このドーパントがソース電極とドレイン電極と接する酸化物半導体の抵抗を低下させるためだけに注入されるものであることを考慮すれば、このドーパントの量は非常に小さく、5×1018atoms/cmを超えることはないと推認される。そのため、特許文献10においても、酸化物半導体膜を構成する金属が、このような極めて低い濃度のホウ素や希ガス元素と結合しているとは認められない。
 加えて、特許文献10に記載された酸化物半導体の構成では(例えば、段落0149参照)、ゲート電極でマスクされた部分に位置する酸化物半導体膜の領域にはホウ素や希ガス元素は含まれていない。つまり、特許文献10では、ゲート電極でマスクされた部分に位置する酸化物半導体膜の領域(即ち、チャネル領域)においては、その酸化物半導体膜を構成する金属が、ドーパントとして用いられているホウ素や希ガス元素とは結合しない。
 このような相違により、特許文献10に記載の酸化物半導体膜では、本願第5発明による上記効果は得られない。
Patent Document 10 discloses that in a method for manufacturing a semiconductor device using an oxide semiconductor, one or more elements selected from boron, a rare gas element, and the like are used as a dopant. However, this patent document does not describe the amount of dopant. Here, considering that this dopant is implanted only to reduce the resistance of the oxide semiconductor in contact with the source electrode and the drain electrode, the amount of this dopant is very small, 5 × 10 18 atoms. / Cm 3 is presumed not to exceed. Therefore, even in Patent Document 10, it is not recognized that the metal constituting the oxide semiconductor film is bonded to such an extremely low concentration of boron or a rare gas element.
In addition, in the structure of the oxide semiconductor described in Patent Document 10 (see, for example, paragraph 0149), a region of the oxide semiconductor film located in a portion masked with the gate electrode contains boron or a rare gas element. Not. That is, in Patent Document 10, in a region of an oxide semiconductor film (that is, a channel region) located in a portion masked with a gate electrode, a metal that forms the oxide semiconductor film is boron used as a dopant. It does not combine with noble gas elements.
Due to such differences, the oxide semiconductor film described in Patent Document 10 cannot obtain the above-described effect of the fifth invention of the present application.

 また、特許文献11には、酸化物半導体膜のソース・ドレイン電極が重ならない部分に該酸化物半導体膜とは異なる別層として表面層を作製し、その表面層にだけインジウムとフッ素との化学結合を設けるTFTが開示されている。つまり、特許文献11に記載のTFTは、表面層とは異なる別層としてその表面層の下部に存在している酸化物半導体膜にフッ素を導入するものではない。これに対して、本願第5発明においては、酸化物半導体膜のうちの主にゲート電極側の領域がチャネル領域として機能する。従って、本願第5発明では酸化物半導体膜中の少なくともゲート電極との界面領域にドーパントが存在する(もちろん他の領域にもドーパントが存在してよい)。よって、特許文献11に記載の酸化物半導体膜では、本願第5発明による上記効果は得られない。 In Patent Document 11, a surface layer is formed as a separate layer different from the oxide semiconductor film in a portion where the source / drain electrodes of the oxide semiconductor film do not overlap with each other, and chemicals of indium and fluorine are formed only on the surface layer. A TFT providing a bond is disclosed. In other words, the TFT described in Patent Document 11 does not introduce fluorine into the oxide semiconductor film existing under the surface layer as a separate layer different from the surface layer. On the other hand, in the fifth invention of the present application, a region mainly on the gate electrode side of the oxide semiconductor film functions as a channel region. Therefore, in the fifth invention of the present application, the dopant exists in at least the interface region with the gate electrode in the oxide semiconductor film (of course, the dopant may also exist in other regions). Therefore, in the oxide semiconductor film described in Patent Document 11, the above effect according to the fifth invention of the present application cannot be obtained.

本願第1発明の一実施形態に係る薄膜トランジスタの概略断面図。1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the first invention of the present application. 本願第1発明の一実施例の薄膜トランジスタの概略断面図。1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the first invention of the present application. In-Si-O膜の組成とバンドギャップとの関係を示す図。FIG. 6 shows a relationship between the composition of an In—Si—O film and a band gap. 本願第1発明の一実施例の元素濃度分布を示す図。The figure which shows element concentration distribution of one Example of this-application 1st invention. 本願第3発明の一実施例の元素濃度分布を示す図。The figure which shows element concentration distribution of one Example of this-application 3rd invention. 本願第1発明の一実施例の電子移動度及びしきい値電圧のシフトを示す図。The figure which shows the shift of the electron mobility and threshold voltage of one Example of this-application 1st invention. 本願第3発明の一実施例のId-Vg特性を示す図The figure which shows the Id-Vg characteristic of one Example of this-application 3rd invention. 本願第4発明の第1の実施形態に係る薄膜トランジスタの概略断面図。The schematic sectional drawing of the thin-film transistor which concerns on 1st Embodiment of this-application 4th invention. 本願第4発明の第2の実施形態に係るもう一つの薄膜トランジスタの概略断面図。The schematic sectional drawing of another thin-film transistor which concerns on 2nd Embodiment of this-application 4th invention. 本願第4発明の実施例の薄膜トランジスタの概略断面図。The schematic sectional drawing of the thin-film transistor of the Example of this-application 4th invention. 本願第4発明の第1の実施例(実施例B1)の薄膜トランジスタのId-Vg特性を示す図。The figure which shows the Id-Vg characteristic of the thin-film transistor of 1st Example (Example B1) of this-application 4th invention. 本願第4発明の第1の実施例(実施例B1)の2種類の半導体材料のスパッタリング成膜のO/(O+Ar)比と導電性の関係を示す図。Shows a first embodiment the two O 2 / (O 2 + Ar ) ratio and conductive relationship sputtering semiconductor material (Example B1) of the present fourth invention. 本願第4発明の第2の実施例(実施例B2)で使用する半導体膜が非晶質であることを確認するためのX線回折パターンを示す図。The figure which shows the X-ray-diffraction pattern for confirming that the semiconductor film used by 2nd Example (Example B2) of this invention 4th invention is amorphous. 本願第4発明の第2の実施例(実施例B2)の薄膜トランジスタのId-Vd特性を示す図。The figure which shows the Id-Vd characteristic of the thin-film transistor of 2nd Example (Example B2) of this-application 4th invention. 本願第5発明の一実施形態である薄膜トランジスタの概略断面図。The schematic sectional drawing of the thin-film transistor which is one Embodiment of this-application 5th invention. 本願第5発明の実施例(実施例C)の薄膜トランジスタの概略断面図。The schematic sectional drawing of the thin-film transistor of the Example (Example C) of this-application 5th invention. 実施例CのIn-Si-O半導体と、In-OH結合を有するIn-Si-O半導体((a) In-Si-O半導体のIn3dXPSスペクトル、(b) In-OH結合を有するIn-Si-O半導体のIn3dXPSスペクトル)。In-Si-O semiconductor of Example C and In-Si-O semiconductor having In-OH bond ((a) In3dXPS spectrum of In-Si-O semiconductor, (b) In-Si having In-OH bond) -In3dXPS spectrum of -O semiconductor). 420nm~600nmの波長の光照射前後のIn-OH結合の有無によるIn-Si-O半導体のI-V特性の比較結果を示す図((a) 光照射前のIn-Si-O半導体と光照射前のIn-OH結合を有するIn-Si-O半導体のI-V特性、(b) 光照射後のIn-OH結合を有するIn-Si-O半導体のI-V特性、(c) 光照射後のIn-Si-O半導体のI-V特性)。Shows the comparison results of the I d -V g characteristics of the In-Si-O semiconductor with or without an In-OH bonds before and after light irradiation of a wavelength of 420nm ~ 600nm ((a) before irradiation In-Si-O semiconductor and the I d -V g characteristics of the in-Si-O semiconductor having an in-OH bonds before the light irradiation, the in-Si-O semiconductor having an in-OH bond after (b) irradiation I d -V g Characteristics, (c) I d -V g characteristics of In—Si—O semiconductor after light irradiation).

 以下、図を参照しながら、本願第1~第3発明の実施形態に係る薄膜トランジスタおよび薄膜トランジスタの製造方法について説明する。なお、以下の全ての図面においては、図面を見やすくするため、各構成要素の寸法や比率などは適宜異ならせてあり、実寸やその比率とは必ずしも一致しない。 Hereinafter, a thin film transistor and a method of manufacturing the thin film transistor according to embodiments of the first to third inventions of the present application will be described with reference to the drawings. In all the following drawings, in order to make the drawings easy to see, the dimensions and ratios of the constituent elements are appropriately changed, and the actual dimensions and the ratios do not necessarily match.

 本願第1発明の薄膜トランジスタは、
 ソース電極およびドレイン電極と、
 前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、
 前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、
 前記ゲート電極と前記半導体層との間に設けられた絶縁体層と
を有する薄膜トランジスタであって、
 前記半導体層が、酸素欠損が導入されることで電子キャリアを生成できる第1金属酸化物に、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物(XOx)を添加した複合金属酸化物で形成され、
 前記第2酸化物を構成する元素Xのうち、ケイ素、タンタル、ジルコニウム、ハフニウム、アルミニウム、イットリウム及び希土類元素からなる群より選ばれる少なくとも一種の元素Xの濃度が、前記半導体層の厚み方向の中央部において極大値を示す、上記薄膜トランジスタである。
 ここで、上記特定の元素Xの濃度は、上記半導体層の厚み方向において連続的にかつ実質的に変動しており、すなわち上記元素Xは、半導体層の厚み方向に濃度勾配を有している。より具体的には、元素Xの濃度は、半導体層の厚み方向の中央部において極大値、すなわち少なくとも1のピークを示す。ここで、「中央部」とは、上記半導体層の両界面(通常は、ソース電極及びドレイン電極側の層間絶縁膜と接する界面、及びゲート電極側の絶縁体層と接する界面)のいずれからも、2nm以上、又は半導体層の厚みの5%以上離れている箇所をいう。
The thin film transistor of the first invention of this application is:
A source electrode and a drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
A thin film transistor having an insulator layer provided between the gate electrode and the semiconductor layer,
The semiconductor layer has a second metal oxide that can generate electron carriers by introducing oxygen vacancies, and the second energy of oxygen is 200 kJ / mol or more higher than that of the first metal oxide. Formed of a complex metal oxide to which an oxide (XOx) is added,
Among the elements X constituting the second oxide, the concentration of at least one element X 1 selected from the group consisting of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements is in the thickness direction of the semiconductor layer. The thin film transistor having a maximum value in the center.
Here, the concentration of the specific element X 1 is in the thickness direction of the semiconductor layer is continuously and substantially change, that is, the element X 1 is a concentration gradient in the thickness direction of the semiconductor layer ing. More specifically, the concentration of the element X 1 shows a maximum value, that is, at least one peak in the central portion in the thickness direction of the semiconductor layer. Here, the “central portion” refers to both the interfaces of the semiconductor layer (usually, the interface in contact with the interlayer insulating film on the source electrode and drain electrode side and the interface in contact with the insulator layer on the gate electrode side). It refers to a location 2 nm or more, or 5% or more of the thickness of the semiconductor layer.

 好ましくは、上記少なくとも一種の元素Xの濃度は、前記半導体層の厚み方向の中央部において最大値を示す。すなわち、半導体層の厚み方向の中央部のいずれかの場所における元素Xの濃度は、半導体層のいずれの箇所における元素Xの濃度よりも高いことが好ましい。 Preferably, the at least one concentration of the element X 1 represents the maximum value in the central portion in the thickness direction of the semiconductor layer. That is, the concentration of the element X 1 in any location of the central portion in the thickness direction of the semiconductor layer is preferably higher than the concentration of the element X 1 in any position of the semiconductor layer.

 本願第1発明においては、元素Xの濃度が、前記半導体層の厚み方向の中央部において極大値を示すことにより、光照射によるしきい値電流のシフト等の特性劣化が抑制され、ソース電極及び/又はドレイン電極と半導体層との界面におけるコンタクト抵抗が低く、かつ電子移動度が高くゲート制御性に優れるという、顕著な技術的効果が実現される。 In the first invention, the concentration of the element X 1 is, by indicating a maximum value in the central portion in the thickness direction of the semiconductor layer, characteristic deterioration such as a shift in the threshold current due to light irradiation can be suppressed, the source electrode And / or a remarkable technical effect that the contact resistance at the interface between the drain electrode and the semiconductor layer is low, the electron mobility is high, and the gate controllability is excellent is realized.

 本願第1発明の薄膜トランジスタは、半導体層を10℃以上400℃以下で形成する工程を有する製造方法によって製造することが好ましい。 The thin film transistor of the first invention of the present application is preferably manufactured by a manufacturing method including a step of forming a semiconductor layer at 10 ° C. or higher and 400 ° C. or lower.

 図1は本願第1発明の好ましい一実施形態に係る薄膜トランジスタ10の概略断面図である。基板20は、公知の形成材料で形成されたものを用いることができ、光透過性を有するもの及び光透過性を有しないもののいずれも用いることができる。例えば、ケイ酸アルカリ系ガラス、石英ガラス、窒化ケイ素などを形成材料とする無機基板;シリコン基板;表面が絶縁処理された金属基板;アクリル樹脂、ポリカーボネート樹脂、PET(ポリエチレンテレフタレート)やPBT(ポリブチレンテレフタレート)などのポリエステル樹脂などを形成材料とする樹脂基板;紙製の基板などの種々のものを用いることができる。また、これらの材料を複数組み合わせた複合材料を形成材料とする基板であっても構わない。基板20の厚さは、設計に応じて適宜設定することができる。 FIG. 1 is a schematic cross-sectional view of a thin film transistor 10 according to a preferred embodiment of the first invention of the present application. As the substrate 20, a substrate formed of a known forming material can be used, and any of those having optical transparency and those having no optical transparency can be used. For example, an inorganic substrate made of alkali silicate glass, quartz glass, silicon nitride, or the like; a silicon substrate; a metal substrate whose surface is insulated; acrylic resin, polycarbonate resin, PET (polyethylene terephthalate), or PBT (polybutylene) Various substrates such as a resin substrate made of a polyester resin such as terephthalate) or a paper substrate can be used. Further, the substrate may be a composite material formed by combining a plurality of these materials. The thickness of the substrate 20 can be appropriately set according to the design.

 本実施形態の薄膜トランジスタ10は、いわゆるボトムゲート型のトランジスタである。薄膜トランジスタ10は、基板20上に設けられたゲート電極30と、ゲート電極30を覆って設けられた絶縁体層40と、絶縁体層40の上面に設けられた半導体層50と、半導体層50の上面において半導体層50に接して設けられたソース電極60およびドレイン電極70、並びに層間絶縁膜80を有している。ゲート電極30は、半導体層50のチャネル領域に対応させて(チャネル領域と平面的に重なる位置に)設けられている。また、半導体層50は、酸素欠損が導入されることで電子キャリアを生成できる第1金属酸化物へ第2酸化物(XOx)を添加した複合金属酸化物から構成されている。なお、当然のことであるが、本願第1発明の作用効果にはなはだしい悪影響が出ない限り、半導体層に第2酸化物以外の成分や不可避の不純物が含まれていてもよい。 The thin film transistor 10 of this embodiment is a so-called bottom gate type transistor. The thin film transistor 10 includes a gate electrode 30 provided on the substrate 20, an insulator layer 40 provided to cover the gate electrode 30, a semiconductor layer 50 provided on the upper surface of the insulator layer 40, A source electrode 60 and a drain electrode 70 provided in contact with the semiconductor layer 50 on the upper surface, and an interlayer insulating film 80 are provided. The gate electrode 30 is provided corresponding to the channel region of the semiconductor layer 50 (at a position overlapping the channel region in a plan view). The semiconductor layer 50 is composed of a composite metal oxide obtained by adding a second oxide (XOx) to a first metal oxide capable of generating electron carriers by introducing oxygen vacancies. As a matter of course, the semiconductor layer may contain components other than the second oxide and inevitable impurities as long as the adverse effects of the first invention of the present application are not adversely affected.

 ゲート電極30、ソース電極60、及びドレイン電極70は、それぞれ通常知られた材料で形成されたものを用いることができる。これらの電極の形成材料としては、例えば、アルミニウム(Al)、金(Au)、銀(Ag)、銅(Cu)、ニッケル(Ni)、モリブデン(Mo)、タンタル(Ta)、タングステン(W)などの金属材料やこれらの合金、インジウムスズ酸化物(Indium Tin Oxide、ITO)、酸化亜鉛(ZnO)などの導電性酸化物を挙げることができる。また、これらの電極は、例えば表面を金属材料でめっきすることにより2層以上の積層構造を形成していてもよい。 Each of the gate electrode 30, the source electrode 60, and the drain electrode 70 can be made of a generally known material. Examples of the material for forming these electrodes include aluminum (Al), gold (Au), silver (Ag), copper (Cu), nickel (Ni), molybdenum (Mo), tantalum (Ta), and tungsten (W). Examples thereof include metal materials such as these, alloys thereof, and conductive oxides such as indium tin oxide (ITO) and zinc oxide (ZnO). Moreover, these electrodes may form the laminated structure of two or more layers, for example by plating the surface with a metal material.

 ゲート電極30、ソース電極60、及びドレイン電極70は、同じ形成材料で形成されたものであってもよく、異なる形成材料で形成されたものであってもよい。製造が容易となることから、ソース電極60とドレイン電極70とは同じ形成材料であることが好ましい。 The gate electrode 30, the source electrode 60, and the drain electrode 70 may be formed of the same forming material or may be formed of different forming materials. Since manufacture becomes easy, it is preferable that the source electrode 60 and the drain electrode 70 are the same formation material.

 絶縁体層40は、絶縁性を有し、ゲート電極30と、ソース電極60およびドレイン電極70との間を電気的に絶縁することが可能であれば、無機材料および有機材料のいずれを用いて形成してもよい。無機材料としては、例えばSiO、SiN、SiON、Al、HfOなどの通常知られた絶縁性の酸化物、窒化物、酸窒化物を挙げることができる。有機材料としては、例えば、アクリル樹脂、エポキシ樹脂、シリコン樹脂、フッ素系樹脂などを挙げることができる。有機材料としては、製造や加工が容易であることから、光硬化型の樹脂材料であることが好ましい。 The insulator layer 40 has an insulating property, and any of an inorganic material and an organic material can be used as long as it can electrically insulate the gate electrode 30 from the source electrode 60 and the drain electrode 70. It may be formed. Examples of the inorganic material include normally known insulating oxides such as SiO 2 , SiN x , SiON, Al 2 O 3 , and HfO 2 , nitrides, and oxynitrides. Examples of the organic material include acrylic resin, epoxy resin, silicon resin, and fluorine resin. The organic material is preferably a photocurable resin material because it is easy to manufacture and process.

 半導体層50は、酸素欠損が導入されることで電子キャリアを生成できる第1金属酸化物と、酸素とのかい離エネルギーが第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きい第2酸化物とを含む複合酸化物で形成される。第1金属酸化物は、好ましくは、インジウム(In)、ガリウム(Ga)、亜鉛(Zn)、および錫(Sn)からなる群から選択された少なくとも1つを含む金属酸化物であり、第2酸化物は、好ましくはジルコニウム(Zr)、ケイ素(Si)、チタン(Ti)、タングステン(W)、タンタル(Ta)、ハフニウム(Hf)、スカンジウム(Sc)、イットリウム(Y)、ランタン(La)、プラセオジム(Pr)、ネオジム(Nd)、ガドリニウム(Gd)、それ以外の希土類元素、アルミニウム(Al)、ボロン(B)および炭素(C)からなる群から選択された少なくとも1つを含む酸化物である。
 好ましくは、第1酸化物の元素がInである場合、第2酸化物の元素は、Zr、Pr、Si、Ti、W、Ta、La、Hf、B、Cからなる群から選択された少なくとも1つであり、第1酸化物の元素がSnである場合、第2酸化物の元素は、Sc、Ti、W、Nd、Gdからなる群から選択された少なくとも1つの元素である。
The semiconductor layer 50 includes a second metal oxide having energy greater than that of the first metal oxide that can generate electron carriers by introducing oxygen vacancies by 200 kJ / mol or more. It is formed of a complex oxide containing an oxide. The first metal oxide is preferably a metal oxide including at least one selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), and tin (Sn), and the second The oxide is preferably zirconium (Zr), silicon (Si), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), scandium (Sc), yttrium (Y), lanthanum (La). Oxide containing at least one selected from the group consisting of praseodymium (Pr), neodymium (Nd), gadolinium (Gd), other rare earth elements, aluminum (Al), boron (B), and carbon (C) It is.
Preferably, when the element of the first oxide is In, the element of the second oxide is at least selected from the group consisting of Zr, Pr, Si, Ti, W, Ta, La, Hf, B, and C. In the case where the element of the first oxide is Sn and the element of the first oxide is Sn, the element of the second oxide is at least one element selected from the group consisting of Sc, Ti, W, Nd, and Gd.

 第1金属酸化物として酸化インジウム(In)を用いた場合、酸化インジウムの酸素のかい離エネルギーは346±30kJ/molと小さいので、酸化インジウムから酸素が容易に脱離して酸素欠損を生成しやすい。しかし、酸素欠損量が大きくなりすぎると半導体的な性質から金属的な性質へ変わって半導体層として適さなくなる。この問題を解決すべく、酸化インジウムの酸素欠損量を制御するため酸化インジウムの酸素のかい離エネルギーより200kJ/mol/以上大きな酸素のかい離エネルギーを有する第2酸化物(XO)、より具体的には金属酸化物である第2金属酸化物あるいは後述するように同等の非金属元素酸化物を添加すればよい。第2酸化物の酸素のかい離エネルギーは、上記で規定するものよりも更に大きいことが好ましく、酸素のかい離エネルギーが725kJ/mol以上、より好ましくは780kJ/mol以上の酸化物を第2酸化物として用いると、酸化インジウムの酸素欠損量の制御が容易となるので望ましい。なお、第1金属酸化物として酸化インジウム以外の物質まで一般化した場合には、上述のように第2酸化物としてはその酸素かい離エネルギーが第1金属酸化物に比べて200kJ/mol以上、より好ましくは255kJ/mol以上大きいものを使用すればよい。本実施形態では第2酸化物として好ましくは金属酸化物を使用するが、具体的に好適な金属酸化物としては、酸素のかい離エネルギーが780kJ/mol以上の酸化物をまとめた表A1および酸素のかい離エネルギーが725kJ/mol以上かつ780kJ/mol以下の金属酸化物をまとめた表A2に示すように、酸化ジルコニウム(Zr-O)、酸化プラセオジム(Pr-O)、酸化ランタン(La-O)、酸化タンタル(Ta-O)、および酸化ハフニウム(Hf-O)が挙げられるが、これらには限定されない。また、同じく表A1記載の酸化ケイ素(Si-O)も、第2酸化物として好ましい。 When indium oxide (In 2 O 3 ) is used as the first metal oxide, the oxygen separation energy of indium oxide is as small as 346 ± 30 kJ / mol, so oxygen is easily desorbed from indium oxide to generate oxygen vacancies. It's easy to do. However, if the amount of oxygen vacancies becomes too large, it changes from semiconducting properties to metallic properties, making it unsuitable as a semiconductor layer. In order to solve this problem, in order to control the oxygen deficiency of indium oxide, a second oxide (XO x ) having an oxygen separation energy of 200 kJ / mol / greater than the oxygen separation energy of indium oxide, more specifically, The second metal oxide, which is a metal oxide, or an equivalent nonmetallic element oxide as described later may be added. The oxygen separation energy of the second oxide is preferably larger than that specified above, and an oxide having an oxygen separation energy of 725 kJ / mol or more, more preferably 780 kJ / mol or more is used as the second oxide. When used, it is preferable because the oxygen deficiency of indium oxide can be easily controlled. In addition, when materials other than indium oxide are generalized as the first metal oxide, as described above, the oxygen separation energy of the second oxide is 200 kJ / mol or more as compared with the first metal oxide. Preferably a thing larger than 255 kJ / mol may be used. In the present embodiment, a metal oxide is preferably used as the second oxide, but as a particularly suitable metal oxide, Table A1 in which oxides having an oxygen separation energy of 780 kJ / mol or more are summarized and oxygen As shown in Table A2, which summarizes metal oxides having a separation energy of 725 kJ / mol to 780 kJ / mol, zirconium oxide (Zr—O), praseodymium oxide (Pr—O), lanthanum oxide (La—O), Examples include, but are not limited to, tantalum oxide (Ta—O) and hafnium oxide (Hf—O). Similarly, silicon oxide (Si—O) described in Table A1 is also preferable as the second oxide.

Figure JPOXMLDOC01-appb-T000001

 
Figure JPOXMLDOC01-appb-T000001

 

Figure JPOXMLDOC01-appb-T000002

 
Figure JPOXMLDOC01-appb-T000002

 

 本実施形態において第1金属酸化物を適した酸素欠損量を有する半導体層とするために添加する第2酸化物としては、特に好ましくは、表A1に示した780kJ/mol以上の第2酸化物がより好ましい。具体的には、酸化ランタン(La-O)、酸化ケイ素(Si-O)、酸化タンタル(Ta-O)、および酸化ハフニウム(Hf-O)が挙げられる。 In the present embodiment, the second oxide added to make the first metal oxide a semiconductor layer having an appropriate oxygen deficiency is particularly preferably a second oxide of 780 kJ / mol or more shown in Table A1. Is more preferable. Specifically, lanthanum oxide (La—O), silicon oxide (Si—O), tantalum oxide (Ta—O), and hafnium oxide (Hf—O) can be given.

 また、第1金属酸化物を適した酸素欠損量を有する半導体層とするために第1金属酸化物へ添加する第2酸化物の含有量には特に制限はないが、0より大きく50重量%以下の範囲にするとよい。特に、第1金属酸化物へ添加する第2酸化物の含有量を0より大きく5重量%以下の範囲にすると、200℃以下の低温度で作製できるなどの点で、実用上好ましい。 Further, the content of the second oxide added to the first metal oxide in order to make the first metal oxide a semiconductor layer having a suitable oxygen deficiency is not particularly limited, but is larger than 0 and 50% by weight. The following range is recommended. In particular, when the content of the second oxide added to the first metal oxide is in the range of more than 0 and 5% by weight or less, it is practically preferable in that it can be produced at a low temperature of 200 ° C. or less.

 In-Zn-O系やIn-Ga-Zn-O系の金属酸化物では、半導体層の形成時に多結晶状になりやすい。そのため、通常知られた薄膜トランジスタでは、半導体層に含まれる結晶粒に起因して、半導体層の表面が平坦にはならない。また、通常知られた酸化膜トランジスタの半導体層は、このような結晶粒に起因して、面方向の電気伝導度が低下してしまう。したがって、半導体層50の表面の平坦化及び高い電気伝導度を得るためには、半導体層は非晶質構造であることが好ましい。 In-Zn-O-based and In-Ga-Zn-O-based metal oxides tend to be polycrystalline when a semiconductor layer is formed. Therefore, in a generally known thin film transistor, the surface of the semiconductor layer does not become flat due to crystal grains contained in the semiconductor layer. In addition, the normally known semiconductor layer of an oxide film transistor has a reduced electrical conductivity in the plane direction due to such crystal grains. Therefore, in order to obtain planarization of the surface of the semiconductor layer 50 and high electrical conductivity, the semiconductor layer preferably has an amorphous structure.

 また、半導体層50の厚みには特に制限はないが、5nm以上かつ20nm以下の範囲であることがより好ましい。なお、本実施形態において、半導体層50の厚さは、半導体層5を形成したスパッタチャンバー内に、膜厚校正を主目的として配置された水晶発振式膜厚計を用いて測定することができる。 Further, the thickness of the semiconductor layer 50 is not particularly limited, but is preferably in the range of 5 nm or more and 20 nm or less. In the present embodiment, the thickness of the semiconductor layer 50 can be measured by using a crystal oscillation type film thickness meter arranged mainly for film thickness calibration in the sputtering chamber in which the semiconductor layer 5 is formed. .

 なお、半導体層50を構成する複合金属酸化物は第1金属酸化物に第2酸化物として金属酸化物を添加したものには限定されず、第1金属酸化物に比べてかい離エネルギーが200kJ/mol以上大きな非金属酸化物を添加してもよい。具体的には、複合金属酸化物は、例えばボロン(B)および炭素(C)のうち少なくとも一つの元素の酸化物を添加したものであっても良い(すなわち、本願では「複合金属酸化物」を「金属酸化物に酸素のとのかい離エネルギーが所定値以上大きな元素を複合させた酸化物」という意味で使用していることに注意されたい)。これは、B-O結合の酸素かい離エネルギーが809kJ/molおよびC-O結合の酸素かい離エネルギーが1076.38±0.67kJ/molと大きいために、第1金属酸化物へ導入する酸素欠損量を容易に制御することができるからである。 In addition, the composite metal oxide which comprises the semiconductor layer 50 is not limited to what added the metal oxide as a 2nd oxide to the 1st metal oxide, and the separation energy is 200 kJ / in comparison with the 1st metal oxide. A non-metal oxide larger than mol may be added. Specifically, the composite metal oxide may be, for example, an oxide of at least one element selected from boron (B) and carbon (C) (ie, “composite metal oxide” in the present application). Is used to mean "an oxide in which a metal oxide is combined with an element having an energy greater than a predetermined value for oxygen"). This is because the oxygen desorption energy of the B—O bond is as large as 809 kJ / mol and the oxygen desorption energy of the C—O bond is as large as 1076.38 ± 0.67 kJ / mol, so that the amount of oxygen deficiency introduced into the first metal oxide This is because it can be easily controlled.

 本願第1発明においては、第2酸化物を構成する元素Xのうち、ケイ素、タンタル、ジルコニウム、ハフニウム、アルミニウム、イットリウム及び希土類元素からなる群より選ばれる少なくとも一種の元素Xの濃度が、半導体層の厚み方向の中央部において極大値を示す。これにより、本願第1発明では、短波長の可視光、例えば波長420nmの光照射による薄膜トランジスタのしきい値電圧のシフトが抑制されるという、実用上高い価値を有する顕著な技術的効果が実現される。以下、この点につき、第1金属酸化物が酸化インジウム(In)である場合を例に説明する。 Present in the first invention, among the element X included in the second oxide, silicon, tantalum, zirconium, hafnium, aluminum, at least one of the concentration of the element X 1 is selected from the group consisting of yttrium and rare earth elements, semiconductor The maximum value is shown at the center in the thickness direction of the layer. As a result, in the first invention of the present application, a remarkable technical effect having a high practical value is realized in that the shift of the threshold voltage of the thin film transistor due to irradiation with short-wavelength visible light, for example, light with a wavelength of 420 nm is suppressed. The Hereinafter, the case where the first metal oxide is indium oxide (In 2 O 3 ) will be described as an example.

 酸化インジウム(In)を含む複合酸化物における、波長420nmの光照射による薄膜トランジスタのしきい値電圧のシフトの要因として、光吸収により、Inバンドギャップの価電子帯近傍の酸素欠損による準位から伝導帯近傍のトラップ準位へ電子がホッピングすることが推定されている。Inのバンドギャップは約3.7eVであり、このバンドギャップの伝導帯(真空準位から4.05eV)を大きく拡大する(真空準位側へ近づける)ことで、上記の電子のホッピングに必要なエネルギーも大きくでき、結果として、光照射によるしきい値電圧のシフトを抑制できることが期待できる。 In a composite oxide containing indium oxide (In 2 O 3 ), oxygen in the vicinity of the valence band of the In 2 O 3 band gap is caused by light absorption as a factor of the threshold voltage shift of the thin film transistor due to light irradiation with a wavelength of 420 nm. It is estimated that electrons hop from a level due to defects to a trap level near the conduction band. The band gap of In 2 O 3 is about 3.7 eV, and the above-mentioned electron hopping is achieved by enlarging the conduction band of this band gap (from the vacuum level to 4.05 eV) (closer to the vacuum level side). It can be expected that the energy required for the above can be increased, and as a result, the shift of the threshold voltage due to light irradiation can be suppressed.

 そこで、発明者らは、Inの伝導帯との差がプラスになるSiO(+3.5eV)をInへ添加したIn-Si-O膜のバンドギャップを調べた。図3にSiOとしての重量がそれぞれ1、3、及び10重量%の膜厚が50nmのIn-Si-O膜の光電子収量分光法によるバンドギャップの評価結果を示す。SiO含量が1重量%のとき約3.7eVであったバンドギャップを、SiO含量を10重量%に増加することで、4.5eVまで拡大することができた。 Therefore, we studied the band gap of an In-SiO film difference added SiO 2 becomes plus (+ 3.5 eV) to In 2 O 3 and the conduction band of the In 2 O 3. FIG. 3 shows the evaluation results of the band gap by photoelectron yield spectroscopy of an In—Si—O film having a thickness of 50 nm with SiO 2 weights of 1, 3 and 10% by weight, respectively. The band gap, which was about 3.7 eV when the SiO 2 content was 1% by weight, could be increased to 4.5 eV by increasing the SiO 2 content to 10% by weight.

 第2酸化物XOのうち、SiOと同様にバンドギャップを拡大する効果を有しうる酸化物の候補としては、Ta(+0.3eV)、ZrO(+1.4eV)、HfO(+1.5eV)、Al(+2.8eV)、Y(+1.3eV)および希土類酸化物が挙げられる。従って、第1酸化物XOを構成する元素Xのうち、しきい値電圧のシフトの抑制を目的として添加される元素Xは、ケイ素、タンタル、ジルコニウム、ハフニウム、アルミニウム、イットリウム及び希土類元素からなる群より選ばれる。また、Si(+2.4eV)も、同様にバンドギャップを拡大する効果を有しうるものであり、第2酸化物とともに、又は第2酸化物に代えて、Siを半導体層を構成する複合金属酸化物に添加することも好ましい。 Among the second oxides XO x , candidate oxides that can have the effect of expanding the band gap like SiO 2 are Ta 2 O 5 (+0.3 eV), ZrO 2 (+1.4 eV), HfO. 2 (+1.5 eV), Al 2 O 3 (+2.8 eV), Y 2 O 3 (+1.3 eV) and rare earth oxides. Therefore, among the elements X constituting the first oxide XO x , the element X 1 added for the purpose of suppressing the threshold voltage shift is silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements. Selected from the group of Similarly, Si 3 N 4 (+2.4 eV) can also have an effect of widening the band gap, and Si 3 N 4 can be used as a semiconductor together with or in place of the second oxide. It is also preferable to add to the composite metal oxide constituting the layer.

 In膜へ導入する元素Xの酸化物の濃度は通常3重量%以上50重量%以下であり、特に10~30重量%の濃度範囲が、添加による好ましくない効果を抑制しながらバンドギャップを拡大する観点から好ましい。 The concentration of the oxide of the element X 1 introduced into the In 2 O 3 film is usually 3% by weight or more and 50% by weight or less. Particularly, the concentration range of 10 to 30% by weight suppresses undesirable effects due to the addition. This is preferable from the viewpoint of expanding the gap.

 上述のように、本願第1発明において、半導体層中の元素Xは、半導体層において、中央部で濃度が高く、両界面で濃度が低いという濃度勾配を有する。すなわち、上記少なくとも一種の元素Xの濃度は、前記半導体層の厚み方向の中央部において極大値すなわち少なくとも1のピークを示す。ここで「中央部」の意義は、上述のとおりである。 As described above, in the first invention, the element X 1 of the semiconductor layer is a semiconductor layer, a high density at the central portion, having a concentration gradient of a low density at both interfaces. That is, the at least one concentration of the element X 1 represents a local maximum value, i.e. at least one peak at the center in the thickness direction of the semiconductor layer. Here, the meaning of the “central part” is as described above.

 本願第1発明の好ましい一実施形態においては、元素Xの酸化物の濃度は、半導体層の厚み方向の中央部において最大値、例えば3重量%以上、50重量%以下、好ましくは10重量%以上、30重量%以下となることが好ましく、そこから両界面に近づくにつれて、それぞれ単調に減少する濃度勾配を有していることが好ましい。両界面における元素Xの酸化物の濃度は、中央部における濃度よりも実質的に低ければよく、特に制限はないが、例えば、0.1重量%以下であることが好ましく、実質的にゼロであることが特に好ましい。 Present in a preferred embodiment of the first invention, the concentration of oxide of the element X 1 is the maximum value in the central portion in the thickness direction of the semiconductor layer, for example, 3 wt% or more, 50 wt% or less, preferably 10 wt% As described above, it is preferably 30% by weight or less, and preferably has a concentration gradient that decreases monotonously as it approaches both interfaces. The concentration of the oxide of the element X 1 at both interfaces is not particularly limited as long as it is substantially lower than the concentration at the center, and is preferably 0.1% by weight or less, for example, substantially zero. It is particularly preferred that

 本願第1発明においては、両界面における元素Xの濃度が低いことにより、ソース電極及び/又はドレイン電極と半導体層との界面におけるコンタクト抵抗が低く、かつ電子移動度が高くゲート制御性に優れるという、実用上好ましい特性を実現することができる。
 ソース電極及び/又はドレイン電極と半導体層との界面における半導体層を構成する複合酸化物中の元素Xの濃度が低いことにより、該複合酸化物は酸素を放出しやすい傾向を有することとなる。この結果、ソース電極及び/又はドレイン電極との界面付近の複合酸化物は、酸素欠損を生じていわゆるメタル化することとなり、ソース電極及び/又はドレイン電極とのコンタクト抵抗が低減される。
 また、半導体層を構成する複合酸化物中の元素Xの濃度が低く、それ以外の第2酸化物の濃度が高いことにより、電子の移動度が向上する傾向がある。ゲート電圧の影響をより受けやすい、ゲート電極側の絶縁膜層との界面付近において、半導体層の元素Xの濃度を低く(電子移動度を高く)することによって、同じゲート電圧でより高い電流を制御することが可能となる、すなわちゲート制御性が向上するという効果が実現できる。
In the first invention, by the concentration of the element X 1 in both interfaces is low, the contact resistance at the interface between the source electrode and / or drain electrode and the semiconductor layer is low and excellent in high gate controllability electron mobility That is, a practically preferable characteristic can be realized.
By concentration of the element X 1 in the composite oxide constituting the semiconductor layer at the interface between the source electrode and / or drain electrode and the semiconductor layer is low, the composite oxide will have a tendency to release oxygen . As a result, the complex oxide in the vicinity of the interface with the source electrode and / or drain electrode generates oxygen vacancies and is so-called metalized, and the contact resistance with the source electrode and / or drain electrode is reduced.
Also, low concentration of the element X 1 in the composite oxide constituting the semiconductor layer, by high concentration of the second oxide otherwise, electron mobility tends to increase. Effect more susceptible to the gate voltage, in the vicinity of the interface between the gate electrode side of the insulating layer, by the concentration of the element X 1 of the semiconductor layer low (high electron mobility) higher current at the same gate voltage Can be controlled, that is, the effect of improving the gate controllability can be realized.

 本願第2発明の薄膜トランジスタは、
 ソース電極およびドレイン電極と、
 前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、
 前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、
 前記ゲート電極と前記半導体層との間に設けられた絶縁体層と
を有する薄膜トランジスタであって、
 前記半導体層が、酸素欠損が導入されることで電子キャリアを生成できる第1金属酸化物に、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物(XO)を添加した複合金属酸化物で形成され、
 前記第2酸化物を構成する元素Xのうち、ケイ素、タンタル、ジルコニウム、ハフニウム、アルミニウム、イットリウム及び希土類元素のいずれにも該当しない少なくとも一種の元素Xの濃度が、前記半導体層の厚み方向の中央部において極小値を示す、上記薄膜トランジスタである。
The thin film transistor of the second invention of the present application,
A source electrode and a drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
A thin film transistor having an insulator layer provided between the gate electrode and the semiconductor layer,
The semiconductor layer has a second metal oxide that can generate electron carriers by introducing oxygen vacancies, and the second energy of oxygen is 200 kJ / mol or more higher than that of the first metal oxide. Formed of a composite metal oxide to which an oxide (XO x ) is added,
Among the elements X constituting the second oxide, the concentration of at least one element X 2 that does not correspond to any of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements is in the thickness direction of the semiconductor layer. The thin film transistor having a minimum value in the center.

 ここで、上記少なくとも一種の元素Xの濃度は、上記半導体層の厚み方向において連続的にかつ実質的に変動しており、すなわち上記少なくとも一種の元素Xは、上記半導体層の厚み方向に濃度勾配を有している。より具体的には、上記少なくとも一種の元素Xの濃度は、前記半導体層の厚み方向の中央部において極小値を示す。ここで、「中央部」とは、上記半導体層の両界面(通常は、ソース電極及びドレイン電極側の層間絶縁膜と接する界面、及びゲート電極側の絶縁体層と接する界面)のいずれからも、2nm以上、又は半導体層の厚みの5%以上離れている箇所をいう。
 好ましくは、上記少なくとも一種の元素Xの濃度は、半導体層の厚み方向の中央部において最小値を示す。すなわち、半導体層の厚み方向の中央部のいずれかの場所における元素Xの濃度は、半導体層の他のいずれの箇所における元素Xの濃度よりも低いことが好ましい。
Here, the concentration of the at least one element X 2 continuously and substantially varies in the thickness direction of the semiconductor layer, that is, the at least one element X 2 is in the thickness direction of the semiconductor layer. It has a concentration gradient. More specifically, the concentration of the at least one element X 2 has a minimum value at the center in the thickness direction of the semiconductor layer. Here, the “central portion” refers to both the interfaces of the semiconductor layer (usually, the interface in contact with the interlayer insulating film on the source electrode and drain electrode side and the interface in contact with the insulator layer on the gate electrode side). It refers to a location 2 nm or more, or 5% or more of the thickness of the semiconductor layer.
Preferably, the at least one element X 2 concentration shows a minimum value at the central portion in the thickness direction of the semiconductor layer. That is, the concentration of the element X 2 in any location of the central portion in the thickness direction of the semiconductor layer is preferably lower than the concentration of the element X 2 in any other portion of the semiconductor layer.

 上記少なくとも一種の元素Xは、前記第2酸化物を構成する元素X、すなわち第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物(XO)を構成する元素Xのうち、ケイ素、タンタル、ジルコニウム、ハフニウム、アルミニウム、イットリウム及び希土類元素のいずれにも該当しない元素である。
 元素Xは上記の定義に該当する元素であればよく、それ以外に特に制限は課せられないが、好ましくはチタン(Ti)である。また、タングステン(W)も、元素Xとして使用することが可能である。
The at least one element X 2 is an element constituting the second oxide, that is, an element constituting the second oxide (XO x ) that is 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide. X is an element that does not correspond to any of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements.
Element X 2 may be any element which corresponds to the above definition, but is not imposed specifically limited otherwise, preferably titanium (Ti). Further, tungsten (W) also can be used as the element X 2.

 本願第2発明において、半導体層中の元素Xの酸化物は、半導体層において、中央部で濃度が低く、両界面で濃度が高いという濃度勾配を有する。すなわち、上記少なくとも一種の元素Xの濃度は、前記半導体層の厚み方向の中央部において極小値を示す。 In the present second invention, oxides of elements X 2 in the semiconductor layer is a semiconductor layer, a low density at the central portion, having a concentration gradient of high concentration both interfaces. That is, the at least one element X 2 concentration shows a minimum value at the central portion in the thickness direction of the semiconductor layer.

 本願第2発明の好ましい一実施形態においては、元素Xの酸化物の濃度は、半導体層の厚み方向の中央部において極小値を有していることが好ましく、そこから両界面に近づくにつれて、それぞれ単調に増加する濃度勾配を有していることが好ましい。両界面における元素Xの酸化物の濃度には特に制限はないが、移動度を高くするため等の観点から、1重量%以上20重量%以下であることが好ましい。中央部における元素Xの酸化物の濃度は、両界面における濃度よりも実質的に低ければよく、特に制限はないが、例えば、0.1重量%以下であることが好ましく、実質的にゼロであることが特に好ましい。 As in the preferred embodiment of the second aspect of the present invention, the concentration of the oxide of the element X 2 is preferably to have a minimum value in the central portion in the thickness direction of the semiconductor layer approaches from there to both interfaces, Each preferably has a monotonically increasing concentration gradient. There is no particular limitation on the concentration of the oxide of the element X 2 in both interfaces, from the viewpoint of for increasing the mobility is preferably 20 wt% or less 1 wt% or more. The concentration of the oxide of the element X 2 in the central portion is not particularly limited as long as it is substantially lower than the concentration at both interfaces, and is preferably 0.1% by weight or less, for example, substantially zero. It is particularly preferred that

 また、本願第2発明においては、両界面における元素Xの濃度が高いことにより、ソース電極及び/又はドレイン電極と半導体層との界面におけるコンタクト抵抗が低く、かつ電子移動度が高くゲート制御性に優れるという、実用上好ましい特性を実現することができる。
 ソース電極及び/又はドレイン電極と半導体層との界面における半導体層を構成する複合酸化物中の元素X(例えばチタン)の濃度が高いことにより、該複合酸化物は酸素を放出しやすい傾向を有することとなる。この結果、ソース電極及び/又はドレイン電極との界面付近の複合酸化物は、酸素欠損を生じていわゆるメタル化することとなり、ソース電極及び/又はドレイン電極とのコンタクト抵抗が低減される。
 また、半導体層を構成する複合酸化物中の元素X(例えばチタン)の濃度が高いことにより、電子の移動度が向上する傾向がある。ゲート電圧の影響をより受けやすい、ゲート電極側の絶縁膜層との界面付近において、半導体層の元素Xの濃度が高く電子移動度が高いことによって、同じゲート電圧でより高い電流を制御することが可能となる、すなわちゲート制御性が向上するという効果が実現できる。
In the second invention of the present application, since the concentration of the element X 2 at both interfaces is high, the contact resistance at the interface between the source electrode and / or the drain electrode and the semiconductor layer is low, the electron mobility is high, and the gate controllability. It is possible to realize a practically preferable characteristic of being excellent in resistance.
Due to the high concentration of element X 2 (for example, titanium) in the composite oxide constituting the semiconductor layer at the interface between the source electrode and / or drain electrode and the semiconductor layer, the composite oxide tends to release oxygen. Will have. As a result, the complex oxide in the vicinity of the interface with the source electrode and / or drain electrode generates oxygen vacancies and is so-called metalized, and the contact resistance with the source electrode and / or drain electrode is reduced.
Further, since the concentration of the element X 2 (for example, titanium) in the complex oxide constituting the semiconductor layer is high, the electron mobility tends to be improved. Effect more susceptible to the gate voltage, in the vicinity of the interface between the gate electrode side of the insulating film layer, by a high high electron mobility concentration of the element X 2 of the semiconductor layer to control a higher current at the same gate voltage In other words, an effect that gate controllability is improved can be realized.

 本願第2発明の薄膜トランジスタの層構成その他の構造は、本願第1発明のものと同様である。上記の本願第1発明の構造についての記載は、本願第2発明の目的に反しない限りにおいて、本願第2発明にも適宜あてはまる。 The layer structure and other structures of the thin film transistor of the second invention of the present application are the same as those of the first invention of the present application. The above description of the structure of the first invention of the present application also applies to the second invention of the present application as long as it does not contradict the purpose of the second invention of the present application.

 本願第1発明の元素Xの濃度分布と、本願第2発明の元素Xの濃度分布とをともに具備している薄膜トランジスタは、本願第1~第3発明の特に好ましい実施形態である。この実施形態においては、第2酸化物を構成する元素Xのうち、ケイ素、タンタル、ジルコニウム、ハフニウム、アルミニウム、イットリウム及び希土類元素からなる群より選ばれる少なくとも一種の元素Xの濃度が、半導体層の厚み方向の中央部において極大値を示し、かつ、第2酸化物を構成する元素Xのうち、ケイ素、タンタル、ジルコニウム、ハフニウム、アルミニウム、イットリウム及び希土類元素のいずれにも該当しない少なくとも一種の元素Xの濃度が、前記半導体層の厚み方向の中央部において極小値を示す。この実施形態においては、例えば、元素Xに該当するケイ素の濃度が半導体層の厚み方向の中央部において極大値を示し、かつ、元素Xに該当するチタンの濃度が半導体層の厚み方向の中央部において極小値を示していてもよい。 Present a concentration distribution of elements X 1 of the first invention, both are provided with a thin film transistor and a concentration distribution of elements X 2 of the present second invention is a particularly preferred embodiment of the present first to third inventions. In this embodiment, the concentration of at least one element X 1 selected from the group consisting of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements among the elements X constituting the second oxide is the semiconductor layer. And at least one element that does not correspond to any of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements among the elements X constituting the second oxide. the concentration of X 2 indicates a minimum value at the central portion in the thickness direction of the semiconductor layer. In this embodiment, for example, the concentration of silicon that corresponds to the element X 1 represents a maximum value in the central portion in the thickness direction of the semiconductor layer, and the concentration of titanium corresponding to the element X 2 is the thickness direction of the semiconductor layer A minimum value may be shown at the center.

 このとき、半導体層の中央部においてケイ素の濃度が極大値を示すことによって、光照射によるしきい値電流のシフト等の特性劣化が抑制されるという的効果が実現されるとともに、半導体層の両界面におけるチタンの濃度が高いことにより、ソース電極及び/又はドレイン電極と半導体層との界面におけるコンタクト抵抗が低く、かつ電子移動度が高くゲート制御性に優れるという効果が実現され、実用上好ましい諸特性を高いレベルで兼ね備えた薄膜トランジスタを実現することができる。 At this time, the silicon concentration at the central portion of the semiconductor layer exhibits a maximum value, thereby realizing a target effect of suppressing characteristic deterioration such as a shift in threshold current due to light irradiation, and both of the semiconductor layers. The high titanium concentration at the interface realizes the effect that the contact resistance at the interface between the source electrode and / or drain electrode and the semiconductor layer is low, the electron mobility is high, and the gate controllability is excellent. A thin film transistor having characteristics at a high level can be realized.

 本願第3発明の薄膜トランジスタは、
 ソース電極およびドレイン電極と、
 前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、
 前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、
 前記ゲート電極と前記半導体層との間に設けられた絶縁体層と
を有する薄膜トランジスタであって、
 前記半導体層が、酸素欠損が導入されることで電子キャリアを生成できる第1金属酸化物に、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物(XOx)を添加した複合金属酸化物で形成され、
 前記半導体層が、更に窒素を含有し、窒素の濃度が、前記半導体層の厚み方向の中央部において極大値を示す、上記薄膜トランジスタである。
 また、本願第1発明、及び本願第2発明においても、半導体層が更に窒素を含有し、窒素の濃度が、前記半導体層の厚み方向の中央部において極大値を示すことが好ましい。
 窒素の導入、特に半導体層の厚み方向の中央部に導入することにより、半導体層の価電子帯が変化して、価電子帯近傍で生じる酸素欠損に起因した準位を抑制でき、結果として光照射によるしきい値電流のシフト等の悪影響を抑制することができる。この観点から、窒素の濃度は、半導体層の界面において低く、厚み方向の中央部において極大値を示す分布となることが好ましい。
The thin film transistor of the third invention of the present application,
A source electrode and a drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
A thin film transistor having an insulator layer provided between the gate electrode and the semiconductor layer,
The semiconductor layer has a second metal oxide that can generate electron carriers by introducing oxygen vacancies, and the second energy of oxygen is 200 kJ / mol or more higher than that of the first metal oxide. Formed of a complex metal oxide to which an oxide (XOx) is added,
In the thin film transistor, the semiconductor layer further contains nitrogen, and the concentration of nitrogen shows a maximum value in a central portion in the thickness direction of the semiconductor layer.
Also in the first and second inventions of the present application, it is preferable that the semiconductor layer further contains nitrogen, and the concentration of nitrogen exhibits a maximum value at the central portion in the thickness direction of the semiconductor layer.
By introducing nitrogen, particularly in the central portion of the semiconductor layer in the thickness direction, the valence band of the semiconductor layer changes, and the level caused by oxygen vacancies generated near the valence band can be suppressed. It is possible to suppress adverse effects such as threshold current shift due to irradiation. From this point of view, the nitrogen concentration is preferably low at the interface of the semiconductor layer and has a distribution showing a maximum value in the central portion in the thickness direction.

 なお、半導体層がSi等を含有する場合、当該半導体層が更に窒素を含有し、窒素の濃度が、前記半導体層の厚み方向の中央部において極大値を示していることが好ましい。この場合、上記の窒素濃度分布に関する効果に加えて、バンドギャップを拡大する効果を有しうるSi(+2.4eV)の濃度が、半導体層の厚み方向の中央部において極大値を示すので、本願第1発明と同様に、光照射によるしきい値電流のシフト等の特性劣化が抑制されるという技術的効果も実現されうる。 In addition, when a semiconductor layer contains Si etc., it is preferable that the said semiconductor layer contains nitrogen further, and the density | concentration of nitrogen has shown the maximum value in the center part of the thickness direction of the said semiconductor layer. In this case, the concentration of Si 3 N 4 (+2.4 eV) that can have the effect of expanding the band gap in addition to the above-described effect on the nitrogen concentration distribution has a maximum value in the central portion in the thickness direction of the semiconductor layer. Therefore, as in the first invention of the present application, a technical effect that characteristic deterioration such as shift of threshold current due to light irradiation is suppressed can be realized.

 第2酸化物が金属酸化物である場合、本願第1~第3発明の半導体層への第2酸化物の添加は、従来公知の方法を採用することにより適宜実施できる。第2酸化物がボロン、炭素等の非金属元素の酸化物である場合も同様であるが、第1金属酸化物が酸化インジウム(In)である場合について、以下にその具体例を説明する。
 第1金属酸化物が酸化インジウム(In)であり、第2酸化物がボロン(B)酸化物である場合の酸化インジウムへのボロン酸化物の添加は、例えばイオンインプランテーションによって行うが、この添加方法では加速電圧を変えることで添加量および深さを制御できる。その含有量は0より大きく10重量%以下であることがより好ましい。なお、この場合、イオンインプランテーションはボロン酸化物ではなくボロンのイオンを第1金属酸化物に打ち込むことにより行われる。このボロンイオンは第1金属酸化物内でボロン酸化物となる。このように、第1金属酸化物内に酸化物を添加するに当たっては、添加処理操作自体では必ずしも酸化物その物を添加する必要はなく、例えば酸化物を構成する酸素以外の元素を添加する処理を行い、第1金属酸化物内部で酸化物とすることもできる。本願においては、このように添加処理操作の形態にかかわらず、第1金属酸化物内に酸化物の形で存在する形態で添加を行うことを「酸化物を添加する」と称する場合があることに注意されたい。
When the second oxide is a metal oxide, the addition of the second oxide to the semiconductor layers of the first to third inventions of the present application can be appropriately performed by employing a conventionally known method. The same applies to the case where the second oxide is an oxide of a nonmetallic element such as boron or carbon, but the specific example of the case where the first metal oxide is indium oxide (In 2 O 3 ) is described below. explain.
When the first metal oxide is indium oxide (In 2 O 3 ) and the second oxide is boron (B) oxide, the boron oxide is added to the indium oxide, for example, by ion implantation. In this addition method, the addition amount and depth can be controlled by changing the acceleration voltage. The content is more preferably greater than 0 and 10% by weight or less. In this case, ion implantation is performed by implanting boron ions instead of boron oxide into the first metal oxide. This boron ion becomes a boron oxide in the first metal oxide. As described above, when adding an oxide into the first metal oxide, it is not always necessary to add the oxide itself in the addition processing operation itself, for example, a process of adding an element other than oxygen constituting the oxide. The oxide can also be formed inside the first metal oxide. In the present application, regardless of the form of the addition treatment operation, the addition in the form of the oxide in the first metal oxide may be referred to as “adding the oxide”. Please be careful.

 また、第1金属酸化物が酸化インジウム(In)であり、第2酸化物が炭素(C)酸化物である場合の、酸化インジウムへの炭素酸化物添加は、例えばInターゲットおよびグラファイトターゲットを用いた共スパッタリング法により実施することが可能である。各々のスパッタリングパワーの比率を変えることで、炭素酸化物の添加量を制御でき、その含有量は0より大きく10重量%以下であることがより好ましい。 In addition, when the first metal oxide is indium oxide (In 2 O 3 ) and the second oxide is carbon (C) oxide, the addition of carbon oxide to indium oxide is, for example, In 2 O 3. It can be carried out by a co-sputtering method using a target and a graphite target. By changing the ratio of each sputtering power, the amount of carbon oxide added can be controlled, and the content is more preferably greater than 0 and not more than 10% by weight.

 なお、酸素のかい離エネルギーが第1金属酸化物より200kJ/mol以上大きな第2酸化物として、最初に説明した第2金属酸化物とここで説明した非金属の酸化物との両者を同時に使用した複合金属酸化物により半導体層50を形成することも可能である。また、本実施形態における第2酸化物の添加処理にあたって、処理の種類によっては複合金属酸化物でできた半導体層中に、第2金属酸化物、及び非金属の酸化物の両方の種類の第2酸化物が不可避的に共存することもあり得る。
 例えば、このような半導体層の薄膜をゾルゲル法などの溶液法で作製する場合には薄膜中に炭素が残留する可能性が高い。このような場合も本願第1~第3発明に包含されることに注意されたい。
As the second oxide having an oxygen separation energy of 200 kJ / mol or more higher than that of the first metal oxide, both the first metal oxide described first and the non-metal oxide described here were simultaneously used. It is also possible to form the semiconductor layer 50 with a composite metal oxide. In addition, in the second oxide addition process in the present embodiment, depending on the type of the process, the second metal oxide and the non-metal oxide of the second type are included in the semiconductor layer made of the composite metal oxide. Two oxides may inevitably coexist.
For example, when a thin film of such a semiconductor layer is manufactured by a solution method such as a sol-gel method, there is a high possibility that carbon remains in the thin film. It should be noted that such a case is also included in the first to third inventions of the present application.

(薄膜トランジスタの製造方法)
 次に、本実施形態の薄膜トランジスタ10の製造方法について説明する。本実施形態の薄膜トランジスタの半導体層を形成する方法には特に制限はないが、物理蒸着法(または物理気相成長法)を用いることにより形成することも可能である。
(Thin Film Transistor Manufacturing Method)
Next, a method for manufacturing the thin film transistor 10 of this embodiment will be described. Although there is no restriction | limiting in particular in the method of forming the semiconductor layer of the thin-film transistor of this embodiment, It is also possible to form by using a physical vapor deposition method (or physical vapor deposition method).

 ここで、物理蒸着法としては、蒸着法やスパッタ法などが挙げられる。蒸着法としては、真空蒸着法、分子線蒸着法(MBE)、イオンプレーティング法、イオンビーム蒸着法などを例示することができる。また、スパッタ法としては、コンベンショナル・スパッタリング、マグネトロン・スパッタリング、イオンビーム・スパッタリング、ECR(電子サイクロトロン共鳴)・スパッタリング、反応性スパッタリングなどを例示することができる。スパッタリング法においてプラズマを用いた場合は、反応性スパッタリング法、DC(直流)スパッタリング法、高周波(RF)スパッタリング法等の成膜法を用いることができる。 Here, examples of physical vapor deposition include vapor deposition and sputtering. Examples of the vapor deposition method include vacuum vapor deposition, molecular beam vapor deposition (MBE), ion plating, and ion beam vapor deposition. Examples of the sputtering method include conventional sputtering, magnetron sputtering, ion beam sputtering, ECR (electron cyclotron resonance) sputtering, and reactive sputtering. When plasma is used in the sputtering method, a film forming method such as a reactive sputtering method, a DC (direct current) sputtering method, or a radio frequency (RF) sputtering method can be used.

 さらには、下記の製造方法を用いて製造されたものが好ましい。下記の製造方法を用いると、より高品質な薄膜トランジスタを製造することができる。 Furthermore, those manufactured using the following manufacturing method are preferable. When the following manufacturing method is used, a higher quality thin film transistor can be manufactured.

 本実施形態の薄膜トランジスタ10の製造方法においては、基板20の上に通常知られた方法でゲート電極30および絶縁体層40を形成した後、半導体層50を形成する。本実施形態の製造方法では、半導体層50は、第1金属酸化物の粉末と、酸素のかい離エネルギーが第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物の粉末とを含む焼結体であるターゲットと、希ガスと酸素との混合ガスとを用いた物理蒸着法により製造される。ここでは、物理蒸着法としてスパッタリング法を用いることとして説明する。 In the method for manufacturing the thin film transistor 10 of the present embodiment, the gate electrode 30 and the insulator layer 40 are formed on the substrate 20 by a generally known method, and then the semiconductor layer 50 is formed. In the manufacturing method of the present embodiment, the semiconductor layer 50 includes the first metal oxide powder and the second oxide powder having an oxygen separation energy of 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide. Is produced by a physical vapor deposition method using a target that is a sintered body including a mixed gas of a rare gas and oxygen. Here, it demonstrates as using sputtering method as a physical vapor deposition method.

 例えば、半導体層50としてIn-Si-O系の金属酸化物を採用する場合には、ターゲットは、酸化インジウムの粉末と酸化ケイ素の粉末との焼結体を採用するとよい。また、ターゲットには、酸化ケイ素の重量%以下での添加物(金属酸化物など)等の不純物が混入していてもよい。例えば、ターゲットに、意図しない不純物として、酸化インジウムおよび酸化ケイ素以外の金属酸化物(酸化亜鉛など)が、ターゲット全体における酸化ケイ素含有量以下の割合(重量比)で混入することがあっても構わない。 For example, when an In—Si—O-based metal oxide is employed as the semiconductor layer 50, a sintered body of indium oxide powder and silicon oxide powder may be employed as the target. Further, the target may be mixed with impurities such as an additive (metal oxide or the like) at a weight percent or less of silicon oxide. For example, metal oxides (such as zinc oxide) other than indium oxide and silicon oxide may be mixed into the target at a ratio (weight ratio) equal to or lower than the silicon oxide content in the entire target as unintended impurities. Absent.

 その場合、焼結体に含まれる酸化ケイ素の含有量が、0重量%より多く50重量%以下であることが好ましい。また、酸化ケイ素の含有量は、0重量%より多く5重量%以下であることが、より好ましい。 In that case, the content of silicon oxide contained in the sintered body is preferably more than 0% by weight and 50% by weight or less. Moreover, it is more preferable that the content of silicon oxide is more than 0 wt% and not more than 5 wt%.

 通常知られた酸化物半導体であるIn-Zn-O系やIn-Ga-Zn-O系の金属酸化物では、酸化インジウムを「ホスト材料」、酸化亜鉛や酸化ガリウムを「ゲスト材料」とすると、ホスト材料(酸化インジウム)に対して、通常2割~3割のゲスト材料(酸化亜鉛や酸化ガリウム)が混入されている。 In In-Zn-O-based and In-Ga-Zn-O-based metal oxides, which are generally known oxide semiconductors, if indium oxide is the "host material" and zinc oxide or gallium oxide is the "guest material" In general, 20 to 30% of guest material (zinc oxide or gallium oxide) is mixed with the host material (indium oxide).

 これに対して、本実施形態の薄膜トランジスタ10の半導体層50は、上述のような焼結体をターゲットに用いて薄膜形成する。本実施形態の製造方法で製造された薄膜トランジスタ10においては上述したように酸化ケイ素の含有量は0重量%より多く5重量%以下であるとより好ましいので、この好ましい組成とした場合の半導体層50の酸化物半導体は、通常知られた酸化物半導体と比べて、ホスト材料(酸化インジウム)に対するゲスト材料(酸化ケイ素)の含有量が、極めて少ないものとすることも可能である。 On the other hand, the semiconductor layer 50 of the thin film transistor 10 of the present embodiment is formed into a thin film using the sintered body as described above as a target. In the thin film transistor 10 manufactured by the manufacturing method of this embodiment, as described above, the silicon oxide content is more preferably more than 0 wt% and 5 wt% or less. Therefore, the semiconductor layer 50 in this preferable composition is used. The oxide semiconductor can have an extremely small content of the guest material (silicon oxide) with respect to the host material (indium oxide) as compared with a conventionally known oxide semiconductor.

 また、薄膜トランジスタ10の製造方法においては、プロセスガスとして希ガスと酸素との混合ガスを用いてもよい。希ガスとしては、ヘリウム、ネオン、アルゴン、クリプトン、キセノンが挙げられる。また、プロセスガスには、水素原子を有する化合物を含まないことが好ましい。 In the method for manufacturing the thin film transistor 10, a mixed gas of a rare gas and oxygen may be used as a process gas. Examples of the rare gas include helium, neon, argon, krypton, and xenon. The process gas preferably does not contain a compound having a hydrogen atom.

 本実施形態の薄膜トランジスタの製造方法においては、発明者の検討により、酸化インジウムと酸化ケイ素とを含むターゲットを用いて半導体層を形成する場合、半導体層を構成する金属酸化物を非晶質膜とするために高温を必要としないことが分かっている。そのため、薄膜トランジスタの製造方法においては、半導体層を形成する工程を、10℃以上200℃以下で行うことで非晶質な半導体層を形成することができる。また、200℃より高く400℃以下で行うことで、結晶化した好適な半導体層を形成することもできる。さらには、半導体層を形成する工程を、室温で実施してもよい。ここで、「室温で実施」とは、半導体層を形成する工程のために非加熱であり、作業環境の温度調整が不要であることを意味する。 In the method for manufacturing a thin film transistor of this embodiment, according to the inventors' investigation, when a semiconductor layer is formed using a target containing indium oxide and silicon oxide, the metal oxide constituting the semiconductor layer is changed to an amorphous film. It has been found that it does not require high temperatures to do. Therefore, in the method for manufacturing a thin film transistor, an amorphous semiconductor layer can be formed by performing a step of forming a semiconductor layer at 10 ° C. or higher and 200 ° C. or lower. Further, by performing the treatment at a temperature higher than 200 ° C. and lower than or equal to 400 ° C., a suitable crystallized semiconductor layer can be formed. Further, the step of forming the semiconductor layer may be performed at room temperature. Here, “implemented at room temperature” means that the semiconductor layer is not heated for the step of forming the semiconductor layer, and the temperature adjustment of the working environment is unnecessary.

 本実施形態の薄膜トランジスタの製造方法において採用されるスパッタリング法としては、RFスパッタリングおよびDCスパッタリングなど公知のものを用いることができる。 As the sputtering method employed in the method for manufacturing the thin film transistor of the present embodiment, known methods such as RF sputtering and DC sputtering can be used.

 また、半導体層50としてIn-Si-O系の金属酸化物を採用する場合には、ターゲットは、酸化インジウムの粉末と、酸化ケイ素の粉末とを用いていればよく、これら粉末の混合物の焼結体であってもよく、それぞれの粉末の焼結体であってもよい。第2酸化物である酸化ケイ素の濃度分布の制御性の観点からは、後者が好ましい。この場合、複数の焼結体を用いた共スパッタリングにより半導体層を形成することができる。 When an In—Si—O-based metal oxide is used as the semiconductor layer 50, the target may be indium oxide powder and silicon oxide powder, and a mixture of these powders may be sintered. A sintered body of each powder may be sufficient. The latter is preferable from the viewpoint of controllability of the concentration distribution of silicon oxide as the second oxide. In this case, the semiconductor layer can be formed by co-sputtering using a plurality of sintered bodies.

 また、本願第1発明における元素Xの濃度分布、本願第2発明における元素Xの濃度分布も、共スパッタリングにより好適に制御することが可能である。例えば、元素Xがケイ素であり、元素XがSiである場合のIn-Si-Ti-O半導体層におけるSi及びTiの濃度分布は、In-Si-OターゲットとIn-Ti-Oターゲットとを用い、両ターゲットを同一チャンバーへ設置して、それぞれのターゲットについてのスパッタリングパワーを、好ましくは連続的に変化させることにより、適宜調整することができる。 The concentration distribution of elements X 1 in the first invention, the concentration distribution of elements X 2 in the present second invention also, it is possible to preferably control by co sputtering. For example, when the element X 1 is silicon and the element X 2 is Si, the concentration distribution of Si and Ti in the In—Si—Ti—O semiconductor layer is expressed by the In—Si—O target and the In—Ti—O target. And both targets are installed in the same chamber, and the sputtering power for each target is preferably adjusted by preferably changing continuously.

 第1金属酸化物として、酸化インジウムの代わりに、酸化亜鉛および酸化錫あるいは酸化インジウム、酸化ガリウム、酸化亜鉛および酸化錫を組み合わせた金属酸化物を用いた場合でも、上記と同様の方法を用いることで、酸素欠損量を制御し、かつ第2酸化物の濃度勾配を制御した半導体層を形成することができる。 The same method as described above should be used even when a metal oxide combining zinc oxide and tin oxide or indium oxide, gallium oxide, zinc oxide and tin oxide is used as the first metal oxide instead of indium oxide. Thus, a semiconductor layer in which the amount of oxygen vacancies is controlled and the concentration gradient of the second oxide is controlled can be formed.

 第2酸化物が酸化ケイ素である場合について説明したが、代わりに、酸化ジルコニウム(Zr-O)、酸化プラセオジム(Pr-O)、酸化ランタン(La-O)、酸化タンタル(Ta-O)、および酸化ハフニウム(Hf-O)のいずれかを用いた場合にも、それぞれの酸素のかい離エネルギーの大きさに対応したプロセス範囲で、半導体層を形成することができる。 The case where the second oxide is silicon oxide has been described, but instead, zirconium oxide (Zr—O), praseodymium oxide (Pr—O), lanthanum oxide (La—O), tantalum oxide (Ta—O), Even when any one of hafnium oxide (Hf—O) is used, the semiconductor layer can be formed in a process range corresponding to the magnitude of the separation energy of oxygen.

 以上のような図1に例示したような実施形態の薄膜トランジスタによれば、特定の酸化物の濃度分布を適切に制御した半導体層を用いることで、本願第1~第3発明の効果を適切に実現することが可能となり、光照射によるしきい値電流のシフト等の特性劣化が抑制され、ソース電極及び/又はドレイン電極と半導体層との界面におけるコンタクト抵抗が低く、かつ電子移動度が高くゲート制御性に優れるという、実用上好ましい特性を高いレベルで兼ね備えた薄膜トランジスタが提供される。 According to the thin film transistor of the embodiment as illustrated in FIG. 1 as described above, the effects of the first to third inventions of the present application are appropriately achieved by using the semiconductor layer in which the concentration distribution of the specific oxide is appropriately controlled. It is possible to realize a gate that suppresses deterioration of characteristics such as threshold current shift due to light irradiation, has low contact resistance at the interface between the source electrode and / or drain electrode and the semiconductor layer, and has high electron mobility. There is provided a thin film transistor having a practically preferable characteristic of excellent controllability at a high level.

 また、以上のような薄膜トランジスタの製造方法によれば、本願第1~第3発明の効果を適切に実現した薄膜トランジスタを容易にかつ効率よく製造することができる。 Further, according to the method for manufacturing a thin film transistor as described above, it is possible to easily and efficiently manufacture a thin film transistor in which the effects of the first to third inventions of the present application are appropriately realized.

なお、本実施形態においては、いわゆるボトムゲート型の薄膜トランジスタについて説明したが、本願第1~第3発明はいわゆるトップゲート型の薄膜トランジスタに適用することもできる。いわゆるトップゲート型の薄膜トランジスタの構成、製造方法等の詳細は、例えば特開2013-219936号公報に記載のように当業界において周知であり、これらに基づき当業者は過度の試行錯誤なしに、本願第1~第3発明をトップゲート型の態様において実施することが可能である。 Although the so-called bottom gate type thin film transistor has been described in this embodiment, the first to third inventions of the present application can also be applied to a so-called top gate type thin film transistor. Details of the structure and manufacturing method of a so-called top gate type thin film transistor are well known in the art as described in, for example, Japanese Patent Application Laid-Open No. 2013-219936, and based on these, those skilled in the art can apply the present application without undue trial and error. The first to third inventions can be implemented in a top gate type embodiment.

 また、本実施形態においては、いわゆるトップコンタクト型の薄膜トランジスタについて説明したが、本願第1~第3発明はいわゆるボトムコンタクト型の薄膜トランジスタに適用することもできる。いわゆるボトムコンタクト型の薄膜トランジスタの構成、製造方法等の詳細も当業界において周知であり、当業者は過度の試行錯誤なしに、本願第1~第3発明をボトムコンタクト型の態様において実施することが可能である。 In this embodiment, a so-called top contact type thin film transistor has been described. However, the first to third inventions of the present application can also be applied to a so-called bottom contact type thin film transistor. Details of the structure and manufacturing method of so-called bottom contact type thin film transistors are also well known in the art, and those skilled in the art can implement the first to third aspects of the present invention in a bottom contact type mode without undue trial and error. Is possible.

 以上、添付図面を参照しながら本願第1~第3発明に係る好適な実施の形態例について説明したが、本願第1~第3発明は斯かる例に限定されないことは言うまでもない。上述した例において示した各構成部材の諸形状や組み合わせ等は一例であって、本願第1~第3発明の主旨から逸脱しない範囲において設計要求等に基づき種々変更可能である。 The preferred embodiments according to the first to third inventions of the present application have been described above with reference to the accompanying drawings. Needless to say, the first to third inventions of the present application are not limited to such examples. The various shapes and combinations of the constituent members shown in the above-described examples are merely examples, and various modifications can be made based on design requirements and the like without departing from the spirit of the first to third inventions of the present application.

 次に、以下、図を参照しながら、本願第4発明の実施形態に係る薄膜トランジスタおよび薄膜トランジスタの製造方法について説明する。なお、以下の全ての図面においては、図面を見やすくするため、各構成要素の寸法や比率などは適宜異ならせてある。 Next, a thin film transistor and a method for manufacturing the thin film transistor according to the fourth embodiment of the present invention will be described below with reference to the drawings. In all the drawings below, the dimensions and ratios of the constituent elements are appropriately changed in order to make the drawings easy to see.

 本願第4発明は、酸素のかい離エネルギーが528kJ/molと大きな酸化錫を電子キャリアを生成する酸化物として用いた場合、添加する金属酸化物についての酸素のかい離エネルギーが酸化錫についての酸素のかい離エネルギーより大きく、かつ酸化錫についての酸素のかい離エネルギーとの差が200kJ/mol未満であるようにすれば上記の問題の酸素欠損の量を制御できるという、本発明者らの新たな知見に基づき、第1の実施形態の薄膜トランジスタおよびその製造方法を提供する。 In the fourth invention of the present application, when tin oxide having a large oxygen separation energy of 528 kJ / mol is used as an oxide for generating an electron carrier, the oxygen separation energy of the metal oxide to be added is the oxygen separation energy of the tin oxide. Based on the new knowledge of the present inventors that the amount of oxygen deficiency in the above problem can be controlled by making the difference from the energy of separation of oxygen with respect to tin oxide less than 200 kJ / mol. The thin film transistor of the first embodiment and the manufacturing method thereof are provided.

 また、本発明者らは上記の金属酸化物に加えて、酸素のかい離エネルギーが酸化錫より小さな追加の酸化物を更に添加し、かつその添加量が上記の金属酸化物の添加量より少なければ、酸素欠損の量を制御できる上に、非晶質の安定形成温度領域を拡大できることを見出した。本願第4発明は、この知見に基づいた第2の実施形態の薄膜トランジスタおよびその製造方法も提供する。 In addition to the above metal oxides, the present inventors further add an additional oxide whose oxygen separation energy is smaller than that of tin oxide, and the addition amount is less than the addition amount of the above metal oxide. The present inventors have found that the amount of oxygen vacancies can be controlled and the amorphous stable formation temperature range can be expanded. The fourth invention of the present application also provides a thin film transistor and a manufacturing method thereof according to the second embodiment based on this finding.

[薄膜トランジスタの構造]
 第1の実施形態の薄膜トランジスタは、ソース電極およびドレイン電極と、前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、前記ゲート電極と前記半導体層との間に設けられた絶縁体層とを設け、前記半導体層が、酸化錫に、酸素のかい離エネルギーが酸化錫の酸素のかい離エネルギーより大きく、酸化錫についての酸素のかい離エネルギーの差とが200kJ/molより小さい金属酸化物を添加した複合金属酸化物である。
[Structure of thin film transistor]
The thin film transistor of the first embodiment is provided corresponding to a source electrode and a drain electrode, a semiconductor layer provided in contact with the source electrode and the drain electrode, and a channel between the source electrode and the drain electrode. A gate electrode, and an insulator layer provided between the gate electrode and the semiconductor layer, wherein the semiconductor layer is tin oxide, and the oxygen separation energy of the tin oxide is greater than the oxygen separation energy of the tin oxide, This is a composite metal oxide to which a metal oxide having a difference in oxygen separation energy of tin oxide of less than 200 kJ / mol is added.

 また、第2の実施形態の薄膜トランジスタでは、第1の実施形態の薄膜トランジスタの前記半導体層が、更に、酸素のかい離エネルギーが酸化錫より小さく、かつ添加量が上記の金属酸化物より少ない追加の酸化物を添加した複合金属酸化物である。 Further, in the thin film transistor of the second embodiment, the semiconductor layer of the thin film transistor of the first embodiment further includes an additional oxidation in which the oxygen separation energy is smaller than that of tin oxide and the addition amount is smaller than that of the above metal oxide. It is a composite metal oxide to which a product is added.

 また、本実施形態の薄膜トランジスタの製造方法は、上記薄膜トランジスタを製造するに当たって、前記半導体層を10℃以上500℃以下で形成する工程を有するものである。 In addition, the method for manufacturing a thin film transistor of this embodiment includes a step of forming the semiconductor layer at 10 ° C. or higher and 500 ° C. or lower when manufacturing the thin film transistor.

 図8は第1の実施形態に係る薄膜トランジスタ201の概略断面図である。基板202は、公知の形成材料で形成されたものを用いることができ、光透過性を有するもの及び光透過性を有しないもののいずれも用いることができる。例えば、ケイ酸アルカリ系ガラス、石英ガラス、窒化ケイ素などを形成材料とする無機基板;シリコン基板;表面が絶縁処理された金属基板;アクリル樹脂、ポリカーボネート樹脂、PET(ポリエチレンテレフタレート)やPBT(ポリブチレンテレフタレート)などのポリエステル樹脂などを形成材料とする樹脂基板;紙製の基板などの種々のものを用いることができる。また、これらの材料を複数組み合わせた複合材料を形成材料とする基板であっても構わない。基板202の厚さは、設計に応じて適宜設定することができる。 FIG. 8 is a schematic cross-sectional view of the thin film transistor 201 according to the first embodiment. As the substrate 202, a substrate formed using a known forming material can be used, and any of those having light transmittance and those having no light transmittance can be used. For example, an inorganic substrate made of alkali silicate glass, quartz glass, silicon nitride, or the like; a silicon substrate; a metal substrate whose surface is insulated; acrylic resin, polycarbonate resin, PET (polyethylene terephthalate), or PBT (polybutylene) Various substrates such as a resin substrate made of a polyester resin such as terephthalate) or a paper substrate can be used. Further, the substrate may be a composite material formed by combining a plurality of these materials. The thickness of the substrate 202 can be appropriately set according to the design.

 薄膜トランジスタ201は、いわゆるボトムゲート型のトランジスタである。薄膜トランジスタ201は、基板202上に設けられたゲート電極203と、ゲート電極203を覆って設けられた絶縁体層204と、絶縁体層204の上面に設けられた半導体層205と、半導体層205の上面において半導体層205に接して設けられたソース電極208およびドレイン電極209を有している。ゲート電極203は、半導体層205のチャネル領域に対応させて(チャネル領域と平面的に重なる位置に)設けられている。また、半導体層205は、酸化錫206へ金属酸化物207を添加した複合金属酸化物から構成されている。なお、当然のことであるが、本願第4発明の作用効果にはなはだしい悪影響が出ない限り、半導体層に金属酸化物207以外の成分や不可避の不純物が含まれていてもよい。これについては以下で記述されている他の実施形態で説明する非金属元素の酸化物の添加を行う場合でも同じである。また、図8では図示のしやすさの都合上、半導体層205(複合金属酸化物)は酸化錫206の中に金属酸化物207の粒子が散在しているようにも見ることができる形態で描画されているが、実際には酸化錫中に金属酸化物が一様に添加、つまりドーピングされることで、複合金属酸化物は一様な物質となっていることに注意されたい。 The thin film transistor 201 is a so-called bottom gate type transistor. The thin film transistor 201 includes a gate electrode 203 provided over a substrate 202, an insulator layer 204 provided to cover the gate electrode 203, a semiconductor layer 205 provided on the top surface of the insulator layer 204, A source electrode 208 and a drain electrode 209 are provided in contact with the semiconductor layer 205 on the upper surface. The gate electrode 203 is provided so as to correspond to the channel region of the semiconductor layer 205 (at a position overlapping the channel region in plan view). The semiconductor layer 205 is composed of a composite metal oxide obtained by adding a metal oxide 207 to tin oxide 206. As a matter of course, the semiconductor layer may contain components other than the metal oxide 207 and inevitable impurities as long as the adverse effects of the fourth invention of the present application are not adversely affected. The same applies to the case of adding an oxide of a non-metallic element described in other embodiments described below. Further, in FIG. 8, for convenience of illustration, the semiconductor layer 205 (composite metal oxide) can be seen as if particles of the metal oxide 207 are scattered in the tin oxide 206. Although drawn, it should be noted that the metal oxide is actually uniformly added to the tin oxide, that is, doped, so that the composite metal oxide becomes a uniform material.

 ゲート電極203、ソース電極208、ドレイン電極209は、通常知られた材料で形成されたものを用いることができる。これらの電極の形成材料としては、例えば、アルミニウム(Al)、金(Au)、銀(Ag)、銅(Cu)、ニッケル(Ni)、モリブデン(Mo)、タンタル(Ta)、タングステン(W)などの金属材料やこれらの合金、インジウムスズ酸化物(Indium Tin Oxide、ITO)、酸化亜鉛(ZnO)などの導電性酸化物を挙げることができる。また、これらの電極は、例えば表面を金属材料でめっきすることにより2層以上の積層構造を形成していてもよい。 As the gate electrode 203, the source electrode 208, and the drain electrode 209, those formed of a generally known material can be used. Examples of the material for forming these electrodes include aluminum (Al), gold (Au), silver (Ag), copper (Cu), nickel (Ni), molybdenum (Mo), tantalum (Ta), and tungsten (W). Examples thereof include metal materials such as these, alloys thereof, and conductive oxides such as indium tin oxide (ITO) and zinc oxide (ZnO). Moreover, these electrodes may form the laminated structure of two or more layers, for example by plating the surface with a metal material.

 ゲート電極203、ソース電極208、ドレイン電極209は、同じ形成材料で形成されたものであってもよく、異なる形成材料で形成されたものであってもよい。製造が容易となることから、ソース電極208とドレイン電極209とは同じ形成材料であることが好ましい。 The gate electrode 203, the source electrode 208, and the drain electrode 209 may be formed of the same forming material, or may be formed of different forming materials. The source electrode 208 and the drain electrode 209 are preferably made of the same material since manufacturing is easy.

 絶縁体層204は、絶縁性を有し、ゲート電極203と、ソース電極208およびドレイン電極209との間を電気的に絶縁することが可能であれば、無機材料および有機材料のいずれを用いて形成してもよい。無機材料としては、例えばSiO、SiN、SiON、Al、HfOなどの通常知られた絶縁性の酸化物、窒化物、酸窒化物を挙げることができる。有機材料としては、例えば、アクリル樹脂、エポキシ樹脂、シリコン樹脂、フッ素系樹脂などを挙げることができる。有機材料としては、製造や加工が容易であることから、光硬化型の樹脂材料であることが好ましい。 The insulator layer 204 has an insulating property, and can be formed using either an inorganic material or an organic material as long as the gate electrode 203 can be electrically insulated from the source electrode 208 and the drain electrode 209. It may be formed. Examples of the inorganic material include normally known insulating oxides such as SiO 2 , SiN x , SiON, Al 2 O 3 , and HfO 2 , nitrides, and oxynitrides. Examples of the organic material include acrylic resin, epoxy resin, silicon resin, and fluorine resin. The organic material is preferably a photocurable resin material because it is easy to manufacture and process.

 半導体層205は、酸化錫に、酸素の解離エネルギーが酸化錫の酸素のかい離エネルギーより大きくかつ両者のかい離エネルギーの差が200kJ/molよりも小さい金属酸化物を添加したものである。 The semiconductor layer 205 is obtained by adding, to tin oxide, a metal oxide in which the dissociation energy of oxygen is larger than the separation energy of oxygen in tin oxide and the difference in separation energy between the two is smaller than 200 kJ / mol.

 本願第4発明では上述した本発明者らの先行出願における第1金属酸化物として酸化錫(SnO)を用いるが、酸化錫の酸素のかい離エネルギーは528kJ/molと小さいので、酸化錫から酸素が容易に脱離して酸素欠損を生成しやすい。しかし、酸素欠損量が大きくなりすぎると半導体的な性質から金属的な性質へ変わって半導体層として適さなくなる。本願発明者らはこの問題を解決すべく検討を重ねた結果、酸化錫の酸素欠損量を制御するためには酸化錫の酸素のかい離エネルギーより大きな酸素のかい離エネルギーを有する金属酸化物を添加すればよいことを見出した。添加できる金属酸化物としては、具体的には、酸素かい離エネルギーが573kJ/molの酸化サマリウム、720kJ/molの酸化タングステン、703kJ/molの酸化ネオジウム、715KJ/molの酸化ガドリウム等が挙げられる。 In the fourth invention of the present application, tin oxide (SnO 2 ) is used as the first metal oxide in the above-mentioned prior application of the present inventors. However, since the separation energy of oxygen of tin oxide is as small as 528 kJ / mol, oxygen from tin oxide is reduced. Easily desorbs and easily generates oxygen deficiency. However, if the amount of oxygen vacancies becomes too large, it changes from semiconducting properties to metallic properties, making it unsuitable as a semiconductor layer. As a result of repeated studies to solve this problem, the inventors of the present application added a metal oxide having an oxygen separation energy larger than that of tin oxide in order to control the oxygen deficiency of tin oxide. I found out that I should do it. Specific examples of the metal oxide that can be added include samarium oxide having an oxygen separation energy of 573 kJ / mol, tungsten oxide of 720 kJ / mol, neodymium oxide of 703 kJ / mol, and gadolinium oxide of 715 KJ / mol.

 また、酸化錫を適切な酸素欠損量を有する半導体層とするために添加する金属酸化物の含有量としては、0より大きく50重量%以下の範囲にするとよい。特に、酸化錫へ添加する金属酸化物の含有量を0より大きく5重量%以下の範囲にすると、半導体層を300℃以下の低温度で作製できる。 Also, the content of the metal oxide added to make tin oxide a semiconductor layer having an appropriate oxygen deficiency is preferably in the range of greater than 0 to 50% by weight. In particular, when the content of the metal oxide added to the tin oxide is in the range of more than 0 to 5% by weight or less, the semiconductor layer can be manufactured at a low temperature of 300 ° C. or less.

 In-Zn-O系やIn-Ga-Zn-O系の金属酸化物では、半導体層の形成時に多結晶状になりやすい。そのため、通常知られた薄膜トランジスタでは、半導体層に含まれる結晶粒に起因して、半導体層の表面が平坦にはならない。また、通常知られた酸化膜トランジスタの半導体層は、このような結晶粒に起因して、面方向の電気伝導度が低下してしまう。したがって、半導体層の表面の平坦化及び高い電気伝導度を得るためには、半導体層は非晶質構造であることが好ましい。 In-Zn-O-based and In-Ga-Zn-O-based metal oxides tend to be polycrystalline when a semiconductor layer is formed. Therefore, in a generally known thin film transistor, the surface of the semiconductor layer does not become flat due to crystal grains contained in the semiconductor layer. In addition, the normally known semiconductor layer of an oxide film transistor has a reduced electrical conductivity in the plane direction due to such crystal grains. Therefore, in order to obtain planarization of the surface of the semiconductor layer and high electrical conductivity, the semiconductor layer preferably has an amorphous structure.

 また、半導体層205の厚みは、5nm以上かつ20nm以下の範囲であることがより好ましい。なお、本実施形態において、半導体層205の厚さは、半導体層205を形成したスパッタチャンバー内に、膜厚校正を主目的として配置された水晶発振式膜厚計を用いて測定した。 The thickness of the semiconductor layer 205 is more preferably in the range of 5 nm to 20 nm. In the present embodiment, the thickness of the semiconductor layer 205 was measured using a crystal oscillation type film thickness meter disposed mainly for film thickness calibration in the sputtering chamber in which the semiconductor layer 205 was formed.

 本願第4発明の第2の実施形態においては、半導体層205を構成する複合金属酸化物は、酸化錫に上述した金属酸化物を添加したものに、更に酸素のかい離エネルギーが酸化錫より小さく、かつ添加量が金属酸化物より少ない追加の酸化物を添加したものである。本願発明者らは、金属酸化物の添加によって酸素欠損量を制御した上に、追加の酸化物を添加することで、半導体層が500℃の高温度域でも非晶質することを見出した。追加の酸化物としては、具体的には、酸素かい離エネルギーが382.4±3.3kJ/molの酸化鉛、238.1±12.6kJ/molの酸化パラジウム、418.6±11.6kJ/molの酸化白金、517.90±0.05kJ/molの酸化硫黄、434±42kJ/molの酸化アンチモン、426.3±6.3kJ/molの酸化ストロンチウム、213±84kJ/molの酸化タリウム、387.7±10kJ/molの酸化イッテルビウム等が挙げられる。 In the second embodiment of the fourth invention of the present application, the composite metal oxide constituting the semiconductor layer 205 is obtained by adding the above-described metal oxide to tin oxide, and further having an oxygen separation energy smaller than that of tin oxide. In addition, an additional oxide having an addition amount smaller than that of the metal oxide is added. The inventors of the present application have found that the semiconductor layer becomes amorphous even in a high temperature range of 500 ° C. by controlling the amount of oxygen vacancies by adding a metal oxide and adding an additional oxide. As the additional oxide, specifically, lead oxide having an oxygen release energy of 382.4 ± 3.3 kJ / mol, palladium oxide having 238.1 ± 12.6 kJ / mol, 418.6 ± 11.6 kJ / mol mol platinum oxide, 517.90 ± 0.05 kJ / mol sulfur oxide, 434 ± 42 kJ / mol antimony oxide, 426.3 ± 6.3 kJ / mol strontium oxide, 213 ± 84 kJ / mol thallium oxide, 387 7 ± 10 kJ / mol ytterbium oxide and the like.

 図9に示す本願第4発明の第2の実施形態の薄膜トランジスタ201’は図8の薄膜トランジスタ201と基本的には同一構造であるが、図8の半導体層205に対応する半導体層205’が酸化錫206に金属酸化物207を添加したものに、更に酸素のかい離エネルギーが酸化錫より小さく、かつ添加量が金属酸化物より少ない追加の酸化物210を添加した複合金属酸化物である点が異なる。なお、図9中で図8中の要素と同じ参照番号が付されているものは対応する図8中の要素と同じであるため、それらについては説明を省略する。 The thin film transistor 201 ′ of the second embodiment of the present invention shown in FIG. 9 has basically the same structure as the thin film transistor 201 of FIG. 8, but the semiconductor layer 205 ′ corresponding to the semiconductor layer 205 of FIG. It is a composite metal oxide in which the metal oxide 207 is added to the tin 206, and an additional oxide 210 in which the oxygen separation energy is smaller than that of the tin oxide and the addition amount is smaller than that of the metal oxide. . 9 that have the same reference numerals as the elements in FIG. 8 are the same as the corresponding elements in FIG. 8, and therefore, the description thereof is omitted.

 なお、第1の実施の形態の説明において図8を参照して注記したように、図9においても図示のしやすさの都合上、半導体層205’(複合金属酸化物)は酸化錫206の中に追加の酸化物210が散在しているようにも見ることができる形態で描画されているが、ここにおいても実際には酸化錫中にこれら酸化物が一様に添加、つまりドーピングされることで、複合金属酸化物は一様な物質となっていることに注意されたい。 As noted in the description of the first embodiment with reference to FIG. 8, the semiconductor layer 205 ′ (composite metal oxide) is made of tin oxide 206 for convenience of illustration also in FIG. 9. It is drawn in a form that can be seen as interspersed with additional oxides 210, but here again, these oxides are actually uniformly added or doped in the tin oxide. Therefore, it should be noted that the composite metal oxide is a uniform material.

 酸化錫(SnO)への、金属酸化物の酸化タングステン(WO)、追加の酸化物の酸化イッテルビウム(Yb)の添加は、例えば、スパッタリング法のターゲット作製段階で行う。 The addition of the metal oxide tungsten oxide (WO 3 ) and the additional oxide ytterbium oxide (Yb 2 O 3 ) to the tin oxide (SnO 2 ) is performed, for example, at the target preparation stage of the sputtering method.

 また、また、Sn-W-OターゲットおよびYbターゲットを用いた共スパッタリング法により、各々スパッタリングパワーの比率を変えることで、添加量を制御でき、その含有量は0より大きく10重量%以下であることがより好ましい。 In addition, the addition amount can be controlled by changing the ratio of sputtering power by co-sputtering method using Sn—W—O target and Yb 2 O 3 target, and the content is larger than 0 and 10% by weight. The following is more preferable.

[薄膜トランジスタの製造方法]
 次に、第1の実施形態の薄膜トランジスタ201の製造方法について説明する。本実施形態の薄膜トランジスタの半導体層は、物理蒸着法(または物理気相成長法)を用いることにより形成することも可能である。
[Thin Film Transistor Manufacturing Method]
Next, a method for manufacturing the thin film transistor 201 according to the first embodiment will be described. The semiconductor layer of the thin film transistor of this embodiment can also be formed by using physical vapor deposition (or physical vapor deposition).

 ここで、物理蒸着法としては、蒸着法やスパッタ法が挙げられる。蒸着法としては、真空蒸着法、分子線蒸着法(MBE)、イオンプレーティング法、イオンビーム蒸着法などを例示することができる。また、スパッタ法としては、コンベンショナル・スパッタリング、マグネトロン・スパッタリング、イオンビーム・スパッタリング、ECR(電子サイクロトロン共鳴)・スパッタリング、反応性スパッタリングなどを例示することができる。スパッタリング法においてプラズマを用いた場合は、反応性スパッタリング法、DC(直流)スパッタリング法、高周波(RF)スパッタリング法等の成膜法を用いることができる。 Here, examples of physical vapor deposition include vapor deposition and sputtering. Examples of the vapor deposition method include vacuum vapor deposition, molecular beam vapor deposition (MBE), ion plating, and ion beam vapor deposition. Examples of the sputtering method include conventional sputtering, magnetron sputtering, ion beam sputtering, ECR (electron cyclotron resonance) sputtering, and reactive sputtering. When plasma is used in the sputtering method, a film forming method such as a reactive sputtering method, a DC (direct current) sputtering method, or a radio frequency (RF) sputtering method can be used.

さらには、下記の製造方法を用いて製造されたものが好ましい。下記の製造方法を用いると、より高品質な薄膜トランジスタを製造することができる。 Furthermore, what was manufactured using the following manufacturing method is preferable. When the following manufacturing method is used, a higher quality thin film transistor can be manufactured.

 本実施形態の薄膜トランジスタ201の製造方法においては、基板202の上に通常知られた方法でゲート電極203および絶縁体層204を形成した後、半導体層205を形成する。本実施形態の製造方法では、半導体層205は、酸化錫の粉末と、酸素のかい離エネルギーが酸化錫の酸素のかい離エネルギーよりも大きい金属酸化物であって酸化錫と当該金属酸化物についての酸素のかい離エネルギーの差が200kJ/mol未満であるものの粉末とを含む焼結体であるターゲットと、希ガスと酸素との混合ガスとを用いた物理蒸着法により製造される。ここでは、物理蒸着法としてスパッタリング法を用いることとして説明する。 In the method for manufacturing the thin film transistor 201 of this embodiment, the gate electrode 203 and the insulator layer 204 are formed on the substrate 202 by a generally known method, and then the semiconductor layer 205 is formed. In the manufacturing method according to the present embodiment, the semiconductor layer 205 includes a tin oxide powder and a metal oxide having an oxygen separation energy larger than that of the tin oxide, and the oxygen of the tin oxide and the metal oxide. It is manufactured by a physical vapor deposition method using a target which is a sintered body containing a powder having a difference in separation energy of less than 200 kJ / mol and a mixed gas of a rare gas and oxygen. Here, it demonstrates as using sputtering method as a physical vapor deposition method.

 例えば、半導体層205としてSn-W-O系の金属酸化物を採用する場合には、ターゲットは、酸化錫の粉末と酸化タングステンの粉末との焼結体を採用するとよい。また、ターゲットには、酸化タングステンの質量%以下での添加物(金属酸化物など)等の不純物が混入していてもよい。例えば、ターゲットに、意図しない不純物として酸化錫および酸化タングステン以外の金属酸化物(酸化亜鉛など)が、ターゲット全体における酸化タングステン含有量以下の割合(重量比)で混入することがあっても構わない。 For example, in the case where an Sn—W—O-based metal oxide is employed as the semiconductor layer 205, a sintered body of a tin oxide powder and a tungsten oxide powder may be employed as the target. Further, the target may be mixed with impurities such as an additive (metal oxide or the like) at a mass% or less of tungsten oxide. For example, a metal oxide (such as zinc oxide) other than tin oxide and tungsten oxide may be mixed into the target at a ratio (weight ratio) equal to or lower than the tungsten oxide content in the target as an unintended impurity. .

 その場合、焼結体に含まれる酸化タングステンの含有量が、0質量%より多く50質量%以下であるとよい。また、酸化タングステンの含有量は、0質量%より多く5質量%以下であるとより好ましい。 In that case, the content of tungsten oxide contained in the sintered body is preferably more than 0 mass% and 50 mass% or less. Further, the content of tungsten oxide is more preferably 0% by mass to 5% by mass.

 通常知られた酸化物半導体であるIn-Zn-O系やIn-Ga-Zn-O系の金属酸化物では、酸化インジウムを「ホスト材料」、酸化亜鉛や酸化ガリウムを「ゲスト材料」とすると、ホスト材料(酸化インジウム)に対して、2割~3割のゲスト材料(酸化亜鉛や酸化ガリウム)が混入されている。 In In-Zn-O-based and In-Ga-Zn-O-based metal oxides, which are generally known oxide semiconductors, if indium oxide is the "host material" and zinc oxide or gallium oxide is the "guest material" The guest material (zinc oxide or gallium oxide) is mixed with 20-30% of the host material (indium oxide).

 これに対して、本実施形態の薄膜トランジスタ201の半導体層205は、上述のような焼結体をターゲットに用いて薄膜形成する。本実施形態の製造方法で製造された薄膜トランジスタ201においては上述したように酸化タングステンの含有量は0質量%より多く5質量%以下であるとより好ましいので、この好ましい組成とした場合の半導体層205の酸化物半導体は、通常知られた酸化物半導体と比べて、ホスト材料(酸化錫)に対するゲスト材料(酸化タングステン)の含有量が、極めて少ないものとなる。 On the other hand, the semiconductor layer 205 of the thin film transistor 201 of the present embodiment is formed into a thin film using the sintered body as described above as a target. In the thin film transistor 201 manufactured by the manufacturing method of this embodiment, as described above, the content of tungsten oxide is more preferably 0% by mass to 5% by mass, and thus the semiconductor layer 205 in the case of this preferable composition. This oxide semiconductor has an extremely small content of the guest material (tungsten oxide) with respect to the host material (tin oxide) as compared with a conventionally known oxide semiconductor.

 また、薄膜トランジスタ201の製造方法においては、プロセスガスとして希ガスと酸素との混合ガスを用いる。希ガスとしては、ヘリウム、ネオン、アルゴン、クリプトン、キセノンが挙げられる。また、プロセスガスには、水素原子を有する化合物を含まない。 In the method for manufacturing the thin film transistor 201, a mixed gas of a rare gas and oxygen is used as a process gas. Examples of the rare gas include helium, neon, argon, krypton, and xenon. Further, the process gas does not include a compound having a hydrogen atom.

 本実施形態の薄膜トランジスタの製造方法においては、発明者の検討により、酸化錫と酸化タングステンとを含むターゲットを用いて半導体層を形成する場合、半導体層を構成する金属酸化物を非晶質膜とするために高温を必要としないことが分かっている。そのため、薄膜トランジスタの製造方法においては、半導体層を形成する工程を、10℃以上300℃以下で行うことで非晶質な半導体層を形成することができる。また、当該工程を300℃より高く500℃以下で行うことで、結晶化した好適な半導体層を形成することもできる。さらには、半導体層を形成する工程を、室温で実施するとよい。ここで、「室温で実施」とは、半導体層を形成する工程のために非加熱であり、作業環境の温度調整が不要であることを意味する。 In the thin film transistor manufacturing method of this embodiment, when the semiconductor layer is formed using a target containing tin oxide and tungsten oxide, the metal oxide constituting the semiconductor layer is changed to an amorphous film. It has been found that it does not require high temperatures to do. Therefore, in a method for manufacturing a thin film transistor, an amorphous semiconductor layer can be formed by performing a step of forming a semiconductor layer at 10 ° C. to 300 ° C. In addition, a suitable crystallized semiconductor layer can be formed by performing the process at a temperature higher than 300 ° C. and lower than or equal to 500 ° C. Further, the step of forming the semiconductor layer is preferably performed at room temperature. Here, “implemented at room temperature” means that the semiconductor layer is not heated for the step of forming the semiconductor layer, and the temperature adjustment of the working environment is unnecessary.

 本実施形態の薄膜トランジスタの製造方法において採用されるスパッタリング法としては、RFスパッタリングおよびDCスパッタリングなど公知のものを用いることができる。 As the sputtering method employed in the method for manufacturing the thin film transistor of the present embodiment, known methods such as RF sputtering and DC sputtering can be used.

 また、ターゲットは、酸化錫の粉末と、酸化タングステンの粉末とを用いていれば、これら粉末の混合物の焼結体であってもよく、それぞれの粉末の焼結体であってもよい。それぞれの金属酸化物の粉末毎に焼結体を形成する場合には、複数の焼結体を用いた共スパッタリングにより半導体層を形成することができる。 Further, the target may be a sintered body of a mixture of these powders or a sintered body of each powder as long as tin oxide powder and tungsten oxide powder are used. When a sintered body is formed for each metal oxide powder, the semiconductor layer can be formed by co-sputtering using a plurality of sintered bodies.

 金属酸化物として、酸化シリコンについて説明したが、代わりに、酸化サマリウム(Sm-O)、酸化タングステン(W-O)、酸化ネオジウム(Nd-O)、および酸化ガドリウム(Gd-O)を用いた場合にも、それぞれの酸素のかい離エネルギーの大きさに対応したプロセス範囲で、半導体層を形成することができる。 Although silicon oxide has been described as the metal oxide, samarium oxide (Sm—O), tungsten oxide (W—O), neodymium oxide (Nd—O), and gadolinium oxide (Gd—O) were used instead. Even in this case, the semiconductor layer can be formed in a process range corresponding to the magnitude of the separation energy of oxygen.

 また、第2の本実施形態の薄膜トランジスタ201の製造方法においては、基板202の上に通常知られた方法でゲート電極203および絶縁体層204を形成した後、半導体層205を形成する。本実施形態の製造方法では、半導体層205は、酸化錫の粉末と、酸素のかい離エネルギーが酸化錫についての酸素のかい離エネルギーよりも大きく、かつ酸化錫についての酸素のかい離エネルギーとの差が200kJ/mol未満である酸素のかい離エネルギーを有する金属酸化物の粉末と、酸素のかい離エネルギーが酸化錫についての酸素のかい離エネルギーより小さく、かつ金属酸化物の添加量より少ない量の追加の酸化物とを含む焼結体であるターゲットと、希ガスと酸素との混合ガスとを用いた物理蒸着法により製造される。ここでは、物理蒸着法としてスパッタリング法を用いることとして説明する。 In the method for manufacturing the thin film transistor 201 of the second embodiment, the semiconductor layer 205 is formed after the gate electrode 203 and the insulator layer 204 are formed on the substrate 202 by a generally known method. In the manufacturing method according to the present embodiment, the semiconductor layer 205 has a difference of 200 kJ between the tin oxide powder and the oxygen separation energy of the tin oxide, and the oxygen separation energy of the tin oxide is 200 kJ. A metal oxide powder having an oxygen separation energy of less than / mol, and an additional oxide in an amount where the oxygen separation energy is less than the oxygen separation energy for tin oxide and less than the addition amount of the metal oxide Is produced by a physical vapor deposition method using a target that is a sintered body containing a noble gas and a mixed gas of oxygen and oxygen. Here, it demonstrates as using sputtering method as a physical vapor deposition method.

 例えば、半導体層205としてSn-W-Yb-O系の金属酸化物を採用する場合には、ターゲットは、酸化錫の粉末と酸化タングステンと酸化イッテルビウムの粉末との焼結体を採用するとよい。また、ターゲットには、酸化イッテルビウムの添加量は酸化タングステンの添加量より必ず小さい。 For example, in the case where a Sn—W—Yb—O-based metal oxide is used as the semiconductor layer 205, a target may be a sintered body of a tin oxide powder, a tungsten oxide powder, and a ytterbium oxide powder. Further, the amount of ytterbium oxide added to the target is always smaller than the amount of tungsten oxide added.

 その場合、焼結体に含まれる酸化タングステンの含有量が、0質量%より多く50質量%以下である場合、酸化イッテルビウムの含有量は、0質量%より多く20質量%より小さくなる。また、酸化イッテルビウムの含有量は、0質量%より多く4質量%であるとより好ましい。 In that case, when the content of tungsten oxide contained in the sintered body is more than 0% by mass and 50% by mass or less, the content of ytterbium oxide is more than 0% by mass and less than 20% by mass. The content of ytterbium oxide is more preferably 0% by mass to 4% by mass.

 また、薄膜トランジスタ201の製造方法においては、プロセスガスとして希ガスと酸素との混合ガスを用いる。希ガスとしては、ヘリウム、ネオン、アルゴン、クリプトン、キセノンが挙げられる。また、プロセスガスには、水素原子を有する化合物を含まない。 In the method for manufacturing the thin film transistor 201, a mixed gas of a rare gas and oxygen is used as a process gas. Examples of the rare gas include helium, neon, argon, krypton, and xenon. Further, the process gas does not include a compound having a hydrogen atom.

 本実施形態の薄膜トランジスタの製造方法においては、発明者の検討により、酸化錫と酸化タングステンと酸化イッテルビウムとを含むターゲットを用いて半導体層を形成する場合、半導体層を形成する工程を、10℃以上500℃以下で行うことで非晶質な半導体層を形成できることがわかった。さらには、半導体層を形成する工程を、室温で実施するとよい。ここで、「室温で実施」とは、半導体層を形成する工程のために非加熱であり、作業環境の温度調整が不要であることを意味する。 In the method for manufacturing a thin film transistor of this embodiment, when the semiconductor layer is formed using a target containing tin oxide, tungsten oxide, and ytterbium oxide, the process of forming the semiconductor layer is 10 ° C. or higher, as studied by the inventors. It was found that an amorphous semiconductor layer can be formed by carrying out at 500 ° C. or lower. Further, the step of forming the semiconductor layer is preferably performed at room temperature. Here, “implemented at room temperature” means that the semiconductor layer is not heated for the step of forming the semiconductor layer, and the temperature adjustment of the working environment is unnecessary.

 本実施形態の薄膜トランジスタの製造方法において採用されるスパッタリング法としては、RFスパッタリングおよびDCスパッタリングなど公知のものを用いることができる。 As the sputtering method employed in the method for manufacturing the thin film transistor of the present embodiment, known methods such as RF sputtering and DC sputtering can be used.

 以上、本願第4発明の薄膜トランジスタの製造方法を説明した。 The method for manufacturing the thin film transistor of the fourth invention of the present application has been described above.

 以上のような図8、図9に例示したような本願第4発明の薄膜トランジスタによれば、新規な複合金属酸化物を半導体層に用いることで、特性変化が抑制されたものとなる。 According to the thin film transistor of the fourth invention of this application as illustrated in FIGS. 8 and 9 as described above, the characteristic change is suppressed by using the novel composite metal oxide for the semiconductor layer.

 また、以上のような構成の半導体装置によれば、特性変化が抑制された薄膜トランジスタを有し、高い信頼性を有するものとなる。 Further, according to the semiconductor device having the above configuration, it has a thin film transistor in which the characteristic change is suppressed, and has high reliability.

また、以上のような薄膜トランジスタの製造方法によれば、新規な複合金属酸化物を半導体層に用い、特性変化が抑制された薄膜トランジスタを容易に製造することができる。 Further, according to the method for manufacturing a thin film transistor as described above, a thin film transistor in which a change in characteristics is suppressed can be easily manufactured by using a novel composite metal oxide for a semiconductor layer.

なお、本実施形態においては、いわゆるボトムゲート型の薄膜トランジスタについて説明したが、本願第4発明はいわゆるトップゲート型の薄膜トランジスタに適用することもできる。 Although the so-called bottom gate type thin film transistor has been described in the present embodiment, the fourth invention of the present application can also be applied to a so-called top gate type thin film transistor.

 また、本実施形態においては、いわゆるトップコンタクト型の薄膜トランジスタについて説明したが、本願第4発明はいわゆるボトムコンタクト型の薄膜トランジスタに適用することもできる。 In the present embodiment, a so-called top contact type thin film transistor has been described. However, the fourth invention of the present application can also be applied to a so-called bottom contact type thin film transistor.

 以上、添付図面を参照しながら本願第4発明に係る好適な実施の形態例について説明したが、本願第4発明は斯かる例に限定されないことは言うまでもない。上述した例において示した各構成部材の諸形状や組み合わせ等は一例であって、本願第4発明の主旨から逸脱しない範囲において設計要求等に基づき種々変更可能である。 As described above, the preferred embodiment according to the fourth invention of the present application has been described with reference to the accompanying drawings, but it is needless to say that the fourth invention of the present application is not limited to such an example. Various shapes, combinations, and the like of the constituent members shown in the above-described examples are merely examples, and various modifications can be made based on design requirements and the like without departing from the gist of the fourth invention of the present application.

 更に、以下、図を参照しながら、本願第5発明の酸化物半導体を用いる薄膜トランジスタおよび薄膜トランジスタの製造方法について説明する。なお、以下の全ての図面において、各構成要素の寸法や比率などが、図面を見易くするために適宜異ならせてある。そのため、実際の各構成要素の寸法や比率などは、それらが開示されている図面に制限されるものではない。
 本願第5発明の酸化物半導体を用いる薄膜トランジスタは、ソース電極およびドレイン電極と、前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、前記ゲート電極と前記半導体層との間に設けられた絶縁体層とを設け、前記半導体層が、酸素欠損が導入されることにより電子キャリアを生成できる金属酸化物からなる第1金属酸化物と、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物とを含んでなる、酸素欠損が導入された酸化物半導体であって、前記第1金属酸化物の金属が、その酸素欠損部分に導入された、OH基、H基、F基、Cl基、又はB基からなる群から選択される少なくとも1つの基と結合している前記酸化物半導体で形成されている、薄膜トランジスタである。
Further, a thin film transistor using the oxide semiconductor of the fifth invention of the present application and a method for manufacturing the thin film transistor will be described below with reference to the drawings. In all the drawings below, the dimensions and ratios of the constituent elements are appropriately changed in order to make the drawings easy to see. Therefore, the actual dimensions and ratios of the constituent elements are not limited to the drawings in which they are disclosed.
The thin film transistor using an oxide semiconductor according to the fifth invention of the present application corresponds to a source electrode and a drain electrode, a semiconductor layer provided in contact with the source electrode and the drain electrode, and a channel between the source electrode and the drain electrode. A metal oxide capable of generating electron carriers by introducing oxygen vacancies, and an insulating layer provided between the gate electrode and the semiconductor layer. An oxidation in which oxygen vacancies are introduced, comprising: a first metal oxide made of a material; and a second oxide having an oxygen separation energy greater than that of the first metal oxide by 200 kJ / mol or more. An OH group, an H group, an F group, a Cl group, wherein the metal of the first metal oxide is introduced into the oxygen deficient portion, It is formed in the oxide semiconductor which is bound to at least one group selected from the group consisting of radicals, a thin film transistor.

 また、本願第5発明の酸化物半導体を用いる薄膜トランジスタの製造方法は、上記薄膜トランジスタを製造するにあたり、前記半導体層を10℃以上400℃以下で形成する工程を有する。前記半導体層を10℃以上200℃以下で形成する工程を有してもよい。 The method for manufacturing a thin film transistor using an oxide semiconductor according to the fifth aspect of the present invention includes a step of forming the semiconductor layer at 10 ° C. or higher and 400 ° C. or lower when manufacturing the thin film transistor. You may have the process of forming the said semiconductor layer at 10 degreeC or more and 200 degrees C or less.

 図15は、本願第5発明の酸化物半導体を用いる薄膜トランジスタの一実施形態を示した概略断面図である。
 図15における薄膜トランジスタ310は、いわゆるボトムゲート型のトランジスタである。この薄膜トランジスタ310は、図15に示されている通り、基板320上に設けられたゲート電極330と、ゲート電極330を覆って設けられた絶縁体層(ゲート絶縁体層)340と、絶縁体層340の上面に設けられた半導体層350と、半導体層350の上面において半導体層350に接して設けられたソース電極360およびドレイン電極370と、全体(具体的には、ソース電極360、ドレイン電極370、及びソース電極360とドレイン電極370に重畳していない領域の半導体層350)を層間絶縁膜380で覆う構造を有している。
FIG. 15 is a schematic cross-sectional view showing an embodiment of a thin film transistor using an oxide semiconductor according to the fifth invention.
A thin film transistor 310 in FIG. 15 is a so-called bottom-gate transistor. As shown in FIG. 15, the thin film transistor 310 includes a gate electrode 330 provided on a substrate 320, an insulator layer (gate insulator layer) 340 provided so as to cover the gate electrode 330, and an insulator layer. The semiconductor layer 350 provided on the upper surface of 340, the source electrode 360 and the drain electrode 370 provided in contact with the semiconductor layer 350 on the upper surface of the semiconductor layer 350, and the whole (specifically, the source electrode 360 and the drain electrode 370) , And a region of the semiconductor layer 350 which does not overlap with the source electrode 360 and the drain electrode 370) is covered with an interlayer insulating film 380.

<基板320>
 基板320は、公知の形成材料で形成されたものを用いることができ、光透過性を有するものと光透過性を有しないもののいずれを用いてもよい。
 基板320の形成材料としては、例えば、ケイ酸アルカリ系ガラス、石英ガラス、窒化ケイ素などを形成材料とする無機基板;シリコン基板;表面が絶縁処理された金属基板;アクリル樹脂、ポリカーボネート樹脂、PET(ポリエチレンテレフタレート)やPBT(ポリブチレンテレフタレート)などのポリエステル樹脂などを形成材料とする樹脂基板;紙製の基板などの種々のものを用いることができる。また、これらの材料を複数組み合わせた複合材料を形成材料とする基板であっても構わない。
 また、基板320の厚さは、設計に応じて適宜設定することができる。
<Board 320>
As the substrate 320, a substrate formed of a known forming material can be used, and any of those having light transmittance and those having no light transmittance may be used.
As a material for forming the substrate 320, for example, an inorganic substrate made of alkali silicate glass, quartz glass, silicon nitride, or the like; a silicon substrate; a metal substrate with an insulating surface; acrylic resin, polycarbonate resin, PET ( Various substrates such as a resin substrate made of a polyester resin such as polyethylene terephthalate) or PBT (polybutylene terephthalate); a paper substrate can be used. Further, the substrate may be a composite material formed by combining a plurality of these materials.
Further, the thickness of the substrate 320 can be appropriately set according to the design.

<ゲート電極330>
 ゲート電極330は、半導体層350のチャネル領域に対応させて(チャネル領域と平面的に重なる位置に)設けられている。つまり、半導体層350のチャネル領域は、ゲート電極330の位置に対応する領域内にある。なお、薄膜トランジスタの半導体層は主にゲート電極側がチャネルとして機能する。ゲート電極330としては、例えばMoWを使用する。
<Gate electrode 330>
The gate electrode 330 is provided so as to correspond to the channel region of the semiconductor layer 350 (at a position overlapping the channel region in plan view). That is, the channel region of the semiconductor layer 350 is in a region corresponding to the position of the gate electrode 330. Note that the semiconductor layer of the thin film transistor mainly functions as a channel on the gate electrode side. For example, MoW is used as the gate electrode 330.

<半導体層350>
 半導体層350は、本願第5発明の酸化物半導体によって形成されている。具体的には、半導体層350は、酸素欠損が導入されることにより電子キャリアを生成できる金属酸化物からなる第1金属酸化物と、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物とから形成されている、酸素欠損部を有する酸化物半導体であって、更に、その酸素欠損部がOH基、H基、F基、Cl基、又はB基からなる群から選択される少なくとも1つによって置換されることによって、前記第1金属酸化物とその置換基とが結合している前記酸化物半導体によって形成されている。但し、本願第5発明の作用効果を達成できる限り、半導体層350には、これら以外の成分や不可避の不純物が含まれていてもよい。
<Semiconductor layer 350>
The semiconductor layer 350 is formed of the oxide semiconductor of the fifth invention of the present application. Specifically, the semiconductor layer 350 includes a first metal oxide made of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and an oxygen separation energy of the first metal oxide. An oxide semiconductor having an oxygen deficient portion, which is formed from a second oxide greater than the energy by 200 kJ / mol or more, and the oxygen deficient portion further includes an OH group, an H group, an F group, a Cl group, Alternatively, it is formed by the oxide semiconductor in which the first metal oxide and the substituent are bonded by being substituted by at least one selected from the group consisting of B groups. However, as long as the effects of the fifth invention of the present application can be achieved, the semiconductor layer 350 may contain components other than these and unavoidable impurities.

 ここで、第1金属酸化物は、酸素欠損が導入されることで電子キャリアを生成できる半導体の性質を有する物質である。第1金属酸化物としては、好ましくは、インジウム、ガリウム、亜鉛、および錫からなる群から選択された少なくとも一つを含む金属酸化物であり、第2酸化物は、好ましくは、ジルコニウム(Zr)、ケイ素(Si)、チタン(Ti)、タングステン(W)、タンタル(Ta)、ハフニウム(Hf)、スカンジウム(Sc)、イットリウム(Y)、ランタン(La)、プラセオジム(Pr)、ネオジム(Nd)、ガドリニウム(Gd)、それ以外の希土類元素、アルミニウム(Al)、及び炭素(C)からなる群から選択される少なくとも1つを含む酸化物である。
 好ましくは、第1酸化物の元素がInである場合、第2酸化物の元素は、Zr、Pr、Si、Ti、W、Ta、La、Hf、Cからなる群から選択された少なくとも1つであり、第1酸化物の元素がSnである場合、第2酸化物の元素は、Sc、Ti、W、Nd、Gdからなる群から選択された少なくとも1つの元素である。
Here, the first metal oxide is a substance having a semiconductor property capable of generating electron carriers by introducing oxygen vacancies. The first metal oxide is preferably a metal oxide containing at least one selected from the group consisting of indium, gallium, zinc, and tin, and the second oxide is preferably zirconium (Zr). , Silicon (Si), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), scandium (Sc), yttrium (Y), lanthanum (La), praseodymium (Pr), neodymium (Nd) , Gadolinium (Gd), other rare earth elements, aluminum (Al), and carbon (C). The oxide includes at least one selected from the group consisting of carbon (C).
Preferably, when the element of the first oxide is In, the element of the second oxide is at least one selected from the group consisting of Zr, Pr, Si, Ti, W, Ta, La, Hf, and C. When the element of the first oxide is Sn, the element of the second oxide is at least one element selected from the group consisting of Sc, Ti, W, Nd, and Gd.

 第1酸化物の元素としては、好ましいものとして、更に、インジウム、亜鉛、および錫のうち少なくとも一つを含む金属酸化物を用いてもよいが、中でも、低温度で酸素欠損を導入し易いインジウムがより好ましい。
 また、第2酸化物としては、ケイ素(Si)、チタン(Ti)、タングステン(W)、タンタル(Ta)、ランタン(La)、ハフニウム(Hf)、ジルコニウム(Zr)、およびプラセオジム(Pr)からなる群から選択される少なくとも一つを含む酸化物を用いることもでき、より好ましくは、ケイ素(Si)、チタン(Ti)、タングステン(W)、タンタル(Ta)、ランタン(La)、およびハフニウム(Hf)からなる群から選択された少なくとも一つを含む酸化物である。また、第2酸化物としては、炭素(C)を含む酸化物を用いることもできる。
 また、前記第2酸化物の含有量は、0より大きく50重量%以下でもよく、0より大きく10重量%以下であってもよく、0より大きく5重量%以下であってもよい。
 半導体層350を形成する酸化物半導体において、酸素欠損部に導入される置換基としては、具体的には、OH基、H基、F基、Cl基、又はB基からなる群から選択される少なくとも1つが挙げられる。特に、OH基やH基が好ましく、OH基がより好ましい。
 その際、OH基を導入する場合、その含有量は0.1%以上10%以下が好ましく、H基を導入する場合、その含有量は0%よりも大きく0.1%以下が好ましく、F基、Cl基、又はB基を導入する場合、その含有量は5×1018atoms/cm超1×1021atoms/cm以下が好ましい。これらの含有量はXPSスペクトルのピーク面積比を用いて決定される。
 OH基の含有量(%)は、[OH]/([OH]+[O])×100の計算式により、H基の含有量(%)は、[H]/([H]+[O])×100の計算式により算出される。ここで、[OH]、[H]、[O]はそれぞれ、酸化物半導体中のOH、H、Oの原子比率を表す。
As a preferable element of the first oxide, a metal oxide containing at least one of indium, zinc, and tin may be used. In particular, indium that easily introduces oxygen vacancies at a low temperature may be used. Is more preferable.
As the second oxide, silicon (Si), titanium (Ti), tungsten (W), tantalum (Ta), lanthanum (La), hafnium (Hf), zirconium (Zr), and praseodymium (Pr) are used. It is also possible to use an oxide containing at least one selected from the group consisting of silicon (Si), titanium (Ti), tungsten (W), tantalum (Ta), lanthanum (La), and hafnium. It is an oxide containing at least one selected from the group consisting of (Hf). As the second oxide, an oxide containing carbon (C) can also be used.
The content of the second oxide may be greater than 0 and 50% by weight or less, greater than 0 and 10% by weight or less, and greater than 0 and 5% by weight or less.
In the oxide semiconductor forming the semiconductor layer 350, the substituent introduced into the oxygen deficient portion is specifically selected from the group consisting of an OH group, an H group, an F group, a Cl group, or a B group. At least one is mentioned. In particular, an OH group and an H group are preferable, and an OH group is more preferable.
At that time, when OH groups are introduced, the content is preferably 0.1% or more and 10% or less, and when H groups are introduced, the content is preferably greater than 0% and 0.1% or less, F When the group, Cl group, or B group is introduced, the content is preferably more than 5 × 10 18 atoms / cm 3 and not more than 1 × 10 21 atoms / cm 3 . These contents are determined using the peak area ratio of the XPS spectrum.
The OH group content (%) is calculated by the formula [OH] / ([OH] + [O]) × 100, and the H group content (%) is [H] / ([H] + [ O]) × 100. Here, [OH], [H], and [O] represent atomic ratios of OH, H, and O in the oxide semiconductor, respectively.

 第1金属酸化物として酸化インジウム(In)を用いた場合、酸化インジウムの酸素のかい離エネルギーは346±30kJ/molと小さいので、酸化インジウムから酸素が容易に脱離して酸素欠損を生成し易い。しかしながら、酸素欠損量が大きくなりすぎると半導体的な性質から金属的な性質へ変わって半導体層として適さなくなる。本願発明者らはこの問題を解決すべく検討を重ねた結果、酸化インジウムの酸素欠損量を制御するためには酸化インジウムの酸素のかい離エネルギーより大きな酸素のかい離エネルギーを有する第2酸化物を添加すればよいことを見出した。
 具体的には、酸素のかい離エネルギーが725kJ/mol以上、より好ましくは780kJ/mol以上の酸化物を第2酸化物として用いると、酸化インジウムの酸素欠損量の制御が容易となる。
When indium oxide (In 2 O 3 ) is used as the first metal oxide, the oxygen separation energy of indium oxide is as small as 346 ± 30 kJ / mol, so oxygen is easily desorbed from indium oxide to generate oxygen vacancies. Easy to do. However, if the amount of oxygen vacancies becomes too large, it changes from semiconducting properties to metallic properties and becomes unsuitable as a semiconductor layer. As a result of repeated studies to solve this problem, the inventors of the present application added a second oxide having an oxygen separation energy larger than that of indium oxide in order to control the oxygen deficiency amount of indium oxide. I found out that I should do.
Specifically, when an oxide having an oxygen separation energy of 725 kJ / mol or more, more preferably 780 kJ / mol or more is used as the second oxide, the amount of oxygen deficiency of indium oxide can be easily controlled.

 また、第1金属酸化物として酸化インジウム以外の物質まで一般化した場合には、第2酸化物としてはその酸素かい離エネルギーが第1金属酸化物に比べて200kJ/mol以上、より好ましくは255kJ/mol以上大きいものを使用すればよい。
 そのため、前記第2酸化物の酸素のかい離エネルギーは、前記第1金属酸化物の酸素のかい離エネルギーよりも255kJ/mol以上大きくてもよい。
Further, when a material other than indium oxide is generalized as the first metal oxide, the oxygen separation energy of the second oxide is 200 kJ / mol or more, more preferably 255 kJ / mol compared to the first metal oxide. What is larger than mol may be used.
Therefore, the oxygen separation energy of the second oxide may be 255 kJ / mol or more larger than the oxygen separation energy of the first metal oxide.

 酸素のかい離エネルギーが780kJ/mol以上である金属酸化物をまとめた表C1および酸素のかい離エネルギーが725kJ/mol以上780kJ/mol以下である酸化物をまとめた表C2に示されるように、本実施形態において、使用可能な第2酸化物のうち第2酸化物としては、酸化ジルコニウム(Zr-O)、酸化プラセオジム(Pr-O)、酸化ランタン(La-O)、酸化ケイ素(Si-O)、酸化タンタル(Ta-O)、および酸化ハフニウム(Hf-O)が挙げられる。 As shown in Table C1 that summarizes metal oxides having an oxygen separation energy of 780 kJ / mol or more and Table C2 that summarizes oxides having an oxygen separation energy of 725 kJ / mol or more and 780 kJ / mol or less. Among the usable second oxides, the second oxide includes zirconium oxide (Zr—O), praseodymium oxide (Pr—O), lanthanum oxide (La—O), and silicon oxide (Si—O). Tantalum oxide (Ta—O), and hafnium oxide (Hf—O).

Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000003

Figure JPOXMLDOC01-appb-T000004
Figure JPOXMLDOC01-appb-T000004

 本実施形態において第1金属酸化物を適した酸素欠損量を有する半導体層350とするために添加する第2酸化物のうち第2酸化物としては、特に、表C1に示した780kJ/mol以上の第2酸化物がより好ましい。具体的には、酸化ランタン(La-O)、酸化ケイ素(Si-O)、酸化タンタル(Ta-O)、および酸化ハフニウム(Hf-O)が挙げられる。
 なお、表中には挙げていないが、酸化チタン(Ti-O)の酸素のかい離エネルギーは、666.5±5.6kJ/molであり、酸化タングステン(W-O)の酸素のかい離エネルギーは、720±71kJ/molである。
Among the second oxides added to make the first metal oxide a semiconductor layer 350 having a suitable oxygen deficiency in this embodiment, the second oxide is particularly 780 kJ / mol or more shown in Table C1. The second oxide is more preferable. Specifically, lanthanum oxide (La—O), silicon oxide (Si—O), tantalum oxide (Ta—O), and hafnium oxide (Hf—O) can be given.
Although not listed in the table, the oxygen separation energy of titanium oxide (Ti—O) is 666.5 ± 5.6 kJ / mol, and the oxygen separation energy of tungsten oxide (W—O) is 720 ± 71 kJ / mol.

 また、第1金属酸化物を適した酸素欠損量を有する半導体層350とするために第1金属酸化物へ添加する第2酸化物の含有量としては、0より大きく50重量%以下の範囲が好ましい。特に、200℃以下の低温度での作製という点で、第1金属酸化物へ添加する第2酸化物の含有量を0より大きく5重量%以下の範囲にすることが好ましい。 Further, the content of the second oxide added to the first metal oxide in order to make the first metal oxide a semiconductor layer 350 having a suitable oxygen deficiency ranges from 0 to 50% by weight. preferable. In particular, it is preferable that the content of the second oxide added to the first metal oxide is in the range of more than 0 and 5% by weight or less in terms of production at a low temperature of 200 ° C. or less.

 また、半導体層350(即ち、半導体層350を形成する酸化物半導体)は非晶質であることが好ましい。
 In-Zn-O系やIn-Ga-Zn-O系の金属酸化物では、半導体層の形成時に多結晶状になり易い。そのため、通常知られた薄膜トランジスタでは、半導体層に含まれる結晶粒に起因して、半導体層の表面が平坦にはならない。また、通常知られた酸化膜トランジスタの半導体層は、このような結晶粒に起因して、面方向の電気伝導度が低下してしまう。
 したがって、半導体層の表面の平坦化及び高い電気伝導度を得るためには、半導体層350は非晶質構造であることが好ましい。
In addition, the semiconductor layer 350 (that is, the oxide semiconductor forming the semiconductor layer 350) is preferably amorphous.
In-Zn-O-based and In-Ga-Zn-O-based metal oxides tend to be polycrystalline when a semiconductor layer is formed. Therefore, in a generally known thin film transistor, the surface of the semiconductor layer does not become flat due to crystal grains contained in the semiconductor layer. In addition, the normally known semiconductor layer of an oxide film transistor has a reduced electrical conductivity in the plane direction due to such crystal grains.
Therefore, in order to obtain planarization of the surface of the semiconductor layer and high electrical conductivity, the semiconductor layer 350 preferably has an amorphous structure.

 また、半導体層350の厚さ(即ち、半導体層350を形成する酸化物半導体の厚さ)は5nm以上かつ20nm以下の範囲であることが好ましい。
 なお、本実施形態においては、その厚さは、半導体層350を形成したスパッタチャンバー内に、膜厚校正を主目的として配置された水晶発振式膜厚計を用いて測定した。
The thickness of the semiconductor layer 350 (that is, the thickness of the oxide semiconductor forming the semiconductor layer 350) is preferably in the range of 5 nm to 20 nm.
In the present embodiment, the thickness was measured using a crystal oscillation type film thickness meter disposed mainly for the purpose of film thickness calibration in the sputtering chamber in which the semiconductor layer 350 was formed.

 また、第2酸化物は炭素(C)の酸化物を含んでもよい。
 具体的には第1金属酸化物に比べてかい離エネルギーが大きな酸化物を形成する元素を添加してもよい。具体的には、酸素欠損を導入した酸化物半導体は、第1金属酸化物に、炭素(C)の酸化物を添加したものであってもよい。これは、C-O結合の酸素かい離エネルギーが1076.38±0.67kJ/molと大きいために、第1金属酸化物へ導入する酸素欠損量を容易に制御することができるからである。
Further, the second oxide may include an oxide of carbon (C).
Specifically, an element that forms an oxide having a larger separation energy than the first metal oxide may be added. Specifically, the oxide semiconductor into which oxygen vacancies are introduced may be one in which an oxide of carbon (C) is added to the first metal oxide. This is because the oxygen desorption energy of the C—O bond is as large as 1076.38 ± 0.67 kJ / mol, so that the amount of oxygen deficiency introduced into the first metal oxide can be easily controlled.

 第1金属酸化物内に酸化物を添加するにあたっては、添加処理操作自体では必ずしも酸化物その物を添加する必要はなく、例えば酸化物を構成する酸素以外の元素を添加する処理を行い、第1金属酸化物内部で酸化物とすることも可能である。よって、本願においては、このように添加処理操作の形態にかかわらず、第1金属酸化物内に酸化物の形で存在する形態で添加を行うことを「酸化物を添加する」と称することに注意されたい。 When the oxide is added to the first metal oxide, it is not always necessary to add the oxide itself in the addition treatment operation itself. For example, a treatment for adding an element other than oxygen constituting the oxide is performed. An oxide can also be formed inside one metal oxide. Therefore, in the present application, regardless of the form of the addition treatment operation, the addition in the form of the oxide in the first metal oxide is referred to as “adding the oxide”. Please be careful.

 また、第1金属酸化物の酸化インジウム(In)への炭素(C)の添加は、Inターゲットおよびグラファイトターゲットを用いた共スパッタリング法により、各々スパッタリングパワーの比率を変えることで添加量を制御でき、その含有量は0より大きく10重量%以下であることがより好ましい。
 よって、第2酸化物として含まれる炭素(C)の含有量は0より大きく10重量%以下が好ましい。
In addition, the addition of carbon (C) to the first metal oxide indium oxide (In 2 O 3 ) is to change the ratio of the sputtering power by a co-sputtering method using an In 2 O 3 target and a graphite target. The amount added can be controlled by the control, and the content is more preferably greater than 0 and 10% by weight or less.
Therefore, the content of carbon (C) contained as the second oxide is preferably greater than 0 and 10% by weight or less.

 半導体層350における第1の金属酸化物と第2酸化物の状態は、第1の金属酸化物中に第2酸化物が一様に添加、つまりドーピングされることによって一様な(即ち、均一に混じった)物質となっている。 The states of the first metal oxide and the second oxide in the semiconductor layer 350 are uniform (that is, uniform by adding or doping the second oxide into the first metal oxide uniformly). It is a substance).

 なお、酸素のかい離エネルギーが大きな第2酸化物として、例えば、炭素(C)の酸化物を用いる場合において、他の第2酸化物を同時に使用して酸素欠損を導入した酸化物半導体を形成することも可能である。また、本願第5発明における酸素のかい離エネルギーの大きな第2酸化物の添加処理の際、処理の種類によっては酸素欠損を導入した酸化物半導体中に両方の種類の酸化物が不可避的に共存することもあり得る。
 例えば、このような酸化物半導体の薄膜をゾルゲル法などの溶液法で作製する場合には薄膜中に炭素が残留する可能性が高い。このような場合も本願第5発明に包含されることに注意されたい。
Note that, for example, in the case of using a carbon (C) oxide as the second oxide having a large oxygen separation energy, another oxide is used to form an oxide semiconductor in which oxygen deficiency is introduced. It is also possible. In addition, when the second oxide having a large oxygen separation energy is added in the fifth invention of the present application, both types of oxides inevitably coexist in the oxide semiconductor into which oxygen deficiency is introduced depending on the type of the treatment. It can happen.
For example, when such a thin film of an oxide semiconductor is manufactured by a solution method such as a sol-gel method, there is a high possibility that carbon remains in the thin film. It should be noted that such a case is also included in the fifth invention of the present application.

 また、半導体層350において、ソース電極360、ドレイン電極370、及びソース電極360とドレイン電極370に重畳していない領域であって、ゲート電極330の位置に対応する領域が、チャネル領域に相当する。ソース電極360とドレイン電極370に重畳している領域は、メタル化によって接触抵抗を下げている。
 図15に示される通り、半導体層350のチャネル領域に対応させて(チャネル領域と平面的に重なる位置に)ゲート電極330が設けられている。
In the semiconductor layer 350, the source electrode 360, the drain electrode 370, and a region that does not overlap with the source electrode 360 and the drain electrode 370 and corresponds to the position of the gate electrode 330 corresponds to a channel region. In the region overlapping with the source electrode 360 and the drain electrode 370, the contact resistance is lowered by metallization.
As shown in FIG. 15, the gate electrode 330 is provided so as to correspond to the channel region of the semiconductor layer 350 (at a position overlapping the channel region in a plan view).

<ゲート電極330、ソース電極360、ドレイン電極370>
 ゲート電極330、ソース電極360、ドレイン電極370は、通常知られた材料で形成されたものを用いることができる。これらの電極の形成材料としては、例えば、アルミニウム(Al)、金(Au)、銀(Ag)、銅(Cu)、ニッケル(Ni)、モリブデン(Mo)、タンタル(Ta)、タングステン(W)などの金属材料やこれらの合金、インジウムスズ酸化物(Indium Tin Oxide、ITO)、酸化亜鉛(ZnO)などの導電性酸化物を挙げることができる。また、これらの電極は、例えば表面を金属材料でめっきすることにより2層以上の積層構造(例えば、Ti/Al/Ti)を形成していてもよい。
<Gate electrode 330, source electrode 360, drain electrode 370>
As the gate electrode 330, the source electrode 360, and the drain electrode 370, those formed of a generally known material can be used. Examples of materials for forming these electrodes include aluminum (Al), gold (Au), silver (Ag), copper (Cu), nickel (Ni), molybdenum (Mo), tantalum (Ta), and tungsten (W). Examples thereof include metal materials such as these, alloys thereof, and conductive oxides such as indium tin oxide (ITO) and zinc oxide (ZnO). Moreover, these electrodes may form a laminated structure of two or more layers (for example, Ti / Al / Ti) by, for example, plating the surface with a metal material.

 ゲート電極330、ソース電極360、ドレイン電極370は、同じ形成材料で形成されたものであってもよく、異なる形成材料で形成されたものであってもよい。製造が容易となることから、ソース電極360とドレイン電極370とは同じ形成材料であることが好ましい。 The gate electrode 330, the source electrode 360, and the drain electrode 370 may be formed of the same forming material, or may be formed of different forming materials. Since manufacture becomes easy, it is preferable that the source electrode 360 and the drain electrode 370 are the same formation material.

<絶縁体層(ゲート絶縁体層)340>
 絶縁体層(ゲート絶縁体層)340は、絶縁性を有し、ゲート電極330と、ソース電極360およびドレイン電極370との間を電気的に絶縁することが可能であれば、無機材料および有機材料のいずれを用いて形成してもよい。無機材料としては、例えばSiO、SiN、SiON、Al、HfOなどの通常知られた絶縁性の酸化物、窒化物、酸窒化物を挙げることができる。有機材料としては、例えば、アクリル樹脂、エポキシ樹脂、シリコン樹脂、フッ素系樹脂などを挙げることができる。有機材料としては、製造や加工が容易であることから、光硬化型の樹脂材料であることが好ましい。
 因みに、基板320にガラスを使用した場合、絶縁体層(ゲート絶縁体層)340は、基板320の接触部分にSiN層を配置し、その上にSiOを配置する二層の積層構造とするのが好ましい。このSiN層は、基板320から発生するカルシウムやリン等が拡散して半導体層350を劣化させるのを防止することができ、その上に配置されたSiOは、SiN層からの窒素の拡散による半導体層の劣化を防止することができるからである。
<Insulator layer (gate insulator layer) 340>
The insulator layer (gate insulator layer) 340 is an insulating material and an organic material as long as it has insulating properties and can electrically insulate the gate electrode 330 from the source electrode 360 and the drain electrode 370. Any of the materials may be used. Examples of the inorganic material include normally known insulating oxides such as SiO 2 , SiN x , SiON, Al 2 O 3 , and HfO 2 , nitrides, and oxynitrides. Examples of the organic material include acrylic resin, epoxy resin, silicon resin, and fluorine resin. The organic material is preferably a photocurable resin material because it is easy to manufacture and process.
Incidentally, when glass is used for the substrate 320, the insulator layer (gate insulator layer) 340 has a two-layer laminated structure in which a SiN layer is disposed at a contact portion of the substrate 320 and SiO 2 is disposed thereon. Is preferred. This SiN layer can prevent the calcium, phosphorus, etc. generated from the substrate 320 from diffusing and deteriorating the semiconductor layer 350, and the SiO 2 disposed thereon is caused by the diffusion of nitrogen from the SiN layer. This is because deterioration of the semiconductor layer can be prevented.

<層間絶縁膜380>
 層間絶縁膜380は、絶縁性を有し、ソース電極360、ドレイン電極370、及びソース電極360とドレイン電極370に重畳していない領域の半導体層350との間を電気的に絶縁することが可能であれば、無機材料および有機材料のいずれを用いて形成してもよい。無機材料としては、例えばSiO、SiN、SiON、Al、HfOなどの通常知られた絶縁性の酸化物、窒化物、酸窒化物を挙げることができる。有機材料としては、例えば、アクリル樹脂、エポキシ樹脂、シリコン樹脂、フッ素系樹脂などを挙げることができる。有機材料としては、製造や加工が容易であることから、光硬化型の樹脂材料であることが好ましい。
<Interlayer insulating film 380>
The interlayer insulating film 380 has insulating properties, and can electrically insulate the source electrode 360, the drain electrode 370, and the source electrode 360 and the semiconductor layer 350 in a region not overlapping with the drain electrode 370. If so, it may be formed using either an inorganic material or an organic material. Examples of the inorganic material include normally known insulating oxides such as SiO 2 , SiN x , SiON, Al 2 O 3 , and HfO 2 , nitrides, and oxynitrides. Examples of the organic material include acrylic resin, epoxy resin, silicon resin, and fluorine resin. The organic material is preferably a photocurable resin material because it is easy to manufacture and process.

<酸化物半導体の製造方法>
 次に、本願第5発明の酸化物半導体を製造する方法について説明する。本実施形態においては、図15の半導体層350を形成するものである。
 本実施形態の酸化物半導体は、物理蒸着法(または物理気相成長法)を用いることにより形成することも可能である。
 ここで、物理蒸着法としては、蒸着法やスパッタ法が挙げられる。蒸着法としては、真空蒸着法、分子線蒸着法(MBE)、イオンプレーティング法、イオンビーム蒸着法などを例示することができる。また、スパッタ法としては、コンベンショナル・スパッタリング、マグネトロン・スパッタリング、イオンビーム・スパッタリング、ECR(電子サイクロトロン共鳴)・スパッタリング、反応性スパッタリングなどを例示することができる。スパッタリング法においてプラズマを用いた場合は、反応性スパッタリング法、DC(直流)スパッタリング法、高周波(RF)スパッタリング法等の成膜法を用いることができる。
 半導体層350を形成するにあたり、酸素欠損が導入されることにより電子キャリアを生成できる金属酸化物からなる第1金属酸化物と、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物とから形成されている、酸素欠損部を有する酸化物半導体をまず作製する。具体的には、第1金属酸化物の粉末と、酸素のかい離エネルギーが第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな酸化物の粉末とを含む焼結体であるターゲットと、希ガスと酸素との混合ガスとを用いた物理蒸着法により作製する。ここでは、物理蒸着法としてスパッタリング法を用いることとして説明する。
<Method for producing oxide semiconductor>
Next, a method for manufacturing the oxide semiconductor of the fifth invention of the present application will be described. In this embodiment, the semiconductor layer 350 of FIG. 15 is formed.
The oxide semiconductor of this embodiment can also be formed by using physical vapor deposition (or physical vapor deposition).
Here, examples of physical vapor deposition include vapor deposition and sputtering. Examples of the vapor deposition method include vacuum vapor deposition, molecular beam vapor deposition (MBE), ion plating, and ion beam vapor deposition. Examples of the sputtering method include conventional sputtering, magnetron sputtering, ion beam sputtering, ECR (electron cyclotron resonance) sputtering, and reactive sputtering. When plasma is used in the sputtering method, a film forming method such as a reactive sputtering method, a DC (direct current) sputtering method, or a radio frequency (RF) sputtering method can be used.
In forming the semiconductor layer 350, the first metal oxide composed of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and the oxygen separation energy of the first metal oxide is greater than the oxygen separation energy of the first metal oxide. First, an oxide semiconductor having an oxygen deficient portion, which is formed from a second oxide that is greater than or equal to 200 kJ / mol, is formed. Specifically, a target that is a sintered body including a first metal oxide powder and an oxide powder having an oxygen separation energy of 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide; It is manufactured by a physical vapor deposition method using a mixed gas of a rare gas and oxygen. Here, it demonstrates as using sputtering method as a physical vapor deposition method.

 例えば、酸素欠損が導入されることにより電子キャリアを生成できる金属酸化物からなる第1金属酸化物と、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物とから形成されている、酸素欠損部を有する酸化物半導体として、In-Si-O系の金属酸化物を採用する場合には、ターゲットは、酸化インジウムの粉末と酸化ケイ素の粉末との焼結体を採用するのが好ましい。また、ターゲットには、酸化ケイ素の重量%以下での添加物(金属酸化物など)等の不純物が混入していてもよい。例えば、ターゲットに、意図しない不純物として、酸化インジウムおよび酸化ケイ素以外の金属酸化物(酸化亜鉛など)が、ターゲット全体における酸化ケイ素含有量以下の割合(重量比)で混入することがあっても構わない。 For example, a first metal oxide composed of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and the oxygen separation energy of the first metal oxide is 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide. In the case where an In—Si—O-based metal oxide is used as the oxide semiconductor formed of the second oxide and having an oxygen deficiency, the target is an indium oxide powder and a silicon oxide powder. It is preferable to employ a sintered body. Further, the target may be mixed with impurities such as an additive (metal oxide or the like) at a weight percent or less of silicon oxide. For example, metal oxides (such as zinc oxide) other than indium oxide and silicon oxide may be mixed into the target at a ratio (weight ratio) equal to or lower than the silicon oxide content in the entire target as unintended impurities. Absent.

 その場合、焼結体に含まれる酸化ケイ素の含有量が、0重量%より多く50重量%以下であるのが好ましい。また、酸化ケイ素の含有量は、0重量%より多く5重量%以下であるとより好ましい。 In that case, the content of silicon oxide contained in the sintered body is preferably more than 0% by weight and 50% by weight or less. Further, the content of silicon oxide is more preferably more than 0 wt% and not more than 5 wt%.

 通常知られた酸化物半導体であるIn-Zn-O系やIn-Ga-Zn-O系の金属酸化物では、酸化インジウムを「ホスト材料」、酸化亜鉛や酸化ガリウムを「ゲスト材料」とすると、ホスト材料(酸化インジウム)に対して、2割~3割のゲスト材料(酸化亜鉛や酸化ガリウム)が混入されている。 In In-Zn-O-based and In-Ga-Zn-O-based metal oxides, which are generally known oxide semiconductors, if indium oxide is the "host material" and zinc oxide or gallium oxide is the "guest material" The guest material (zinc oxide or gallium oxide) is mixed with 20-30% of the host material (indium oxide).

 これに対して、本実施形態において、上述のような焼結体をターゲットに用いて薄膜形成する。本実施形態の製造方法で製造される酸化物半導体においては上述したように酸化ケイ素の含有量は0重量%より多く5重量%以下であるとより好ましいので、この好ましい組成とした場合の半導体層350の酸化物半導体は、通常知られた酸化物半導体と比べて、ホスト材料(酸化インジウム)に対するゲスト材料(酸化ケイ素)の含有量が、極めて少ないものとなる。 In contrast, in this embodiment, a thin film is formed using the sintered body as described above as a target. In the oxide semiconductor manufactured by the manufacturing method of the present embodiment, the silicon oxide content is more preferably more than 0 wt% and not more than 5 wt% as described above. Therefore, the semiconductor layer in this preferred composition The 350 oxide semiconductor has an extremely small content of the guest material (silicon oxide) with respect to the host material (indium oxide) as compared with a conventionally known oxide semiconductor.

 また、本実施形態の酸化物半導体の製造方法においては、プロセスガスとして希ガスと酸素との混合ガスを用いる。希ガスとしては、ヘリウム、ネオン、アルゴン、クリプトン、キセノンが挙げられる。また、プロセスガスには、水素原子を有する化合物を含まない。 In the oxide semiconductor manufacturing method of this embodiment, a mixed gas of a rare gas and oxygen is used as a process gas. Examples of the rare gas include helium, neon, argon, krypton, and xenon. Further, the process gas does not include a compound having a hydrogen atom.

 また、本実施形態の酸化物半導体の製造方法においては、発明者の検討により、酸素欠損が導入されることにより電子キャリアを生成できる金属酸化物からなる第1金属酸化物と、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物とから形成されている、酸素欠損部を有する酸化物半導体を作製するにあたり、酸化インジウムと酸化ケイ素とを含むターゲットを用いる場合、該酸化物半導体を構成する金属酸化物を非晶質膜とするのに高温を必要としないことがわかっている。そのため、本実施形態の薄膜トランジスタ310の製造方法においては、酸素欠損を導入したIn-Si-O系を形成する工程を、10℃以上200℃以下で行うことで非晶質な酸化物半導体を形成することができる。また、200℃より高く400℃以下で行うことで、結晶化した好適な酸化物半導体を形成することもできる。さらには、酸化物半導体を形成する工程を、室温で実施するとよい。ここで、「室温で実施」とは、酸化物半導体を形成する工程のために非加熱であり、作業環境の温度調整が不要であることを意味する。 In addition, in the method for manufacturing an oxide semiconductor according to the present embodiment, according to the study of the inventor, the first metal oxide composed of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and the oxygen separation energy. In producing an oxide semiconductor having an oxygen deficient portion, which is formed from a second oxide having a larger oxygen dissociation energy than the first metal oxide by 200 kJ / mol or more, indium oxide and silicon oxide are used. In the case where a target including the oxide semiconductor is used, it has been found that a high temperature is not required to make the metal oxide constituting the oxide semiconductor an amorphous film. Therefore, in the method for manufacturing the thin film transistor 310 of this embodiment, an amorphous oxide semiconductor is formed by performing the step of forming an In—Si—O system into which oxygen vacancies are introduced at 10 ° C. or higher and 200 ° C. or lower. can do. In addition, by performing the treatment at a temperature higher than 200 ° C. and lower than or equal to 400 ° C., a suitable crystallized oxide semiconductor can be formed. Further, the step of forming the oxide semiconductor is preferably performed at room temperature. Here, “implemented at room temperature” means non-heating for the step of forming an oxide semiconductor, and does not require temperature adjustment of the working environment.

 本実施形態の酸化物半導体の製造方法において採用されるスパッタリング法としては、RFスパッタリングおよびDCスパッタリングなど公知のものを用いることができる。 As the sputtering method employed in the method for manufacturing an oxide semiconductor according to this embodiment, known methods such as RF sputtering and DC sputtering can be used.

 また、ターゲットは、酸化インジウムの粉末と、酸化ケイ素の粉末とを用いていれば、これら粉末の混合物の焼結体であってもよく、それぞれの粉末の焼結体であってもよい。それぞれの金属酸化物の粉末毎に焼結体を形成する場合には、複数の焼結体を用いた共スパッタリングにより酸素欠損量を制御した酸化物半導体を形成することができる。 Further, the target may be a sintered body of a mixture of these powders or a sintered body of each powder, as long as the target uses indium oxide powder and silicon oxide powder. In the case where a sintered body is formed for each metal oxide powder, an oxide semiconductor in which the amount of oxygen vacancies is controlled by co-sputtering using a plurality of sintered bodies can be formed.

 第1金属酸化物として、酸化インジウムの代わりに、酸化亜鉛および酸化錫あるいは酸化インジウム、酸化ガリウム、酸化亜鉛および酸化錫を組み合わせた金属酸化物を用いた場合でも、上記と同様の方法を用いることで、酸素欠損量を制御した酸化物半導体を形成することができる。 The same method as described above should be used even when a metal oxide combining zinc oxide and tin oxide or indium oxide, gallium oxide, zinc oxide and tin oxide is used as the first metal oxide instead of indium oxide. Thus, an oxide semiconductor in which the amount of oxygen vacancies is controlled can be formed.

 第2酸化物として、酸化ケイ素について説明したが、代わりに、酸化ジルコニウム(Zr-O)、酸化プラセオジム(Pr-O)、酸化ランタン(La-O)、酸化タンタル(Ta-O)、および酸化ハフニウム(Hf-O)を用いた場合にも、それぞれの酸素のかい離エネルギーの大きさに対応したプロセス範囲で、酸素欠損量を制御した酸化物半導体を形成することができる。 Silicon oxide has been described as the second oxide, but instead zirconium oxide (Zr—O), praseodymium oxide (Pr—O), lanthanum oxide (La—O), tantalum oxide (Ta—O), and oxidation Even when hafnium (Hf—O) is used, an oxide semiconductor in which the amount of oxygen vacancies is controlled can be formed in a process range corresponding to the magnitude of the separation energy of oxygen.

 次に、このようにして作製した酸素欠損部を有する酸化物半導体に対して、その酸素欠損部に置換基を導入する。導入する置換基としては、OH基、H基、F基、Cl基、又はB基からなる群から選択される少なくとも1つを用いることが可能である。
 また、酸素欠損部にOH基を導入する場合、高湿度下で、熱処理することによって導入する。例えば、密閉した石英反応容器へHOガスを導入した80%以上の高湿度下、150℃から300℃の温度範囲で、熱処理することによって導入する。
 また、酸素欠損部にH基を導入する場合、H雰囲気ガス下で、熱処理することによって導入する。例えば、H雰囲気ガス下で300~400℃のアニール処理することによって導入する。
 また、酸素欠損部にF基、Cl基、又はB基を導入する場合、イオンインプランテーション(イオン注入)又はプラズマ処理法によって導入する。
Next, a substituent is introduced into the oxygen deficient portion of the oxide semiconductor having the oxygen deficient portion thus manufactured. As the substituent to be introduced, at least one selected from the group consisting of OH group, H group, F group, Cl group, or B group can be used.
In addition, when an OH group is introduced into the oxygen deficient part, it is introduced by heat treatment under high humidity. For example, it sealed 80% or more high humidity of introducing H 2 O gas into the quartz reaction vessel, at a temperature range of 300 ° C. from 0.99 ° C., introduced by heat treatment.
In addition, when introducing an H group into the oxygen deficient portion, it is introduced by heat treatment in an H 2 atmosphere gas. For example, it is introduced by annealing at 300 to 400 ° C. under H 2 atmosphere gas.
In addition, when an F group, a Cl group, or a B group is introduced into the oxygen deficient portion, it is introduced by ion implantation (ion implantation) or a plasma treatment method.

 以上、本実施形態の酸化物半導体の製造方法を説明した。 In the above, the manufacturing method of the oxide semiconductor of this embodiment was demonstrated.

 <薄膜トランジスタ310の製造方法>
 次に、本願第5発明の酸化物半導体を用いて薄膜トランジスタ310を製造する方法について説明する。
<Method for Manufacturing Thin Film Transistor 310>
Next, a method for manufacturing the thin film transistor 310 using the oxide semiconductor of the fifth invention of the present application will be described.

 本実施形態の薄膜トランジスタ310の製造方法においては、基板320の上に通常知られた方法でゲート電極330および絶縁体層(ゲート絶縁体層)340を形成した後、絶縁体層340の上面に半導体層350を形成する。この半導体層350は、上述の製法によって製造された酸化物半導体で形成される。また、ゲート電極330は、半導体層350のチャネル領域に対応させて(チャネル領域と平面的に重なる位置に)設けられている。更に、通常知られた方法によって、この半導体層350の一部がソース電極360およびドレイン電極370と重なるように半導体層350上にソース電極360およびドレイン電極370を設けるとともに、更に全体(具体的には、ソース電極360、ドレイン電極370、及びソース電極360とドレイン電極370に重畳していない領域の半導体層350)を層間絶縁膜380で覆う。
 このようにして、発光層からの光照射に対して信頼性の高い薄膜トランジスタ310を製造することができる。
In the method of manufacturing the thin film transistor 310 of this embodiment, the gate electrode 330 and the insulator layer (gate insulator layer) 340 are formed on the substrate 320 by a generally known method, and then the semiconductor is formed on the upper surface of the insulator layer 340. Layer 350 is formed. The semiconductor layer 350 is formed using an oxide semiconductor manufactured by the above-described manufacturing method. The gate electrode 330 is provided so as to correspond to the channel region of the semiconductor layer 350 (at a position overlapping the channel region in a plan view). Further, the source electrode 360 and the drain electrode 370 are provided on the semiconductor layer 350 so that a part of the semiconductor layer 350 overlaps the source electrode 360 and the drain electrode 370 by a generally known method, and further, the whole (specifically, Covers the source electrode 360, the drain electrode 370, and the semiconductor layer 350 in a region not overlapping with the source electrode 360 and the drain electrode 370, with the interlayer insulating film 380.
In this manner, the thin film transistor 310 with high reliability with respect to light irradiation from the light emitting layer can be manufactured.

 以上のような図15に例示した本願第5発明の薄膜トランジスタによれば、新規な酸化物半導体を半導体層に用いることで、特性変化が抑制されたものとなる。 According to the thin film transistor of the fifth invention of this application illustrated in FIG. 15 as described above, the change in characteristics is suppressed by using a novel oxide semiconductor for the semiconductor layer.

 また、このような構成の薄膜トランジスタを用いる半導体装置は、特性変化が抑制された薄膜トランジスタを有するので、高い信頼性を有するものとなる。 In addition, the semiconductor device using the thin film transistor having such a structure has high reliability because it has a thin film transistor in which the characteristic change is suppressed.

 また、以上のような薄膜トランジスタの製造方法によれば、新規な酸化物半導体を半導体層に用い、特性変化が抑制された薄膜トランジスタを容易に製造することができる。 Further, according to the method for manufacturing a thin film transistor as described above, a thin film transistor in which a change in characteristics is suppressed by using a novel oxide semiconductor for a semiconductor layer can be easily manufactured.

 なお、本実施形態においては、いわゆるボトムゲート型の薄膜トランジスタについて説明したが、本願第5発明はいわゆるトップゲート型の薄膜トランジスタに適用することもできる。 In the present embodiment, a so-called bottom gate type thin film transistor has been described. However, the fifth invention of the present application can also be applied to a so-called top gate type thin film transistor.

 また、本実施形態においては、いわゆるトップコンタクト型の薄膜トランジスタについて説明したが、本願第5発明はいわゆるボトムコンタクト型の薄膜トランジスタに適用することもできる。 In this embodiment, a so-called top contact type thin film transistor has been described. However, the fifth invention of the present application can also be applied to a so-called bottom contact type thin film transistor.

 以上、添付図面を参照しながら本願第5発明に係る好適な実施の形態例について説明したが、本願第5発明は斯かる例に限定されないことは言うまでもない。上述した例において示した各構成部材の諸形状や組み合わせ等は一例であって、本願第5発明の主旨から逸脱しない範囲において設計要求等に基づき種々変更可能である。 As described above, the preferred embodiment according to the fifth invention of the present application has been described with reference to the accompanying drawings, but it is needless to say that the fifth invention of the present application is not limited to such an example. Various shapes, combinations, and the like of the constituent members shown in the above-described examples are examples, and various modifications can be made based on design requirements and the like without departing from the gist of the fifth invention of the present application.

 以下に本願第1~第3発明を実施例により説明するが、本願第1~第3発明はこれらの実施例に限定されるものではない。 Hereinafter, the first to third inventions of the present application will be described by examples, but the first to third inventions of the present application are not limited to these examples.

(実施例A1)
 本実施例においては、図2に示す薄膜トランジスタを作製し、動作確認を行った。図に示す薄膜トランジスタは、図1に示した薄膜トランジスタ10と実質的に同様の構成になっており、図1の薄膜トランジスタ10が有するゲート電極30の代わりに、p型不純物を多量にドープしたSi層21を用いる構成となっている。
(Example A1)
In this example, the thin film transistor shown in FIG. 2 was manufactured and the operation was confirmed. The thin film transistor shown in the figure has substantially the same configuration as that of the thin film transistor 10 shown in FIG. 1, and instead of the gate electrode 30 included in the thin film transistor 10 shown in FIG. Is used.

 実施例の薄膜トランジスタは、p型不純物をドープしたSi基板を用い、表面を酸化することで絶縁体層24を形成した後、絶縁体層24の表面に後述の方法を用いて半導体層25を形成することで製造した。ソース電極26およびドレイン電極27は、半導体層25の表面にマスク蒸着することにより形成した。 The thin film transistor of the example uses a Si substrate doped with a p-type impurity, forms the insulator layer 24 by oxidizing the surface, and then forms the semiconductor layer 25 on the surface of the insulator layer 24 using a method described later. It was manufactured by doing. The source electrode 26 and the drain electrode 27 were formed by mask vapor deposition on the surface of the semiconductor layer 25.

 ソース電極26とドレイン電極27は、金(Au)を形成材料とし、厚さは50nmであった。また、ソース電極26とドレイン電極27との離間距離(ゲート長)は350μmであり、対向している部分の長さが940μmであった。 The source electrode 26 and the drain electrode 27 were made of gold (Au) as a forming material and had a thickness of 50 nm. Further, the separation distance (gate length) between the source electrode 26 and the drain electrode 27 was 350 μm, and the length of the facing portion was 940 μm.

 酸化物半導体層25は、SiO濃度が10重量%のIn-Si-OターゲットとTi濃度が10重量%のIn-Ti-Oターゲットを用い、両ターゲットを同一チャンバーへ設置して、プロセスガス流量:O/Ar=3sccm/20sccm、真空度0.25Pa、加熱無しで、表A3に示すように、成膜された膜厚に応じてお互いターゲットについてのスパッタリングパワーを連続的に変えて、膜厚60nmのIn-Ti-Si-O膜を作製した。

Figure JPOXMLDOC01-appb-T000005
The oxide semiconductor layer 25 uses an In—Si—O target with a SiO 2 concentration of 10% by weight and an In—Ti—O target with a Ti concentration of 10% by weight. Flow rate: O 2 / Ar = 3 sccm / 20 sccm, degree of vacuum 0.25 Pa, without heating, as shown in Table A3, continuously changing the sputtering power for each target according to the film thickness formed, An In—Ti—Si—O film with a thickness of 60 nm was formed.
Figure JPOXMLDOC01-appb-T000005

 作製したIn-Ti-Si-O膜の膜中のTi、Si元素の濃度分布を、Arエッチングしながら深さ分解能XPS測定で求められた結果を図4に示す。ゲート絶縁膜24に近い側とソース/ドレイン電極26/27側でTi濃度が高く、Si濃度が低く、そして中央部で逆の濃度勾配になるIn-Ti-Si-O膜が形成できた。 FIG. 4 shows the results obtained by depth resolution XPS measurement of the concentration distribution of Ti and Si elements in the fabricated In—Ti—Si—O film while Ar etching. An In—Ti—Si—O film having a high Ti concentration, a low Si concentration, and a reverse concentration gradient in the central portion was formed on the side close to the gate insulating film 24 and the source / drain electrode 26/27 side.

(実施例A2)
 実施例A1と同様のIn-Si-Oターゲットに用いて、DCパワー200W、加熱無しで、In-Si-O-N膜を作製した。このときのスパッタリングガスの条件は表A4に示すとおりであり、O/Ar=2sccm/30sccmの条件でIn-Si-O膜の成膜を行い、組成を連続的に変化させながらIn-Si-O膜の中央部でのみ、Nガスを導入した(N/Ar=2sccm/30sccm)。この膜のN濃度分布を、Arエッチングしながら深さ分解能XPS測定で求めた結果を図5に示す。

Figure JPOXMLDOC01-appb-T000006
(Example A2)
Using an In—Si—O target similar to that in Example A1, an In—Si—O—N film was produced with a DC power of 200 W and no heating. The conditions of the sputtering gas at this time are as shown in Table A4. An In—Si—O film was formed under the conditions of O 2 / Ar = 2 sccm / 30 sccm, and the In—Si—O film was continuously changed while changing the composition. N 2 gas was introduced only at the center of the —O film (N 2 / Ar = 2 sccm / 30 sccm). FIG. 5 shows the result obtained by measuring the N concentration distribution of this film by depth resolution XPS measurement while performing Ar etching.
Figure JPOXMLDOC01-appb-T000006

(評価)
 実施例A1において作製したIn-Ti-Si-O薄膜トランジスタの特性を評価するため、評価環境25℃、暗所で、Vds=15V一定で、Id-Vg特性より電子移動度(cm/Vs)および初期のしきい値電圧を求めた。続いて、波長420~600nmの光照射を1000sec実施した後の電子移動度およびしきい値電圧のシフト(初期のしきい値電圧との差)を図6に示す。
 実施例A2において作製したIn-Si-O-N薄膜トランジスタの特性を評価するため、評価環境25℃、光照射を1000秒した後のId-Vg特性を測定した。結果を、図7に示す。
 比較として、In-Ti-O薄膜トランジスタのId-Vg特性を併せて図7に示す。波長420~600nmの光照射によって、In-Ti-OはIoff値が増加し、かつしきい値電圧も負側へシフトすることが分かる。一方、In-Si-O-N薄膜トランジスタは、光照射後でも、光照射前とほぼ同様の特性で、劣化はほとんど認められなかった。
 なお、光照射前のIn-Si-O-N薄膜トランジスタ及びIn-Ti-O薄膜トランジスタのId-Vg特性は、図7中の破線で示したものと略同一であった。
(Evaluation)
In order to evaluate the characteristics of the In-Ti-Si-O thin film transistor manufactured in Example A1, the electron mobility (cm 2 / Vs) is determined from the Id-Vg characteristics, in an evaluation environment of 25 ° C., in the dark, with Vds = 15 V constant. The initial threshold voltage was determined. Subsequently, FIG. 6 shows the electron mobility and threshold voltage shift (difference from the initial threshold voltage) after 1000 seconds of light irradiation with a wavelength of 420 to 600 nm.
In order to evaluate the characteristics of the In—Si—O—N thin film transistor manufactured in Example A2, the Id—Vg characteristics after an evaluation environment of 25 ° C. and light irradiation for 1000 seconds were measured. The results are shown in FIG.
For comparison, FIG. 7 also shows the Id—Vg characteristics of an In—Ti—O thin film transistor. It can be seen that by irradiation with light having a wavelength of 420 to 600 nm, the I-off value of In—Ti—O increases and the threshold voltage also shifts to the negative side. On the other hand, the In—Si—O—N thin film transistor had almost the same characteristics after light irradiation as before light irradiation, and hardly deteriorated.
Note that the Id-Vg characteristics of the In—Si—O—N thin film transistor and the In—Ti—O thin film transistor before light irradiation were substantially the same as those indicated by the broken line in FIG.

 比較として、金属半導体層のみをIn-Ga-Zn-O(IGZO)に変え、他は実施例A1と同様の薄膜トランジスタについて測定した電子移動度、及びしきい値電圧シフトのデータをプロットした。この薄膜トランジスタの60nm膜厚のIGZO膜は、IGZOターゲット(In:Ga:ZnO=1:1:1 (mol比))を用いたDCスパッタリング法で、室温、スパッタリングガス流量:Ar/O=21.5sccm/1.5sccm、DCパワー100Wの条件で作製した。
 結果を併せて図6に示す。IGZOを用いた薄膜トランジスタは、光照射によるしきい値電圧のシフトが約2Vと大きく、電子移動度も5cm/Vsと小さな値を示した。一方、実施例A1のIn-Ti-Si-Oを用いた薄膜トランジスタは、しきい値電圧のシフトが1Vよりも小さく、電子移動度も10cm/Vsに近い高い値を示した。
 また、実施例A1のIn-Ti-Si-Oを用いた薄膜トランジスタは、ソース電極26及び/ドレイン電極27と半導体層25との界面におけるコンタクト抵抗が低く、かつ、優れたゲート制御性を有していた。
For comparison, only the metal semiconductor layer was changed to In—Ga—Zn—O (IGZO), and the other data plotted were the electron mobility and threshold voltage shift data measured for the same thin film transistor as in Example A1. The 60 nm-thick IGZO film of this thin film transistor is a DC sputtering method using an IGZO target (In 2 O 3 : Ga 2 O 3 : ZnO = 1: 1: 1 (mol ratio)) at room temperature and a sputtering gas flow rate: It was produced under the conditions of Ar / O 2 = 21.5 sccm / 1.5 sccm and DC power of 100 W.
The results are also shown in FIG. The thin film transistor using IGZO has a large threshold voltage shift of about 2 V due to light irradiation, and the electron mobility is as small as 5 cm 2 / Vs. On the other hand, the thin film transistor using In—Ti—Si—O of Example A1 showed a high threshold voltage shift smaller than 1 V and an electron mobility close to 10 cm 2 / Vs.
In addition, the thin film transistor using In—Ti—Si—O of Example A1 has low contact resistance at the interface between the source electrode 26 / drain electrode 27 and the semiconductor layer 25, and has excellent gate controllability. It was.

 以上の結果から、本願第1~第3発明の薄膜トランジスタの動作確認ができ、本願第1~第3発明の有用性が確かめられた。 From the above results, the operation of the thin film transistor of the first to third inventions of the present application was confirmed, and the usefulness of the first to third inventions of the present application was confirmed.

 以下に本願第4発明を実施例により説明するが、本願第4発明はこれらの実施例に限定されるものではない。 Hereinafter, the fourth invention of the present application will be described by examples, but the fourth invention of the present application is not limited to these examples.

[第1の実施例(実施例B1)]
 上記第1の実施形態に対応する本実施例においては、図10に示す薄膜トランジスタを作製し、動作確認を行った。図に示す薄膜トランジスタは、図8に示した薄膜トランジスタ201と同様の構成になっており、図8の薄膜トランジスタ201が有するゲート電極203の代わりに、p型不純物を多量にドープしたSi層211を用いる構成となっている。
[First Example (Example B1)]
In this example corresponding to the first embodiment, the thin film transistor shown in FIG. 10 was manufactured and the operation was confirmed. The thin film transistor shown in the figure has the same structure as that of the thin film transistor 201 shown in FIG. 8, and uses a Si layer 211 doped with a large amount of p-type impurities in place of the gate electrode 203 included in the thin film transistor 201 shown in FIG. It has become.

 実施例の薄膜トランジスタは、p型不純物をドープしたSi基板を用い、表面を酸化することで絶縁体層204を形成した後、絶縁体層204の表面に後述の方法を用いて半導体層205を形成することで製造した。ソース電極208およびドレイン電極209は、半導体層205の表面にマスク蒸着することにより形成した。 The thin film transistor of the example uses a Si substrate doped with a p-type impurity, forms the insulator layer 204 by oxidizing the surface, and then forms the semiconductor layer 205 on the surface of the insulator layer 204 using a method described later. It was manufactured by doing. The source electrode 208 and the drain electrode 209 were formed by mask vapor deposition on the surface of the semiconductor layer 205.

 ソース電極208とドレイン電極209は、金(Au)を形成材料とし、厚さは50nmであった。また、ソース電極208とドレイン電極209との離間距離(ゲート長)は350μmであり、対向している部分の長さが940μmであった。 The source electrode 208 and the drain electrode 209 are made of gold (Au) and have a thickness of 50 nm. Further, the separation distance (gate length) between the source electrode 208 and the drain electrode 209 was 350 μm, and the length of the facing portion was 940 μm.

 半導体層205は、スパッタリング装置を用い、ターゲット材として、Sn-W-Oターゲットを用いて以下のスパッタ条件でスパッタリング法(DCスパッタリング)により成膜した。Sn-W-Oターゲットは、20%W添加Sn系のサンプル品を用いた。成膜した半導体層205の厚さは20nmであった。 The semiconductor layer 205 was formed by a sputtering method (DC sputtering) using a sputtering apparatus and using a Sn—W—O target as a target material under the following sputtering conditions. As the Sn—W—O target, a 20% W-added Sn-based sample product was used. The thickness of the deposited semiconductor layer 205 was 20 nm.

 (スパッタリング条件)
 DC power  :200W
 真空度      :0.2Pa
 プロセスガス流量 :Ar 20sccm/O 2sccm
           (sccm:Standard Cubic Centimeter per Minute)
 基板温度     :25℃。加熱なし
(Sputtering conditions)
DC power: 200W
Degree of vacuum: 0.2 Pa
Process gas flow rate: Ar 20 sccm / O 2 2 sccm
(Sccm: Standard Cubic Centimeter per Minute)
Substrate temperature: 25 ° C. Without heating

 このようにして作製した薄膜トランジスタの特性は、評価環境を25℃、暗所、真空中として測定した。図11はこの薄膜トランジスタの伝達特性の測定結果を示す。 The characteristics of the thin film transistor thus fabricated were measured under the evaluation environment of 25 ° C. in a dark place and in a vacuum. FIG. 11 shows the measurement results of the transfer characteristics of this thin film transistor.

 また、上記のスパッタリング条件で、O/(Ar+O)の比率を5~25%の範囲で変えた場合のSn-OおよびSn-W-O系薄膜トランジスタの電気伝導の特性を図12に示す。Sn-W-Oは、図12の全ての酸素比率で、Sn-Oに比べて優れた電気伝導性を示す。これは、W-O結合の酸素かい離エネルギー(720±71kJ/mol)が、Sn-Oの酸素かい離エネルギー(528kJ/mol)に比べて大きいために、酸化錫(Sn-O)から精度良く適した酸素を脱離して酸素欠損量を制御できた効果である。また、Sn-W-Oの方が、O/(Ar+O)の比率の変化に対して電気伝導特性の変化が少ないことを示している。この結果から、Sn-W-Oの方がプロセスマージンが大きいことがわかる。 In addition, FIG. 12 shows the electrical conduction characteristics of Sn—O and Sn—W—O thin film transistors when the ratio of O 2 / (Ar + O 2 ) is changed in the range of 5 to 25% under the above sputtering conditions. . Sn—W—O exhibits superior electrical conductivity compared to Sn—O at all oxygen ratios in FIG. This is suitable from tin oxide (Sn—O) with high accuracy because the oxygen dissociation energy of W—O bond (720 ± 71 kJ / mol) is larger than that of Sn—O (528 kJ / mol). This is the effect of controlling the amount of oxygen deficiency by desorbing oxygen. In addition, Sn—W—O indicates that the change in electrical conduction characteristics is smaller than the change in the ratio of O 2 / (Ar + O 2 ). From this result, it can be seen that Sn—W—O has a larger process margin.

[第2の実施例(実施例B2)]
 上記第2の実施形態に対応する本実施例においても、図10に示す薄膜トランジスタを作製し、動作確認を行った。半導体層205は、スパッタリング装置を用い、ターゲット材として、Sn-W-Yb-Oターゲットを用いて以下のスパッタ条件でスパッタリング法(DCスパッタリング)により成膜した。Sn-W-Oターゲットは、20%Wおよび2%Yb添加Sn系のサンプル品を用いた。成膜した半導体層205の厚さは20nmであった。
[Second Example (Example B2)]
Also in this example corresponding to the second embodiment, the thin film transistor shown in FIG. 10 was manufactured and the operation was confirmed. The semiconductor layer 205 was formed by a sputtering method (DC sputtering) using a sputtering apparatus and using a Sn—W—Yb—O target as a target material under the following sputtering conditions. As the Sn—W—O target, 20% W and 2% Yb-added Sn-based sample products were used. The thickness of the deposited semiconductor layer 205 was 20 nm.

 (スパッタリング条件)
 DC power  :150W
 真空度      :0.2Pa
 プロセスガス流量 :Ar 20sccm/O 2sccm
           (sccm:Standard Cubic Centimeter per Minute)
 基板温度     :25℃。加熱なし
(Sputtering conditions)
DC power: 150W
Degree of vacuum: 0.2 Pa
Process gas flow rate: Ar 20 sccm / O 2 2 sccm
(Sccm: Standard Cubic Centimeter per Minute)
Substrate temperature: 25 ° C. Without heating

 Sn-W-Yb-O膜の後熱処理による結晶構造を調べるために、膜厚20nmのSn-W-O膜をガラス基板上に作製して、大気中、450℃で15分熱処理したX線回折パターンを図13に示す。比較としてガラス基板のみも示す。450℃で15分熱処理しても何のピークも認められないことより、非晶質であることが分かった。 In order to investigate the crystal structure of the Sn—W—Yb—O film by post-heat treatment, a 20 nm-thick Sn—W—O film was formed on a glass substrate and heat-treated at 450 ° C. for 15 minutes in the atmosphere. The diffraction pattern is shown in FIG. Only a glass substrate is also shown for comparison. Even when heat-treated at 450 ° C. for 15 minutes, no peak was observed, indicating that the film was amorphous.

 また、この非晶質なSn-W-Yb-O膜を用いて作製した薄膜トランジスタの特性は、評価環境を25℃、暗所、真空中として測定した。図14は本願第4発明の薄膜トランジスタの特性を測定した結果を示す。 The characteristics of the thin film transistor manufactured using this amorphous Sn—W—Yb—O film were measured under the evaluation environment of 25 ° C. in a dark place and in a vacuum. FIG. 14 shows the results of measuring the characteristics of the thin film transistor of the fourth invention.

 以上の結果から、本願第4発明の薄膜トランジスタの動作確認ができ、本願第4発明の有用性が確かめられた。 From the above results, the operation of the thin film transistor of the fourth invention of the present application was confirmed, and the usefulness of the fourth invention of the present application was confirmed.

 以下に本願第5発明を実施例Cにより説明するが、本願第5発明はこれらの実施例に限定されるものではない。 Hereinafter, the fifth invention of the present application will be described by Example C, but the fifth invention of the present application is not limited to these Examples.

 本実施例Cにおいては、図16に示す薄膜トランジスタ400を作製し、動作確認を行った。図16に示す薄膜トランジスタ400では、図15のゲート電極330の代わりに、p型不純物を多量にドープしたSi層である基板450をゲート電極として使用する構成となっている。 In Example C, the thin film transistor 400 shown in FIG. 16 was manufactured and the operation was confirmed. In the thin film transistor 400 shown in FIG. 16, a substrate 450 that is a Si layer doped with a large amount of p-type impurities is used as the gate electrode instead of the gate electrode 330 shown in FIG.

 実施例Cの薄膜トランジスタは、p型不純物をドープしたSi基板450を用い、表面を酸化することで絶縁体層410を形成した後、絶縁体層410の表面に後述の方法を用いて酸化物半導体の半導体層420を形成することで製造した。ソース電極430およびドレイン電極440は、酸化物半導体の半導体層420の表面にマスク蒸着することにより形成した。 The thin film transistor of Example C uses a Si substrate 450 doped with a p-type impurity, forms an insulator layer 410 by oxidizing the surface, and then forms an oxide semiconductor on the surface of the insulator layer 410 using a method described later. The semiconductor layer 420 was formed. The source electrode 430 and the drain electrode 440 were formed by mask vapor deposition on the surface of the semiconductor layer 420 of an oxide semiconductor.

 ソース電極430とドレイン電極440は、金(Au)を形成材料とし、厚さは50nmであった。またソース電極430とドレイン電極440との離間距離(ゲート長)は350μmであり、対向している部分の長さが940μmであった。 The source electrode 430 and the drain electrode 440 are made of gold (Au) and have a thickness of 50 nm. Further, the distance (gate length) between the source electrode 430 and the drain electrode 440 was 350 μm, and the length of the facing portion was 940 μm.

 本実施例Cにおいては、酸化物半導体の半導体層420を以下のようにして作製した。 In this example C, an oxide semiconductor layer 420 was fabricated as follows.

 <In-OH結合を有するIn-Si-O半導体の半導体層420の作製>
 In-OH結合を有するIn-Si-O半導体の半導体層420は、以下のようにして作製した。
 まず、酸素欠損を導入したIn-Si-O半導体を、スパッタリング装置を用いて、ターゲット材としてSiO含有量が10重量%のIn-Si-Oターゲットを用いて、O/Ar=3sccm/20sccm、真空度0.25Pa、加熱無しのスパッタリング条件下で、膜厚60nmのIn-Si-O膜を作製し、続いて、大気中、150℃で10分間の熱処理を施すことにより作製した。
 次に、密閉した石英反応容器へHOガスを導入した80%以上の高湿度下、150℃から300℃の温度範囲で、熱処理して、酸素欠損部に-OH基を導入することによりIn-OH結合を有するIn-Si-O半導体の半導体層420を作製した。本実施例Cで導入したOH基の含有量は0.5%とした。その確認は、インジウム3d軌道起因のXPSスペクトル(以後、「In3d XPSスペクトル」と称する)によって行った。
 図17に、150℃での上記熱処理前後におけるIn-Si-O膜のIn3d XPSスペクトルの結果を示す。図17において、(a)は上記熱処理前のIn-Si-O半導体のIn3dXPSスペクトルであり、(b)は上記熱処理後のIn-OH結合を有するIn-Si-O半導体のIn3dXPSスペクトルである。図17に見られる通り、上記熱処理後の-OH基を導入したIn-Si-O半導体におけるIn-OH結合に起因するピーク位置は、444eVに認められ、上記熱処理前のIn-Si-O半導体におけるIn-O結合に起因するピーク位置は443.5eVに認められる。したがって、上記熱処理後の-OH基を導入したIn-Si-O半導体におけるIn-OH結合に起因するピーク位置は、上記熱処理前のIn-Si-O半導体におけるIn-O結合に起因するピーク位置に対して、高エネルギー側へシフトしていることがわかる。
 導入するOH基の含有量は0.1%以上10%以下が好ましい。10%以下になるとモバイルイオン(ここで、「モバイルイオン」とは、電圧の正負の印加に対応して、酸化物中で局在化したイオンを意味する。)の発生源を回避することができ、半導体の性質よりもより金属的な振る舞いとなるのを防ぐことができるからである。
<Fabrication of In—Si—O Semiconductor Semiconductor Layer 420 with In—OH Bond>
The semiconductor layer 420 of an In—Si—O semiconductor having an In—OH bond was manufactured as follows.
First, an In—Si—O semiconductor into which oxygen vacancies have been introduced is used by using a sputtering apparatus and an In—Si—O target having a SiO 2 content of 10 wt% as a target material, and O 2 / Ar = 3 sccm / An In—Si—O film having a thickness of 60 nm was formed under sputtering conditions of 20 sccm, a degree of vacuum of 0.25 Pa, and no heating, followed by heat treatment at 150 ° C. for 10 minutes in the atmosphere.
Next, by introducing H 2 O gas into a sealed quartz reaction vessel under a high humidity of 80% or more in a temperature range of 150 ° C. to 300 ° C., and introducing —OH groups into oxygen deficient portions. A semiconductor layer 420 of an In—Si—O semiconductor having an In—OH bond was manufactured. The OH group content introduced in Example C was 0.5%. The confirmation was performed by an XPS spectrum derived from the indium 3d orbital (hereinafter referred to as “In3d XPS spectrum”).
FIG. 17 shows the results of In3d XPS spectra of the In—Si—O film before and after the heat treatment at 150 ° C. In FIG. 17, (a) is an In3dXPS spectrum of an In—Si—O semiconductor before the heat treatment, and (b) is an In3dXPS spectrum of an In—Si—O semiconductor having an In—OH bond after the heat treatment. As can be seen from FIG. 17, the peak position due to the In—OH bond in the In—Si—O semiconductor into which the —OH group was introduced after the heat treatment was found at 444 eV, and the In—Si—O semiconductor before the heat treatment was observed. The peak position due to the In—O bond in is observed at 443.5 eV. Therefore, the peak position due to the In—OH bond in the In—Si—O semiconductor into which the —OH group is introduced after the heat treatment is the peak position due to the In—O bond in the In—Si—O semiconductor before the heat treatment. On the other hand, it turns out that it has shifted to the high energy side.
The content of OH groups to be introduced is preferably 0.1% or more and 10% or less. If it becomes 10% or less, it is possible to avoid a source of mobile ions (herein, “mobile ions” means ions localized in the oxide corresponding to the application of positive and negative voltages). This is because the metal behavior can be prevented from being more than the property of the semiconductor.

 <In-H結合を有するIn-Si-O半導体の半導体層の作製>
 酸素欠損を導入したIn-Si-O半導体へのH基の導入に関しても、OH基の導入と同じやり方で、酸素欠損を導入したIn-Si-O半導体を最初に作製した。
 次に、この酸素欠損を導入したIn-Si-O半導体を、H雰囲気ガス下で300~400℃のアニール処理し、それによって酸素欠損部にH基を導入してIn-H結合を有するIn-Si-O半導体の半導体層420を作製した。その確認は、その確認は、In3d XPSスペクトルによって行った。
 導入するH基の含有量は、半導体的性質を維持するために0%よりも大きく0.1%以下が好ましい。
<Fabrication of In—Si—O Semiconductor Semiconductor Layer Having In—H Bond>
Regarding introduction of H groups into an In—Si—O semiconductor into which oxygen vacancies were introduced, an In—Si—O semiconductor into which oxygen vacancies were introduced was first produced in the same manner as the introduction of OH groups.
Next, the In—Si—O semiconductor into which oxygen vacancies have been introduced is annealed at 300 to 400 ° C. in an H 2 atmosphere gas, thereby introducing H groups into the oxygen vacancy and having In—H bonds. A semiconductor layer 420 of an In—Si—O semiconductor was manufactured. The confirmation was performed by In3d XPS spectrum.
The content of H group to be introduced is preferably greater than 0% and 0.1% or less in order to maintain semiconducting properties.

 <In-F、In-Cl、In-B結合を少なくとも1つ有するIn-Si-O半導体の半導体層の作製>
 酸素欠損を導入したIn-Si-O半導体へのF、Cl、B基の導入に関しても、OH基の導入と同じやり方で、酸素欠損を導入したIn-Si-O半導体を最初に作製した。
 次に、この酸素欠損を導入したIn-Si-O半導体に対して、F、Cl、Bのいずれか少なくとも一つのイオンを1×1018atoms/cm以上1×1021atoms/cm以下の含有量の範囲でイオン注入し、それによって酸素欠損部にF、Cl、Bのいずれか少なくとも一つの基を導入させてIn-F、In-Cl、In-B結合を少なくとも1つ有するIn-Si-O半導体の半導体層420を作製した。その確認は、In3d XPSスペクトルによって行った。
 因みに、これらイオンの導入法としては、イオン注入の代わりにプラズマ処理法を用いてもよい。
<Fabrication of In—Si—O Semiconductor Semiconductor Layer Having At least One In—F, In—Cl, In—B Bond>
Regarding the introduction of F, Cl, and B groups into an In—Si—O semiconductor into which oxygen vacancies were introduced, an In—Si—O semiconductor into which oxygen vacancies were introduced was first produced in the same manner as the introduction of OH groups.
Next, at least one ion of F, Cl, and B is added to the In—Si—O semiconductor into which oxygen vacancies are introduced at 1 × 10 18 atoms / cm 3 or more and 1 × 10 21 atoms / cm 3 or less. In the case of In which has at least one In-F, In-Cl, or In-B bond by ion-implanting within the range of the content of at least one of them, thereby introducing at least one group of F, Cl, and B into the oxygen deficient portion. A semiconductor layer 420 of —Si—O semiconductor was produced. The confirmation was performed by In3d XPS spectrum.
Incidentally, as a method for introducing these ions, a plasma processing method may be used instead of ion implantation.

 <In-OH結合を有するIn-Si-O半導体を用いた薄膜トランジスタの信頼性評価>
 上述の方法によって作製したIn-OH結合を有するIn-Si-O半導体(OH含有量:0.5%)を用いて作製した図16に示す薄膜トランジスタの特性は、評価環境を25℃、Vds(ドレイン電圧)=15V(一定)として、I(ドレイン電流)-V(ゲート電圧)特性によって評価した。比較の為に、OH基を導入していないIn-Si-O半導体を用いた点だけが異なる薄膜トランジスタも作製した。
 図18は、420nm以上600nm以下の波長を有する光照射を100秒間実施した後のI-V特性を示した結果である。図18の(a)は、光照射前のOH基を導入していないIn-Si-O半導体と光照射前のIn-OH結合を有するIn-Si-O半導体のI-V特性を示し、(b)は、 光照射後のIn-OH結合を有するIn-Si-O半導体のI-V特性を示し、(c)は、光照射後のOH基を導入していないIn-Si-O半導体のI-V特性を示す。
 図18に示す通り、光照射前後のIn-OH結合を有するIn-Si-O半導体を用いた薄膜トランジスタのI-V特性は、両者ともとほぼ一致していた。一方、OH基を導入していないIn-Si-O半導体を用いた薄膜トランジスタの光照射前後のI-V特性は、光照射前と比べてIカーブが負側へシフトし、またオフ電流(Ioff)値も上昇する傾向を示していた。
 そのため、OH基を導入していないIn-Si-O半導体を用いた薄膜トランジスタでは、420nm以上600nm以下の波長を有する光照射に対して「しきい値電圧のシフト」が十分に抑制できないけれども、OH基を導入すれば、「しきい値電圧のシフト」を十分に抑制できることがわかった。
<Reliability evaluation of thin film transistor using In—Si—O semiconductor having In—OH bond>
The characteristics of the thin film transistor illustrated in FIG. 16 manufactured using an In—Si—O semiconductor having an In—OH bond (OH content: 0.5%) manufactured by the above-described method are as follows: evaluation environment is 25 ° C., V ds (Drain voltage) = 15 V (constant), and evaluation was performed based on I d (drain current) −V g (gate voltage) characteristics. For comparison, thin film transistors that differ only in the use of In—Si—O semiconductors into which OH groups were not introduced were also produced.
FIG. 18 shows the result of showing the I d -V g characteristics after irradiation with light having a wavelength of 420 nm or more and 600 nm or less for 100 seconds. FIG. 18A shows the I d -V g characteristics of an In—Si—O semiconductor into which OH groups have not been introduced before light irradiation and an In—Si—O semiconductor having an In—OH bond before light irradiation. (B) shows the I d -V g characteristics of an In—Si—O semiconductor having an In—OH bond after light irradiation, and (c) shows an In group in which no OH group has been introduced after light irradiation. The I d -V g characteristic of the —Si—O semiconductor is shown.
As shown in FIG. 18, the I d -V g characteristics of the thin film transistor using the In—Si—O semiconductor having In—OH bonds before and after the light irradiation were almost the same. On the other hand, the I d -V g characteristics before and after the light irradiation of the thin film transistor using an In—Si—O semiconductor into which no OH group is introduced show that the I d curve shifts to the negative side compared to before the light irradiation, and is off. The current (I off ) value also tended to increase.
Therefore, a thin film transistor using an In—Si—O semiconductor into which no OH group has been introduced cannot sufficiently suppress “threshold voltage shift” with respect to light irradiation having a wavelength of 420 nm to 600 nm. It was found that the “threshold voltage shift” can be sufficiently suppressed by introducing a group.

 本願第1~第3発明は、光照射によるしきい値電流のシフト等の特性劣化が抑制され、ソース電極及び/又はドレイン電極と半導体層との界面におけるコンタクト抵抗が低く、かつ電子移動度が高くゲート制御性に優れるという、実用上高い価値を有する特性を兼ね備えた薄膜トランジスタを提供することが可能であり、液晶ディスプレイや有機ELディスプレイ等の表示機器をはじめとする産業の各分野において高い利用可能性を有する。 In the first to third inventions of the present application, characteristic deterioration such as shift of threshold current due to light irradiation is suppressed, contact resistance at the interface between the source electrode and / or drain electrode and the semiconductor layer is low, and electron mobility is low. It is possible to provide thin film transistors that have high practical value, such as high gate control, and can be used in various industrial fields including liquid crystal displays and organic EL displays. Have sex.

 また、以上説明したように、本願第4発明によれば、酸素欠損量を制御した複合金属酸化物の半導体層を実現することができるので、薄膜トランジスタの性能向上に大いに貢献することが可能である。 In addition, as described above, according to the fourth invention of the present application, since it is possible to realize a composite metal oxide semiconductor layer in which the amount of oxygen vacancies is controlled, it is possible to greatly contribute to improving the performance of the thin film transistor. .

 更に、以上説明したように、本願第5発明によれば、発光層からの発光で誘発される「しきい値電圧のシフト」も十分に抑制できる酸化物半導体を提供することができるので、発光層からの光照射に対する信頼性の向上が望まれている薄膜トランジスタのような半導体素子や、有機ELディスプレイや液晶ディスプレイの電子機器等の半導体装置に適用可能である。 Furthermore, as described above, according to the fifth invention of the present application, it is possible to provide an oxide semiconductor that can sufficiently suppress a “threshold voltage shift” induced by light emission from the light emitting layer. The present invention can be applied to a semiconductor device such as a semiconductor element such as a thin film transistor and an electronic device such as an organic EL display or a liquid crystal display for which improvement in reliability with respect to light irradiation from a layer is desired.

110、110’ 薄膜トランジスタ
120     基板
121     pドープSi層
130     ゲート電極
140、124  絶縁膜層
150、125  半導体層
160、126  ソース電極
170、127  ドレイン電極
180     層間絶縁膜
201、201’---薄膜トランジスタ
202---基板
203---ゲート電極
204---絶縁膜層
205、205’---半導体層
206---酸化錫
207---金属酸化物
208---ソース電極
209---ドレイン電極
210---酸化物
211---p型不純物をドープしたSi基板
310、400---薄膜トランジスタ
320---基板
330---ゲート電極
340、410---絶縁体層
350、420---半導体層
360、430---ソース電極
370、440---ドレイン電極
380---層間絶縁膜
450---p型不純物を多量にドープしたSi層基板(ゲート電極)
 
110, 110 'thin film transistor 120 substrate 121 p-doped Si layer 130 gate electrode 140, 124 insulating film layer 150, 125 semiconductor layer 160, 126 source electrode 170, 127 drain electrode 180 interlayer insulating film 201, 201'-thin film transistor 202- --Substrate 203 --- Gate electrode 204 --- Insulating film layer 205, 205 '--- Semiconductor layer 206 --- Tin oxide 207 --- Metal oxide 208 --- Source electrode 209 --- Drain electrode 210 --- oxide 211 --- Si substrate 310 doped with p-type impurities, 400 --- thin film transistor 320 --- substrate 330 --- gate electrodes 340, 410 --- insulator layers 350, 420-- -Semiconductor layers 360, 430--source electrodes 370, 440--drain electrodes 380--interlayer insulating film 450--Si layer substrate doped with a large amount of p-type impurities (gate Electrode)

Claims (57)

 ソース電極およびドレイン電極と、
 前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、
 前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、
 前記ゲート電極と前記半導体層との間に設けられた絶縁体層と
を有する薄膜トランジスタであって、
 前記半導体層が、酸素欠損が導入されることで電子キャリアを生成できる第1金属酸化物に、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物(XOx)を添加した複合金属酸化物で形成され、
 前記第2酸化物を構成する元素Xのうち、ケイ素、タンタル、ジルコニウム、ハフニウム、アルミニウム、イットリウム及び希土類元素からなる群より選ばれる少なくとも一種の元素Xの濃度が、前記半導体層の厚み方向の中央部において極大値を示す、上記薄膜トランジスタ。
A source electrode and a drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
A thin film transistor having an insulator layer provided between the gate electrode and the semiconductor layer,
The semiconductor layer has a second metal oxide that can generate electron carriers by introducing oxygen vacancies, and the second energy of oxygen is 200 kJ / mol or more higher than that of the first metal oxide. Formed of a complex metal oxide to which an oxide (XOx) is added,
Among the elements X constituting the second oxide, the concentration of at least one element X 1 selected from the group consisting of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements is in the thickness direction of the semiconductor layer. The thin film transistor, which exhibits a maximum value in the center.
前記元素Xの濃度が、前記半導体層の厚み方向の中央部において最大値を示す、請求項1に記載の薄膜トランジスタ。 2. The thin film transistor according to claim 1, wherein the concentration of the element X <b> 1 exhibits a maximum value at a central portion in a thickness direction of the semiconductor layer.  ソース電極およびドレイン電極と、
 前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、
 前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、
 前記ゲート電極と前記半導体層との間に設けられた絶縁体層と
を有する薄膜トランジスタであって、
 前記半導体層が、酸素欠損が導入されることで電子キャリアを生成できる第1金属酸化物に、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物(XOx)を添加した複合金属酸化物で形成され、
 前記第2酸化物を構成する元素Xのうち、ケイ素、タンタル、ジルコニウム、ハフニウム、アルミニウム、イットリウム及び希土類元素のいずれにも該当しない少なくとも一種の元素Xの濃度が、前記半導体層の厚み方向の中央部において極小値を示す、上記薄膜トランジスタ。
A source electrode and a drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
A thin film transistor having an insulator layer provided between the gate electrode and the semiconductor layer,
The semiconductor layer has a second metal oxide that can generate electron carriers by introducing oxygen vacancies, and the second energy of oxygen is 200 kJ / mol or more higher than that of the first metal oxide. Formed of a complex metal oxide to which an oxide (XOx) is added,
Among the elements X constituting the second oxide, the concentration of at least one element X 2 that does not correspond to any of silicon, tantalum, zirconium, hafnium, aluminum, yttrium, and rare earth elements is in the thickness direction of the semiconductor layer. The thin film transistor, which exhibits a minimum value in the center.
前記元素Xの濃度が、前記半導体層の厚み方向の中央部において最小値を示す、請求項3に記載の薄膜トランジスタ。 4. The thin film transistor according to claim 3, wherein the concentration of the element X 2 has a minimum value at a central portion in a thickness direction of the semiconductor layer.  ソース電極およびドレイン電極と、
 前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、
 前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、
 前記ゲート電極と前記半導体層との間に設けられた絶縁体層と
を有する薄膜トランジスタであって、
 前記半導体層が、酸素欠損が導入されることで電子キャリアを生成できる第1金属酸化物に、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物(XOx)を添加した複合金属酸化物で形成され、
 前記半導体層が、更に窒素を含有し、窒素の濃度が、前記半導体層の厚み方向の中央部において極大値を示す、上記薄膜トランジスタ。
A source electrode and a drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
A thin film transistor having an insulator layer provided between the gate electrode and the semiconductor layer,
The semiconductor layer has a second metal oxide that can generate electron carriers by introducing oxygen vacancies, and the second energy of oxygen is 200 kJ / mol or more higher than that of the first metal oxide. Formed of a complex metal oxide to which an oxide (XOx) is added,
The above-mentioned thin film transistor, wherein the semiconductor layer further contains nitrogen, and the concentration of nitrogen shows a maximum value at a central portion in the thickness direction of the semiconductor layer.
 前記第2酸化物の酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも255kJ/mol以上大きい、請求項1から5のいずれか一項に記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 1 to 5, wherein an oxygen separation energy of the second oxide is greater by 255 kJ / mol or more than an oxygen separation energy of the first metal oxide.  前記第1金属酸化物は、インジウム、ガリウム、亜鉛、および錫からなる群から選択された少なくとも一つの金属の酸化物である、請求項1から5のいずれか一項に記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 1 to 5, wherein the first metal oxide is an oxide of at least one metal selected from the group consisting of indium, gallium, zinc, and tin.  前記第2酸化物は、ジルコニウム(Zr)、およびプラセオジム(Pr)からなる群から選択された少なくとも一つの金属の酸化物である、請求項1から5のいずれか一項に記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 1 to 5, wherein the second oxide is an oxide of at least one metal selected from the group consisting of zirconium (Zr) and praseodymium (Pr).  前記第2酸化物は、ケイ素(Si)、タンタル(Ta)、ランタン(La)、およびハフニウム(Hf)からなる群から選択された少なくとも一つの酸化物である、請求項6に記載の薄膜トランジスタ。 The thin film transistor according to claim 6, wherein the second oxide is at least one oxide selected from the group consisting of silicon (Si), tantalum (Ta), lanthanum (La), and hafnium (Hf).  前記半導体層における前記第2酸化物の含有量が0より大きく50重量%以下である、請求項1から9の何れかに記載の薄膜トランジスタ。 10. The thin film transistor according to claim 1, wherein the content of the second oxide in the semiconductor layer is greater than 0 and 50 wt% or less.  前記半導体層における前記第2酸化物の含有量が0より大きく5重量%以下である、請求項1から10の何れかに記載の薄膜トランジスタ。 11. The thin film transistor according to claim 1, wherein the content of the second oxide in the semiconductor layer is greater than 0 and 5% by weight or less.  前記半導体層が非晶質である、請求項1から11の何れかに記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 1 to 11, wherein the semiconductor layer is amorphous.  前記半導体層の厚さが5nm以上かつ20nm以下の範囲である、請求項1から12の何れかに記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 1 to 12, wherein a thickness of the semiconductor layer is in a range of 5 nm or more and 20 nm or less.  前記第2酸化物が、ボロン(B)および炭素(C)からなる群から選択された少なくとも一つの元素の酸化物である、請求項1から5のいずれか1項に記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 1 to 5, wherein the second oxide is an oxide of at least one element selected from the group consisting of boron (B) and carbon (C).  前記半導体層中のボロン(B)および炭素(C)の含有量が0より大きく10重量%以下である、請求項14に記載の薄膜トランジスタ。 The thin film transistor according to claim 14, wherein the content of boron (B) and carbon (C) in the semiconductor layer is greater than 0 and 10 wt% or less.  前記半導体層が10℃以上400℃以下の温度で形成される、
請求項1から15の何れか1項に記載の薄膜トランジスタの製造方法。
The semiconductor layer is formed at a temperature of 10 ° C. or higher and 400 ° C. or lower;
The method for manufacturing a thin film transistor according to claim 1.
 前記半導体層が10℃以上200℃以下の温度で形成される、請求項16に記載の薄膜トランジスタの製造方法。 The method for manufacturing a thin film transistor according to claim 16, wherein the semiconductor layer is formed at a temperature of 10 ° C or higher and 200 ° C or lower.  請求項1から15のいずれか1項に記載の薄膜トランジスタを有する装置。 An apparatus having the thin film transistor according to any one of claims 1 to 15.  液晶ディスプレイ又は有機ELディスプレイである、請求項18に記載の装置。 The apparatus according to claim 18, which is a liquid crystal display or an organic EL display.  ソース電極およびドレイン電極と、
 前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、
 前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、
 前記ゲート電極と前記半導体層との間に設けられた絶縁体層と
を設け、
 前記半導体層が、酸化錫に、酸素のかい離エネルギーが酸化錫より大きくかつ酸化錫の酸素のかい離エネルギーとの差が200kJ/mol未満である金属酸化物を添加した複合金属酸化物である
薄膜トランジスタ。
A source electrode and a drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
Providing an insulator layer provided between the gate electrode and the semiconductor layer;
The thin film transistor in which the semiconductor layer is a composite metal oxide in which tin oxide is added with a metal oxide having an oxygen separation energy larger than that of tin oxide and a difference from the oxygen separation energy of tin oxide being less than 200 kJ / mol.
 前記半導体層は、酸素の解離エネルギーが酸化錫よりも小さい追加の酸化物を前記金属酸化物よりも少ない量だけ含む、請求項20に記載の薄膜トランジスタ。 21. The thin film transistor according to claim 20, wherein the semiconductor layer includes an additional oxide whose oxygen dissociation energy is smaller than that of tin oxide in an amount smaller than that of the metal oxide.  前記半導体層中の前記追加の酸化物の含有量が20重量%以下である、請求項21に記載の薄膜トランジスタ。 The thin film transistor according to claim 21, wherein the content of the additional oxide in the semiconductor layer is 20 wt% or less.  前記半導体層中の前記追加の酸化物の含有量が4重量%以下である、請求項22に記載の薄膜トランジスタ。 23. The thin film transistor according to claim 22, wherein the content of the additional oxide in the semiconductor layer is 4% by weight or less.  前記半導体層が非晶質である、請求項20から23の何れかに記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 20 to 23, wherein the semiconductor layer is amorphous.  前記半導体層の厚さが5nm以上かつ20nm以下である、請求項20から24の何れかに記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 20 to 24, wherein a thickness of the semiconductor layer is 5 nm or more and 20 nm or less.  前記追加の酸化物は、鉛、パラジウム、白金、硫黄、アンチモン、ストロンチウム、タリウム、イッテルビウムからなる群から選択された少なくとも一の酸化物である、請求項21から25の何れかに記載の薄膜トランジスタ。 26. The thin film transistor according to claim 21, wherein the additional oxide is at least one oxide selected from the group consisting of lead, palladium, platinum, sulfur, antimony, strontium, thallium, and ytterbium.  前記金属酸化物はサマリウム、タングステン、ネオジウム、ガドリニウムからなる群から選択された少なくとも一の酸化物である、請求項20から26の何れかに記載の薄膜トランジスタ。 27. The thin film transistor according to claim 20, wherein the metal oxide is at least one oxide selected from the group consisting of samarium, tungsten, neodymium, and gadolinium.  前記半導体層中の前記金属酸化物の含有量が0より大きく50重量%以下である、請求項20から27の何れかに記載の薄膜トランジスタ。 28. The thin film transistor according to claim 20, wherein a content of the metal oxide in the semiconductor layer is greater than 0 and 50% by weight or less.  前記前記半導体層中の前記金属酸化物の含有量が5重量%以下である、請求項28に記載の薄膜トランジスタ。 The thin film transistor according to claim 28, wherein a content of the metal oxide in the semiconductor layer is 5% by weight or less.  前記半導体層を10℃以上500℃以下で形成する、請求項20から29の何れかに記載の薄膜トランジスタの製造方法。 30. The method of manufacturing a thin film transistor according to any one of claims 20 to 29, wherein the semiconductor layer is formed at 10 ° C. or more and 500 ° C. or less.  前記半導体層を10℃以上300℃以下で形成する、請求項30に記載の薄膜トランジスタの製造方法。 The method of manufacturing a thin film transistor according to claim 30, wherein the semiconductor layer is formed at a temperature of 10 ° C to 300 ° C.  酸素欠損が導入されることにより電子キャリアを生成できる金属酸化物からなる第1金属酸化物と、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物とを含んでなる酸化物半導体であって、前記第1金属酸化物の金属が、OH基、H基、F基、Cl基、又はB基からなる群から選択される少なくとも1つとの結合を有する、前記酸化物半導体。 A first metal oxide composed of a metal oxide capable of generating electron carriers by introducing oxygen vacancies; and a second metal whose oxygen separation energy is 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide. An oxide semiconductor comprising an oxide, wherein the metal of the first metal oxide is at least one selected from the group consisting of an OH group, an H group, an F group, a Cl group, or a B group The oxide semiconductor having a bond.  前記第2酸化物の酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも255kJ/mol以上大きい、請求項32に記載の酸化物半導体。 The oxide semiconductor according to claim 32, wherein the oxygen separation energy of the second oxide is 255 kJ / mol or more larger than the oxygen separation energy of the first metal oxide.  前記第1金属酸化物の金属が、インジウム、ガリウム、亜鉛、および錫からなる群から選択される少なくとも一つである、請求項32に記載の酸化物半導体。 The oxide semiconductor according to claim 32, wherein the metal of the first metal oxide is at least one selected from the group consisting of indium, gallium, zinc, and tin.  前記第2酸化物は、ケイ素(Si)、チタン(Ti)、タングステン(W)、タンタル(Ta)、ランタン(La)、ハフニウム(Hf)、ジルコニウム(Zr)、およびプラセオジム(Pr)からなる群から選択される少なくとも一つを含む酸化物である、請求項32から34のいずれか一項に記載の酸化物半導体。 The second oxide is made of silicon (Si), titanium (Ti), tungsten (W), tantalum (Ta), lanthanum (La), hafnium (Hf), zirconium (Zr), and praseodymium (Pr). The oxide semiconductor according to any one of claims 32 to 34, which is an oxide containing at least one selected from the group consisting of:  前記第2酸化物は、ケイ素(Si)、チタン(Ti)、タングステン(W)、タンタル(Ta)、ランタン(La)、およびハフニウム(Hf)からなる群から選択された少なくとも一つを含む酸化物である、請求項35に記載の酸化物半導体。 The second oxide is an oxide containing at least one selected from the group consisting of silicon (Si), titanium (Ti), tungsten (W), tantalum (Ta), lanthanum (La), and hafnium (Hf). 36. The oxide semiconductor according to claim 35, wherein the oxide semiconductor is a product.  前記第2酸化物の含有量が0より大きく50重量%以下である、請求項32から36のいずれか一項に記載の酸化物半導体。 The oxide semiconductor according to any one of claims 32 to 36, wherein the content of the second oxide is greater than 0 and 50 wt% or less.  前記第2酸化物の含有量が0より大きく5重量%以下である、請求項37に記載の酸化物半導体。 38. The oxide semiconductor according to claim 37, wherein the content of the second oxide is greater than 0 and 5% by weight or less.  酸化物半導体の厚さが5nm以上かつ20nm以下の範囲である、請求項32から38のいずれか一項に記載の酸化物半導体。 The oxide semiconductor according to any one of claims 32 to 38, wherein the thickness of the oxide semiconductor is in the range of 5 nm to 20 nm.  前記第2酸化物が、炭素(C)を含む酸化物である、請求項32から39のいずれか一項に記載の酸化物半導体。 The oxide semiconductor according to any one of claims 32 to 39, wherein the second oxide is an oxide containing carbon (C).  炭素(C)の含有量が0より大きく10重量%以下である、請求項40に記載の酸化物半導体。 41. The oxide semiconductor according to claim 40, wherein the content of carbon (C) is greater than 0 and 10% by weight or less.  前記第1金属酸化物の金属がインジウムであって、前記第2酸化物の酸素のかい離エネルギーが725kJ/mol以上である、請求項32に記載の酸化物半導体。 The oxide semiconductor according to claim 32, wherein the metal of the first metal oxide is indium, and the oxygen separation energy of the second oxide is 725 kJ / mol or more.  前記第1金属酸化物の金属がOH基との結合を有している、請求項32から42のいずれか一項に記載の酸化物半導体。 The oxide semiconductor according to any one of claims 32 to 42, wherein the metal of the first metal oxide has a bond with an OH group.  前記OH基の含有量が0.1%以上10%以下である、請求項43に記載の酸化物半導体。 44. The oxide semiconductor according to claim 43, wherein a content of the OH group is 0.1% or more and 10% or less.  前記第1金属酸化物の金属がH基との結合を有する、請求項32から42に記載の酸化物半導体。 43. The oxide semiconductor according to claim 32, wherein the metal of the first metal oxide has a bond with an H group.  前記H基の含有量が0%よりも大きく0.1%以下である、請求項45に記載の酸化物半導体。 The oxide semiconductor according to claim 45, wherein a content of the H group is greater than 0% and 0.1% or less.  前記第1金属酸化物の金属が、F基、Cl基、又はB基からなる群から選択される少なくとも1つとの結合を有する、請求項32から42のいずれか一項に記載の酸化物半導体。 43. The oxide semiconductor according to any one of claims 32 to 42, wherein the metal of the first metal oxide has a bond with at least one selected from the group consisting of an F group, a Cl group, or a B group. .  前記F基、Cl基、又はB基からなる群から選択される少なくとも1つの含有量が5×1018atoms/cm超1×1021atoms/cm以下である、請求項47に記載の酸化物半導体。 48. The content of at least one selected from the group consisting of the F group, Cl group, or B group is more than 5 × 10 18 atoms / cm 3 and not more than 1 × 10 21 atoms / cm 3 . Oxide semiconductor.  酸化物半導体が非晶質である、請求項32から48のいずれか一項に記載の酸化物半導体。 The oxide semiconductor according to any one of claims 32 to 48, wherein the oxide semiconductor is amorphous.  請求項32から49のいずれか一項に記載の酸化物半導体を含んでなる、薄膜トランジスタ。 A thin film transistor comprising the oxide semiconductor according to any one of claims 32 to 49.  ソース電極およびドレイン電極と、
 前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、
 前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、
 前記ゲート電極と前記半導体層との間に設けられた絶縁体層と
を設け、
 前記半導体層が請求項32から49のいずれか一項に記載の酸化物半導体で形成されている、薄膜トランジスタ。
A source electrode and a drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
Providing an insulator layer provided between the gate electrode and the semiconductor layer;
50. A thin film transistor, wherein the semiconductor layer is formed of the oxide semiconductor according to any one of claims 32 to 49.
 請求項51に記載の薄膜トランジスタを含んでなる、半導体装置。 52. A semiconductor device comprising the thin film transistor according to claim 51.  前記半導体層が10℃以上400℃以下で形成される、請求項32から49のいずれか一項に記載の酸化物半導体の製造方法。 The method for manufacturing an oxide semiconductor according to any one of claims 32 to 49, wherein the semiconductor layer is formed at 10 ° C or higher and 400 ° C or lower.  前記半導体層が10℃以上200℃以下で形成される、請求項32から49のいずれか一項に記載の酸化物半導体の製造方法。 The method for manufacturing an oxide semiconductor according to any one of claims 32 to 49, wherein the semiconductor layer is formed at 10 ° C or higher and 200 ° C or lower.  酸素欠損が導入されることにより電子キャリアを生成できる金属酸化物からなる第1金属酸化物の粉末と、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物の粉末との焼結体からなるターゲットと、希ガスと酸素からなる混合ガスであって水素原子を有する化合物を含まないプロセスガスとを用いた物理蒸着法により、前記第1金属酸化物と、前記第2酸化物とを含む酸化物半導体を形成する工程と、
 前記酸化物半導体を大気中、150℃で熱処理することにより酸素欠損を有する前記酸化物半導体を形成する工程と、
 前記酸素欠損を有する酸化物半導体を、HOガスを導入した80%以上の高湿度下、150~300℃の温度範囲で熱処理することにより、前記第1金属酸化物の金属とOH基との結合を形成する工程とを含む、請求項43又は44に記載の酸化物半導体の製造方法。
The first metal oxide powder composed of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and the oxygen separation energy is 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide. The first metal is obtained by physical vapor deposition using a target composed of a sintered body with a powder of the second oxide and a process gas that is a mixed gas composed of a rare gas and oxygen and does not contain a compound having a hydrogen atom. Forming an oxide semiconductor including an oxide and the second oxide;
Forming the oxide semiconductor having oxygen vacancies by heat-treating the oxide semiconductor at 150 ° C. in the atmosphere;
By heat-treating the oxide semiconductor having oxygen vacancies in a temperature range of 150 to 300 ° C. under a high humidity of 80% or more introduced with H 2 O gas, the metal of the first metal oxide, the OH group, and 45. The method of manufacturing an oxide semiconductor according to claim 43 or 44, including a step of forming a bond.
 酸素欠損が導入されることにより電子キャリアを生成できる金属酸化物からなる第1金属酸化物の粉末と、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物の粉末との焼結体からなるターゲットと、希ガスと酸素からなる混合ガスであって水素原子を有する化合物を含まないプロセスガスとを用いた物理蒸着法により、前記第1金属酸化物と、前記第2酸化物とを含む酸化物半導体を形成する工程と、
 前記酸化物半導体を大気中、150℃で熱処理することにより酸素欠損を有する前記酸化物半導体を形成する工程と、
 前記酸素欠損を有する酸化物半導体を、H雰囲気ガス下、300~400℃の温度範囲で熱処理することにより、前記第1金属酸化物の金属とH基との結合を形成する工程とを含む、請求項45又は46に記載の酸化物半導体の製造方法。
The first metal oxide powder composed of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and the oxygen separation energy is 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide. The first metal is obtained by physical vapor deposition using a target composed of a sintered body with a powder of the second oxide and a process gas that is a mixed gas composed of a rare gas and oxygen and does not contain a compound having a hydrogen atom. Forming an oxide semiconductor including an oxide and the second oxide;
Forming the oxide semiconductor having oxygen vacancies by heat-treating the oxide semiconductor at 150 ° C. in the atmosphere;
Forming a bond between the metal of the first metal oxide and an H group by heat-treating the oxide semiconductor having oxygen vacancies in a temperature range of 300 to 400 ° C. in an H 2 atmosphere gas. The method for producing an oxide semiconductor according to claim 45 or 46.
 酸素欠損が導入されることにより電子キャリアを生成できる金属酸化物からなる第1金属酸化物の粉末と、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな第2酸化物の粉末との焼結体からなるターゲットと、希ガスと酸素からなる混合ガスであって水素原子を有する化合物を含まないプロセスガスとを用いた物理蒸着法により、前記第1金属酸化物と、前記第2酸化物とを含む酸化物半導体を形成する工程と、
 前記酸化物半導体を大気中、150℃で熱処理することにより酸素欠損を有する前記酸化物半導体を形成する工程と、
 前記酸素欠損を有する酸化物半導体に、フッ素イオン、塩素イオン、又はホウ素イオンからなる群から選択される少なくとも1つをイオン注入することにより、前記第1金属酸化物の金属と、前記イオン注入された基との結合を形成する工程とを含む、請求項47又は48に記載の酸化物半導体の製造方法。
 
The first metal oxide powder composed of a metal oxide capable of generating electron carriers by introducing oxygen vacancies, and the oxygen separation energy is 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide. The first metal is obtained by physical vapor deposition using a target composed of a sintered body with a powder of the second oxide and a process gas that is a mixed gas composed of a rare gas and oxygen and does not contain a compound having a hydrogen atom. Forming an oxide semiconductor including an oxide and the second oxide;
Forming the oxide semiconductor having oxygen vacancies by heat-treating the oxide semiconductor at 150 ° C. in the atmosphere;
By ion-implanting at least one selected from the group consisting of fluorine ions, chlorine ions, or boron ions into the oxide semiconductor having oxygen vacancies, the ions of the metal of the first metal oxide are implanted. The method for producing an oxide semiconductor according to claim 47 or 48, further comprising a step of forming a bond with a group.
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