CN105702722A - Low on-resistance power semiconductor components - Google Patents

Abstract

A low-on-resistance power semiconductor component comprises a substrate with an epitaxial layer, a grid structure, a terminal structure and a patterned conducting layer, wherein the epitaxial layer is provided with a first ditch and a second ditch, the grid structure is arranged in the first ditch and comprises a grid electrode and a shielding electrode arranged below the grid electrode, the terminal structure is arranged in the second ditch and comprises a terminal electrode, and the patterned conducting layer is arranged on an interlayer dielectric layer. The invention is characterized in that the shielding electrode and the terminal electrode are designed to apply a gate voltage, the patterned conductive layer is arranged above the epitaxial layer and electrically contacts the gate electrode of the gate structure and the terminal electrode of the terminal structure by means of a first conductive plug and a second conductive plug, respectively.

Description

Low on-resistance power semiconductor components

technical field

The invention relates to a power semiconductor component, and in particular to a low conduction resistance power semiconductor component.

Background technique

Semiconductor packages are well known in the semiconductor field, and such semiconductor packages may include one or more semiconductor components, such as an integrated circuit component, die or chip. Generally speaking, an integrated circuit component includes an electronic circuit formed on a substrate using semiconductor materials and semiconductor processes such as deposition, etching, lithography, annealing, doping, and diffusion. The substrate is usually a silicon wafer to facilitate Nano integrated circuits are formed thereon.

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are a common semiconductor component that is most commonly used in power supplies, mobile electronic devices, or battery-powered devices such as mobile phones. For example, a metal oxide semiconductor field effect transistor device can be used to connect a power supply to an electronic load device and be used as a switch. In the trenches in the epitaxial layer on the substrate.

Further, the mosfet device operates by applying an appropriate voltage to its gate electrode, thereby forming a channel connected between the source and drain to allow current to flow. When the Mosfet device is turned on, the relationship between current and voltage is like a linear equation, which means that the device functions like a resistor. For Mosfet components, higher drain-source on-resistance (Rdson) may cause greater power loss, based on the drain-source on-resistance can usually be simulated and calculated, Therefore, the most ideal situation for metal oxide semiconductor field effect transistor components is to have a very low Rdson.

To sum up, in order to further reduce the Rdson of the MOS field effect transistor assembly, those skilled in the art have proposed improved structural designs for the existing MOS field effect transistor assembly.

Contents of the invention

The main purpose of the present invention is to provide a low on-resistance power semiconductor component, in which a wider current channel can be formed between two adjacent trench gate structures to reduce the overlapping accumulation of gate and drain resistance value (Racc).

In order to achieve the above-mentioned purpose and effect, the technical means adopted in the present invention are as follows: a low on-resistance power semiconductor component, comprising a substrate, an epitaxial layer, a gate structure, a terminal structure, an interlayer dielectric layer, A base region and a patterned conductive layer. Wherein, a gate conducting region is defined on the substrate, the epitaxial layer is disposed on the substrate, and has at least one first trench and at least one second trench; the gate structure is disposed on the first trench, and includes a a gate electrode, a shielding electrode disposed below the gate electrode, and an isolation dielectric completely covering the gate electrode and the shielding electrode; the terminal structure is disposed on the second trench and includes a terminal electrode and an isolation dielectric completely covering the terminal electrode, wherein the gate electrode of the gate structure and the terminal electrode of the terminal structure are electrically connected to a gate voltage; the base region is formed in the epitaxial layer and surrounds the first trenches and second trenches, the interlayer dielectric layer is disposed on the base region; the patterned conductive layer is disposed on the interlayer dielectric layer, wherein the patterned conductive layer is provided by means of a first conductive plug and a The second conductive plugs electrically contact the gate electrode of the gate structure and the terminal electrode of the terminal structure respectively.

Through the specific implementation of the above technical means, the low on-resistance power semiconductor component of the present invention is suitable for being applied to a rechargeable battery component. Not only that, the on-resistance power semiconductor component can meet the requirements of The need for miniaturization.

Other purposes and advantages of the present invention can be further understood from the technical contents disclosed in the present invention. In order to make the above and other objects, features and advantages of the present invention more comprehensible, specific embodiments and accompanying drawings are described in detail below.

Description of drawings

FIG. 1 is a layout diagram of a low on-resistance power semiconductor component of the present invention.

FIG. 2 is a schematic cross-sectional view along the section line A-A in FIG. 1 .

FIG. 3 is a schematic cross-sectional view along the section line B-B in FIG. 1 .

FIG. 4 is a schematic cross-sectional view along the section line C-C in FIG. 1 .

FIG. 5 is a schematic cross-sectional view along the line D-D in FIG. 1 .

FIG. 6 is a schematic cross-sectional view along line E-E of FIG. 1 .

FIG. 7 is a schematic view of the usage state of the low on-resistance power semiconductor component of the present invention.

8 to 11 are process schematic diagrams of the method for forming the gate structure and the terminal structure of the present invention.

12 to 14 are process schematic diagrams of the method for forming the body region, the source region and the heavy body region of the present invention.

detailed description

The disclosed content of the present invention relates to an innovative power semiconductor component. In order to achieve the purpose of miniaturization, the component layout is constructed with a rectangular trench-type terminal structure and at least two straight strip-shaped trench-type gate structures. made.

Furthermore, the trench-type terminal structure includes a terminal electrode and an isolation dielectric disposed between the terminal electrode and the corresponding trench, and each trench-type gate structure comprises a gate electrode and a gate electrode disposed between the gate electrode and the corresponding trench. Therefore, in the non-conducting state, the thick oxide insulating layer at the bottom of the trench can withstand a higher electric field, so the breakdown voltage can be increased, and the concentration of the high epitaxial layer can be adjusted to reduce the conductivity. The effect of on-resistance.

Most importantly, the shielding electrode of the trenched gate structure and the terminal electrode of the trenched termination structure are designed to apply a gate voltage, so that when the power semiconductor device starts, the current can flow close to the gate. pole structure, thereby forming a wider current channel between two adjacent gate structures.

Please refer to FIG. 1 and refer to FIG. 2 to FIG. 6 together. FIG. 1 shows a layout diagram of a low on-resistance power semiconductor component according to a preferred embodiment of the present invention, and FIG. 2 to FIG. 6 are respectively represented on FIG. 1 Schematic cross-section along different section lines.

First, as shown in FIG. 1 , a semiconductor substrate 10 defines a gate conduction region 11, a source conduction region 12, a plurality of active regions 13, and a plurality of contact regions 14, etc., these regions are mainly for clarity in the following The specific arrangement positions of gate and source metal layers, source and heavy body regions, and contact plugs in the low on-resistance power semiconductor component of the preferred embodiment of the present invention are illustrated. In addition, the two straight trenches in FIG. 1 are element trenches 15 (Celltrench), and a rectangular trench surrounding the two straight strip trenches is a terminal trench 16 (Terminationtrench); it is worth noting that the element trenches 15 Used to accommodate the gate structure, the terminal trench 16 is used to accommodate the terminal structure.

In order to clearly understand the structural characteristics of the low on-resistance power semiconductor component of the preferred embodiment of the present invention, please refer to FIG. 2 to FIG. 1 is a schematic cross-sectional view of the section line B-B, and FIG. 4 is a schematic cross-sectional view along the section line C-C of FIG. 1 . As shown in the above figures, the low on-resistance power semiconductor component generally includes a substrate 20, an epitaxial layer 21, at least one gate structure 22, at least one terminal structure 23, an interlayer dielectric layer 24, a pattern conductive layer 25 and a protective layer 26.

Specifically, a gate conduction region 11 and a source conduction region 12 (as shown in FIG. 1 ) arranged parallel to and spaced from the gate conduction region 11 are defined on the substrate 20, and the material of the substrate 20 may be a semiconductor material. , and can be used as the drain electrode layer in power semiconductor components. The epitaxial layer 21 is formed on the substrate 20, both of the epitaxial layer 21 and the substrate 20 have a first conductivity type (such as N-type or P-type), wherein the doping concentration of the substrate 20 is higher than that of the epitaxial layer 21 concentration; although the preferred embodiment of the present invention takes the N-type epitaxial layer 21 and the N-type substrate 20 as an example, the present invention is not limited thereto.

Furthermore, the epitaxial layer 21 can be divided into a first epitaxial layer 211 located on the substrate 20 and a second epitaxial layer 212 located on the first epitaxial layer 211, wherein the substrate 20, the first epitaxial layer 211 and the second epitaxial layer 212 are also N-type semiconductors; it should be noted that the doping concentration (such as N+) of the substrate 20 must be higher than the doping concentration (such as N) of the first epitaxial layer 211, and the first epitaxial layer 211 The doping concentration of N must be higher than the doping concentration of the second epitaxial layer 212 (eg, N−). Accordingly, when the present invention is applied to bidirectional conductive series components, the lateral conduction resistance can be reduced and the lateral current flow can be improved.

Please refer to FIG. 5 and FIG. 6 , FIG. 2 is a schematic cross-sectional view along line D-D in FIG. 5 , and FIG. 6 is a schematic cross-sectional view along line E-E in FIG. 1 . As shown in the above figures, the epitaxial layer 21 has at least one first trench 213 and at least one second trench 214, wherein the first trench 213 extends through the second epitaxial layer 212 and part of the first epitaxial layer 211, the second Both ends of a ditch 213 communicate with the second ditch 214 , and the width of the second ditch 214 may be greater than that of the first ditch 213 .

To further illustrate the method for forming the first trench 213 and the second trench 214, first spin-coat a photoresist material on the epitaxial layer 21, then expose and pattern the photoresist material to form a patterned photoresist layer, and then The epitaxial layer 21 is etched through the patterned photoresist layer to form the first and second trenches 213 , 214 . The above-mentioned relevant process steps are well known to those skilled in the art, so they will not be repeated here.

Please refer to FIG. 2 to FIG. 6 again, the gate structure 22 is disposed on the first trench 213, and includes a gate electrode 221, a shielding electrode 222 disposed below the gate electrode 221, and a completely covering gate electrode 221 and The isolating dielectric that shields the electrode 222 . It should be noted that the gate structure 22 of this preferred embodiment may further include an electrode cover 226, and the material of the electrode cover 226 may be, but not limited to, silicon nitride (Si ₃ N ₄ ). It is above the gate electrode 221, in addition to preventing the gate electrode 221 from being over-etched and any other damage, it can also be used as a self-aligned mask for the ion implantation process.

Furthermore, the gate electrode 221 and the shielding electrode 222 below it are embedded in the first trench 213, and the material of the gate electrode 221 and the shielding electrode 222 can be but not limited to doped polysilicon, wherein the gate electrode 221 and An inter-electrode dielectric layer 223 is disposed between the shielding electrodes 222 to insulate the two from each other; moreover, a gate dielectric layer is disposed between the gate electrode 221 and the upper half of the sidewall of the first trench 213. layer 224 , and a shielding dielectric layer 225 is arranged between the shielding electrode 222 and the lower half of the sidewall of the first trench 213 to isolate the gate and shielding electrodes 221 , 222 from the surrounding N-type epitaxial layer 21 .

The terminal structure 23 is disposed in the second trench 214, and includes a terminal electrode 231 and an isolation dielectric completely covering the terminal electrode 231, wherein the terminal electrode 231 is embedded in the second trench 214, and its material can be but not limited to doped Doped polysilicon, the isolation dielectric is disposed between the terminal electrode 231 and the second trench 214 . Furthermore, the terminal electrode 231 in the terminal structure 23 and the shielding electrode 222 in the gate structure 22 are electrically connected to each other (as shown in FIG. 5 ), and the two are mainly designed to apply a gate voltage. Accordingly, as shown in FIG. 7, when the power semiconductor device is started, a wider current channel T can be formed between two adjacent gate structures 22, wherein the flow of current is almost close to the gate structures 22. , which in turn can avoid the occurrence of narrow channel phenomenon (also known as pinch phenomenon).

To further describe the method of forming the gate structure 22 and the terminal structure 23 , please refer to FIG. 8 to FIG. 11 , which are schematic process diagrams of the method. As shown in FIG. 8, firstly, a first dielectric layer 22a is formed on the sidewalls of the first and second trenches 213, 214. The material of the first dielectric layer 22a may include silicon dioxide or other suitable dielectrics. electrical material.

Next, a first conductive layer 22b is formed to fill the first and second trenches 213, 214, wherein the first conductive layer 22b can be a doped polysilicon layer formed by directly depositing on the first and second trenches 213, 214 Alternatively, the first conductive layer 22b can also be formed by first depositing an intrinsic polysilicon layer (Intrinsic polysilicon) on the first and second trenches 213, 214, and then using an ion implantation process to dope the intrinsic polysilicon layer. Formed doped polysilicon layer. In practical implementation, no matter what the formation method of the first conductive layer 22b is, a thermal drive-in process can be selectively performed thereafter.

As shown in FIG. 9, a patterned photoresist layer is then formed to cover the second trench 214, and then the first dielectric layer 22a and the first conductive layer 22b not covered by the patterned photoresist layer are etched to remove Except for part of the first dielectric layer 22 a and part of the first conductive layer 22 b inside the first trench 213 , the patterned photoresist layer is removed after the etching is completed. After the above process steps are completed, the shielding electrode 222 can be formed in the first trench 213, and at the same time, a shielding dielectric layer 225 is formed on the lower half of the sidewall of the first trench 213 to cover the shielding electrode 222; The terminal electrode 231 can be formed in the second trench 214 , and the electrical isolation layer 232 can be formed on the entire sidewall of the second trench 214 to cover the terminal electrode 231 , thereby forming the terminal structure 23 .

As shown in FIG. 10, a second dielectric layer 23a is then deposited along the outline configuration of the first and second trenches 213, 214, so that the upper half of the sidewall of the shielding electrode 222 and the terminal electrode 231 and the first trench 213 All parts are covered by the second dielectric layer 23a, and the material of the second dielectric layer 23a may include silicon dioxide or other suitable dielectric materials such as a combination of a low temperature oxide and a high temperature oxide. Thereafter, a second conductive layer 23b is formed to fill the first trench 213 by using processes such as deposition and etch back. The second conductive layer 23b can also be a doped polysilicon layer, and its formation method can refer to the first conductive layer 22b , so it will not be described here. After the above process steps are completed, the gate electrode 221 can be formed above the shielding electrode 222, and an interelectrode dielectric layer 223 is formed between the gate electrode 221 and the shielding electrode 222, and at the same time, the first trench 213 A gate dielectric layer 224 is formed on the upper half of the sidewall to cover the gate electrode 221 .

As shown in FIG. 11 , an electrode cover 226 is then formed to fill the cavity defined by the upper surface of the gate dielectric layer 224 in the first trench 213 , and the electrode cover 226 and the second epitaxial layer 212 are coplanar. To further illustrate the method for forming the electrode cover 226, first deposit a layer of half-filled silicon oxide (SiO ₂ ) layer to cover the surface of the second epitaxial layer 212, and at the same time fill the cavity between the above-mentioned gate dielectric layers 224, and then Use dry etching (Dryetch) to remove the silicon oxide layer exposing the first trench 213, this silicon oxide layer can be used as a good buffer bonding layer (Bufferlayer), and then fill a layer of silicon nitride material (Si ₃ N ₄ ) , and then use (for example but not limited to) etch back to remove the silicon nitride material exposing the first trench 213 (remaining on the surface of the second epitaxial layer 212 ), so as to form the electrode cover 226 above the gate electrode 221 . After the above process steps are completed, the gate structure 22 can be formed in the first trench 213 .

Please refer to FIG. 1 to FIG. 3 again and refer to FIG. 6, at least one body region 31 (Bodyregion) is formed in the second epitaxial layer 212, which surrounds the first ditch 213 and the second ditch 214; the body region 31 has different In the first conductivity type and the second conductivity type, that is, the substrate 20 and epitaxial layer 21 of the first conductivity type are n-type semiconductors, and the base region 31 of the first conductivity type is p-type semiconductor. In addition, a plurality of source regions 32 and a plurality of heavy body regions 33 are formed in the base region 31, wherein these source regions 32 are arranged at intervals with the first trench 213 (as shown in FIG. 1 and FIG. 2 ), these The heavy body region 33 is spaced apart from the first trenches 213 along the first direction, and is spaced apart from the source regions 32 along the second direction perpendicular to the first direction (as shown in FIG. 3 and FIG. 6 ). .

Further, these source regions 32 are mainly regarded as the active region 13 in the source conduction region 12 (as shown in FIG. 1 ) from the perspective of device layout, wherein each source region 32 has the first conductivity type, In this preferred embodiment, it is designed as a heavily doped region of the first conductivity type to form Ohmic contacts (Ohmiccontacts) with the patterned conductor layer 25; in addition, each heavily base region 33 has a second conductivity type Type, which is designed as a heavily doped second conductivity type region in this preferred embodiment, is used to adjust the potential difference between the input/output terminals of the device.

To further describe the method of forming the body region 31 , the source region 32 and the heavy body region 33 , please refer to FIG. 12 to FIG. 14 , which are schematic process diagrams of the method. As shown in FIG. 12 , first, after the electrode cover 226 is formed, the base region 31 is formed in the second epitaxial layer 21 by an ion implantation process. The operating conditions of the ion implantation process include but are not limited to boron as the dopant, And use the doping dose of 6e12at/cm ² and the implantation energy between 120 and 180KeV. Thereafter, a thermal drive-in process is used to make the base region 31 reach a predetermined junction depth.

After the formation of the base region 31, another ion implantation process is used to form the source region 32 in the second epitaxial layer 21. The operating conditions of the ion implantation process include but not limited to using arsenic as the dopant, and using /cm ² dopant dose and implantation energy between 40 and 60KeV. Thereafter, a thermal drive-in process is also used to make the source region 32 reach a predetermined junction depth.

As shown in FIGS. 13 and 14 , an interlayer dielectric layer 24 is formed on the second epitaxial layer 212 after the formation of the source region 32 to cover the gate and terminal structures 22 , 23 and the source and heavy body region 32 , 33; the material of the interlayer dielectric layer 24 may include oxide, borophosphosilicate glass (BPSG) or a combination thereof, and may utilize high-density plasma chemical vapor deposition (HDP-CVD) or general chemical vapor deposition method (CVD) formation.

After the interlayer dielectric layer 24 is formed, a patterned photoresist layer (not shown) is firstly formed to cover the terminal structure 23, and then the interlayer dielectric layer 24 not covered by the patterned photoresist layer is etched, A plurality of through holes 34 are formed in the interlayer electrical layer 24 and the base region 31 in the source conduction region 12 . After the via hole 34 is formed, a heavily doped region 33 is formed in the _second epitaxial layer 21 by another ion implantation process. Impurities, and use 1e15 ~ 3e15at/cm ² dopant dose and implantation energy between 40 to 60KeV. Thereafter, a thermal drive-in process can also be used to make the heavily doped region 33 reach a predetermined junction depth. It is worth noting that the 226 in the gate structure 22 can be used as a self-aligned mask in the above-mentioned ion implantation process, so that the source region 32 and the heavily doped region 33 are precisely positioned so that they are aligned with the first trench 213 are arranged at intervals.

Please refer to FIGS. 1 to 3 again and with reference to FIGS. 5 to 6, the patterned conductive layer 25 is formed on the interlayer dielectric layer 24. The material of the patterned conductive layer 25 can be titanium (Ti), titanium nitride ( TiN), tungsten (W), aluminum-silicon alloy (Al-Si) or aluminum-silicon-copper alloy (Al-Si-Cu), etc., but the present invention is not limited thereto, the patterned conductive layer 25 of this preferred embodiment It includes a source metal layer 251 deposited in the source conduction region 11 and a gate metal layer 252 deposited in the gate conduction region 12 (as shown in FIG. 1 , FIG. 5 and FIG. 6 ). Furthermore, in the source conduction region 12, these through holes 34 are filled with the source metal layer 251 (as shown in FIG. 2 and FIG. 3 ), accordingly, the source metal layer 251 can be connected to the source region 32 and the heavily doped region 33 are electrically connected.

Please refer to FIG. 1 and FIG. 4 again. It is worth noting that the present invention does not form a through hole 34 in the gate conduction region 11, and the gate metal layer 252 is mainly connected to the gate through at least one first contact plug 35. The gate electrode 221 in the pole structure 22 has good electrical contact, and has good electrical contact with the terminal electrode in the terminal structure 23 through at least one second contact plug 36 .

To further illustrate the method of forming the first and second contact plugs 35, 36, at least one first contact hole 351 and at least one second contact hole 351 and at least one second contact hole 351 are formed in the gate conduction region 11 at the same time as the through hole 34 is formed. hole 361; wherein, the first contact hole 351 extends through the interlayer electrical layer 24 and the electrode cover 226 and the gate dielectric layer 224 of the gate structure 22 to expose the gate electrode 221, and the second contact hole 361 The electrical isolation layer 232 extending through the interlayer electrical layer 24 and the terminal structure 23 is used to expose the terminal electrode 231 . Thereafter, the first contact hole 351 and the second contact hole 361 are respectively filled with a contact structure of a metal material (such as tungsten) with better hole-filling ability and lower resistance value. Before the metal contact structure, ion implantation must be performed on the first and second contact holes 351, 361, thereby forming ohmic contacts between the first and second contact plugs 35, 36 and the gate and terminal electrodes 221, 231 .

Thereafter, a chemical mechanical polishing process (CMP) is used to make the metal contact structures in the first and second contact holes 351 and 361 coplanar with the interlayer dielectric layer 24 . In this way, the first and second contact plugs 35, 36 can be respectively formed in the contact regions 14 shown in FIG. Show).

To sum up, compared with the existing power semiconductor components, the low on-resistance power semiconductor component of the present invention uses the conductive plug in the gate conduction area as a buried bus line, which can not only reduce the gate input resistance, and there is no need to divide the source metal layer during wire bonding packaging, that is to say, the source metal layer has a larger effective area to facilitate subsequent wire bonding packaging processes.

Secondly, the component layout of the present invention is constructed by a rectangular trench-type terminal structure and at least two straight trench-type gate structures located inside it, wherein the trench-type terminal structure includes a terminal electrode and a The isolation dielectric between the terminal electrode and the corresponding trench, each of the trench gate structures includes a gate electrode and a shielding electrode disposed below the gate electrode; therefore, the present invention can meet the requirements of miniaturization In addition, in the non-conducting state, the thicker oxide insulating layer at the bottom of the trench can withstand a higher electric field, so the breakdown voltage can be increased, and the concentration of the high epitaxial layer can be adjusted to reduce the on-resistance. Effect.

Most importantly, the shielding electrode of the trenched gate structure and the terminal electrode of the trenched termination structure are designed to apply a gate voltage, so that when the power semiconductor device starts, the current can flow close to the gate. pole structure, thereby forming a wider current channel between two adjacent gate structures, thereby avoiding the occurrence of narrow channel phenomenon (also known as pinch phenomenon).

The above descriptions are only examples of the present invention, and are not intended to limit the scope of patent protection of the present invention. Any person skilled in the art, without departing from the spirit and scope of the present invention, the changes and modifications made by equivalent replacements still fall within the patent protection scope of the present invention.

【Symbol Description】

10 Semiconductor substrate 11 Gate conduction region

12 Source conduction region

13 active areas

14 contact area

15 component trench

16 terminal ditch

20 substrates

21 epitaxial layer 211 first epitaxial layer

212 second epitaxial layer

213 First Ditch

214 Second Ditch

22 Gate Structure 221 Gate Electrode

222 shaded electrodes

223 interelectrode dielectric layer

224 gate dielectric layer

225 masking dielectric layer

226 electrode cover

22a first dielectric layer

22b first conductive layer

23 terminal structure 231 terminal electrode

232 electrical isolation layer

23a second dielectric layer

23b second conductive layer

24 interlayer dielectric layers

25 patterned conductive layer 251 source metal layer

252 gate metal layer

26 layers of protection

31 basal region

32 source area

33 heavy matrix area

34 through holes

35 first contact plug 351 first contact hole

36 second contact plug 361 second contact hole

352, 362 metal contact structure

Claims (10)

1. a low on-resistance power semiconductor subassembly, it is characterised in that including:

One substrate, on it, definition has a gate turn-on region；

One epitaxial layer, is arranged on described substrate, and has at least one first irrigation canals and ditches and at least one second irrigation canals and ditches；

One grid structure, is arranged in described first irrigation canals and ditches, and wherein, described grid structure includes a gate electrode, the shielding electrode and of lower section being arranged at described gate electrode is completely covered the isolation dielectric medium of described gate electrode and described shielding electrode；

One terminal structure, is arranged in described second irrigation canals and ditches, and wherein, described terminal structure includes a terminal electrode and and the isolation dielectric medium of described terminal electrode is completely covered；

One matrix area, is formed in described epitaxial layer and around described first irrigation canals and ditches and described second irrigation canals and ditches；

One interlayer dielectric layer, is arranged on described matrix area；And

One patterned conductive layer, is arranged on described interlayer dielectric layer, and wherein, described patterned conductive layer electrically contacts the gate electrode of described grid structure and the terminal electrode of described terminal structure respectively by one first conductive plunger and one second conductive plunger；

Wherein, the gate electrode of described grid structure and the terminal electrode of described terminal structure electrically connect a grid voltage。

2. low on-resistance power semiconductor subassembly according to claim 1, further include plurality of source regions and multiple severe matrix area, the plurality of source area is formed in described matrix area and is distributed in distance with described first groove, the plurality of severe matrix area is distributed in distance along a first direction and described first groove, is distributed in distance along a second direction being perpendicular to described first direction with the plurality of source area simultaneously。

3. low on-resistance power semiconductor subassembly according to claim 1, wherein, described grid structure also includes an electrode lid, and described electrode lid is arranged at the top of described gate electrode, and the material of described electrode lid is silicon nitride (Si₃N₄)。

4. low on-resistance power semiconductor subassembly according to claim 1, wherein, described epitaxial layer is further separated into first epitaxial layer and being positioned on described substrate and is positioned at the second epitaxial layer on described first epitaxial layer, described substrate, described first epitaxial layer and described second epitaxial layer have the first conductivity type, the doping content of described substrate is higher than the doping content of described first epitaxial layer, and the doping content of described first epitaxial layer is higher than the doping content of described second epitaxial layer。

5. low on-resistance power semiconductor subassembly according to claim 1, wherein, described substrate there is also defined the source conduction region of one and the arrangement of described gate turn-on region parallel interval, it is positioned at described gate turn-on region, the electrode lid of described interlayer circle electric layer and described grid structure and gate dielectric are formed with at least one first contact hole to expose described gate electrode, and are filled with a metal contact structure in described first contact hole to form described first contact plunger。

6. low on-resistance power semiconductor subassembly according to claim 5, wherein, described interlayer circle electric layer and electrically isolating of described terminal structure are formed with at least one second contact hole to expose described terminal electrode in layer, and are filled with a metal contact structure in described second contact hole to form described second contact plunger。

7. low on-resistance power semiconductor subassembly according to claim 1, wherein, the dopant dose forming described matrix area is 6E12 atom/cm², the dopant dose forming the plurality of source area is 1e15～8e15at/cm², the dopant dose forming the plurality of severe matrix area is 1e15～3e15at/cm²。

8. low on-resistance power semiconductor subassembly according to claim 1, wherein, described substrate can be used as the drain electrode layer of described low on-resistance power semiconductor subassembly。

9. low on-resistance power semiconductor subassembly according to claim 1, wherein, described substrate there is also defined the source conduction region of one and the arrangement of described gate turn-on region parallel interval, described source conduction region is parallel with described gate turn-on region and is spaced, described patterned conductive layer includes source metal layer and a gate metal layer, described source metal is arranged in described source conduction region, and described gate metal layer is arranged in described gate turn-on region。

10. low on-resistance power semiconductor subassembly according to claim 9, wherein, it is positioned at described source conduction region, described interlayer circle electric layer and described matrix area are formed with multiple through hole, the plurality of through hole corresponds to the plurality of source area and the plurality of severe matrix area, and is filled with described source metal in the plurality of through hole。