[go: up one dir, main page]

CN105679661A - 一种减小氧化铪栅介质漏电流的方法 - Google Patents

一种减小氧化铪栅介质漏电流的方法 Download PDF

Info

Publication number
CN105679661A
CN105679661A CN201610010259.3A CN201610010259A CN105679661A CN 105679661 A CN105679661 A CN 105679661A CN 201610010259 A CN201610010259 A CN 201610010259A CN 105679661 A CN105679661 A CN 105679661A
Authority
CN
China
Prior art keywords
leakage current
hafnium oxide
gate dielectric
hfo
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610010259.3A
Other languages
English (en)
Inventor
陈松岩
许怡红
李成
黄巍
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xiamen University
Original Assignee
Xiamen University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xiamen University filed Critical Xiamen University
Priority to CN201610010259.3A priority Critical patent/CN105679661A/zh
Publication of CN105679661A publication Critical patent/CN105679661A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

一种减小氧化铪栅介质漏电流的方法，涉及氧化铪。1)首先对p-Si(100)衬底进行RCA标准清洗，去除有机污染物、氧化物和金属杂质等物质；2)将p-Si(100)衬底放入电子束真空镀膜系统中，沉积一层HfO2薄膜，得到HfO2/Si结构；3)将步骤2)得到的样品放入感应耦合等离子体刻蚀机中，采用氧等离子体对其进行处理；4)将步骤3)处理后的样品正面固定在掩膜板上，放入磁控溅射机中沉积金属作为上电极，在样品Si衬底的背面溅射金属作为背电极，即得MOS结构器件。既能降低热预算又可降低栅漏电流，即在沉积的HfO2材料上采用氧等离子体对其进行再氧化处理，从而达到减小氧空位密度，降低栅漏电流作用。

Description

一种减小氧化铪栅介质漏电流的方法
技术领域
本发明涉及氧化铪(HfO2)，尤其是涉及一种减小氧化铪栅介质漏电流的方法。
背景技术
随着半导体技术的发展，晶体管的特征尺寸不断等比例缩小，为了避免短沟道效应，栅氧化层的厚度也需近似成比例地减薄，32nm技术节点时传统的SiO2栅介质需减薄到1nm之下[1-2]，这将使得电子以直接隧穿的方式通过栅介质层而导致栅漏电流的增大。与SiO2相比，高κ介质材料因其具有较大的介电常数，使其在相同的等效氧化层厚度(EOT)的条件具有更大的物理厚度，从而抑制电子的直接隧穿，减小栅漏电流。其中，氧化铪(HfO2)因具有较大的介电常数(～25)、相对较大的带隙(～5.8eV)、相对较好的热稳定性等特点而成为最有前景的SiO2栅介质替代材料[2-5]。然而，HfO2材料本身具有较高的氧空位，氧空位可在带隙中引入施主能级[1,6]而成为电荷陷阱和漏电通道，增大栅漏电流，降低了HfO2的性能。
目前，解决HfO2中氧空位密度较高的问题主要采用的方法是对HfO2进行O2或NH3环境下退火[7]，其中，O2退火可以对HfO2进行再氧化以降低氧空位密度，NH3退火可以在HfO2材料中掺入N原子从而耦合氧空位消除氧空位在禁带中引入的陷阱能级。然而，HfO2材料结晶温度低(～400℃)，退火容易使非晶态的HfO2变为多晶态，多晶晶界存在缺陷，将成为漏电的通道，从而增大器件的栅漏电流，降低器件的性能。
参考文献：
[1]翁妍,汪辉.高κ材料用作纳米级MOS晶体管栅介质薄层(上)[J].半导体技术,2008(1):1-5.
[2]RenaultO,SamourD,DamlencourtJF,etal.HfO2/SiO2interfacechemistrystudiedbysynchrotronradiationX-rayphotoelectronspectroscopy[J].AppliedPhysicsLetters,2002,81:3627-3629.
[3]ZhuWJ,MaTP,TamagawaT,etal.Currenttransportinmetal/hafniumoxide/siliconstructure[J].ElectronDeviceLetters,IEEE,2002,23(2):97-99.
[4]IkedaH,GotoT,SakashitaM,etal.LocalleakagecurrentofHfO2thinfilmscharacterizedbyconductingatomicforcemicroscopy[J].JapaneseJournalofAppliedPhysics,2003,42(4S):1949.
[5]GusevEP,D’EmicCP.ChargedetrappinginHfO2high-κgatedielectricstacks[J].Appliedphysicsletters,2003,83(25):5223-5225.
[6]BroqvistP,PasquarelloA.OxygenvacancyinmonoclinicHfO2:Aconsistentinterpretationoftrapassistedconduction,directelectroninjection,andopticalabsorptionexperiments[J].Appliedphysicsletters,2006,89(26):262904.
[7]AkbarMS,GopalanS,ChoHJ,etal.High-performanceTaN/HfSiON/Simetal-oxide-semiconductorstructurespreparedbyNH3post-depositionanneal[J].Appliedphysicsletters,2003,82(11):1757-1759.
发明内容
本发明的目的在于针对目前晶体管常用栅介质材料HfO2中氧空位密度较高、漏电较大的问题，提供一种既能降低热预算又可降低栅漏电流，即在沉积的HfO2材料上采用氧等离子体对其进行再氧化处理，从而达到减小氧空位密度，降低栅漏电流作用的一种减小氧化铪栅介质漏电流的方法。
本发明包括以下步骤：
1)首先对p-Si(100)衬底进行RCA标准清洗，去除有机污染物、氧化物和金属杂质等物质；
2)将p-Si(100)衬底放入电子束真空镀膜系统(e-Beam)中，沉积一层HfO2薄膜，得到HfO2/Si结构；
3)将步骤2)得到的样品放入感应耦合等离子体刻蚀机中，采用氧等离子体对其进行处理；
4)将步骤3)处理后的样品正面固定在掩膜板上，放入磁控溅射机中沉积金属作为上电极，在样品Si衬底的背面溅射金属作为背电极，即得MOS结构器件。
在步骤2)中，所述沉积可采用电子束蒸发沉积；所述HfO2薄膜的厚度可为20nm；
在步骤3)中，所述处理的条件可为：设置氧气流量40sccm，功率130W，在反应离子刻蚀(RIE)模式下，对样品进行氧等离子体处理，处理时间为10min。
在步骤4)中，所述沉积金属可沉积一层50nm的TaN和300nmAl作为上电极。
当氧气流量为40sccm、功率为130W时，在反应离子刻蚀(RIE)模式下，对样品进行氧等离子体处理10min后，MOS器件在-1V时的反向漏电流密度低至3.15×10-7A/cm2，器件的电容最大值约为8.65×10-10F，HfO2的k值可达16。
本发明在HfO2栅介质上采用氧等离子体(O2plasma)处理对其进行再氧化，从而达到填补HfO2介质中氧空位，抑制栅漏电流的作用。
本发明的技术方案是首先在清洗后的Si衬底上采用电子束真空镀膜系统(e-Beam)沉积一层HfO2，接着将其放入感应耦合等离子体刻蚀机中，在反应离子刻蚀(RIE)模式下，采用氧等离子体对其进行再氧化处理10min。
本发明采用氧等离子体处理的方法对HfO2进行再氧化处理，可填补HfO2介质中氧空位，消除氧空位在禁带中引入的陷阱能级，从而有效地减小了栅漏电流，且避免了常规的O2或NH3环境下退火所导致的HfO2介质层晶化而产生的晶界漏电问题，降低了器件工艺的热预算。本发明是一种简易、低成本、与半导体工艺兼容的降低HfO2栅漏电流的新方法。
附图说明
图1为本发明减小HfO2栅介质漏电流的流程示意图。
图2为氧等离子体处理前后HfO2栅-MOS结构的电流-电压(I-V)曲线图。
图3为氧等离子体处理前后HfO2栅-MOS结构的电容-电压(C-V)曲线图。
具体实施方式
以下实施例将结合附图对本发明作进一步的说明。
实施例1：图1给出本发明减小HfO2栅介质漏电流的流程示意图。其中，1为Si衬底，2为沉积的HfO2栅介质层，3为经过氧等离子体处理的HfO2栅介质层，4为TaN层，5为金属Al层。首先对Si衬底进行清洗：先将Si片放入Ⅲ号液(H2O2∶H2SO4＝1∶4)中加热10min，去除有机污染物，用去离子水冲洗后放入氢氟酸溶液中(HF∶H2O＝1∶20)漂洗4min，去除表面SiO2层；用去离子水冲洗后放入Ⅰ号液(H2O2∶NH3∶H2O＝1∶1∶4)中加热10min，再用去离子水冲洗，接着放入氢氟酸溶液中再漂洗4min，并再次用去离子水冲洗，最后放入Ⅱ号液(H2O2∶HCl∶H2O＝1∶1∶4)中加热10min，用去离子水冲洗后放入氢氟酸溶液中漂洗4min，经过去离子水冲洗，最后用N2吹干(见图1(a))。
将清洗后的Si片迅速放入高精度电子束真空镀膜系统(e-Beam)中，用电子束蒸发沉积一层约为20nm的HfO2薄膜(见图1(b))；接着，将样品放入感应耦合等离子体刻蚀机中，设置氧气流量40sccm，功率130W，在反应离子刻蚀(RIE)模式下，对样品进行氧等离子体处理(见图1(c))，处理时间为10min；
最后，将处理过的样品固定在掩膜板上，用磁控溅射机沉积一层50nm的TaN和300nmAl作为上电极，在Si衬底背面溅射金属Al作为背电极，得到MOS器件结构(见图1(d))。对样品进行I-V和C-V电学特性的测试，测试结果分别如图2、3所示。
实施例2：与实施例1类似，其区别在于HfO2栅介质层未进行氧等离子体处理，该原生(as-deposited)样品I-V和C-V电学特性分别如图2、3所示。

Claims (5)

1.一种减小氧化铪栅介质漏电流的方法，其特征在于包括以下步骤：
1)首先对p-Si(100)衬底进行RCA标准清洗，去除有机污染物、氧化物和金属杂质等物质；
2)将p-Si(100)衬底放入电子束真空镀膜系统(e-Beam)中，沉积一层HfO2薄膜，得到HfO2/Si结构；
3)将步骤2)得到的样品放入感应耦合等离子体刻蚀机中，采用氧等离子体对其进行处理；
4)将步骤3)处理后的样品正面固定在掩膜板上，放入磁控溅射机中沉积金属作为上电极，在样品Si衬底的背面溅射金属作为背电极，即得MOS结构器件。
2.如权利要求1所述一种减小氧化铪栅介质漏电流的方法，其特征在于在步骤2)中，所述沉积采用电子束蒸发沉积。
3.如权利要求1所述一种减小氧化铪栅介质漏电流的方法，其特征在于在步骤2)中，所述HfO2薄膜的厚度为20nm。
4.如权利要求1所述一种减小氧化铪栅介质漏电流的方法，其特征在于在步骤3)中，所述处理的条件为：设置氧气流量40sccm，功率130W，在反应离子刻蚀模式下，对样品进行氧等离子体处理，处理时间为10min。
5.如权利要求1所述一种减小氧化铪栅介质漏电流的方法，其特征在于在步骤4)中，所述沉积金属是沉积一层50nm的TaN和300nmAl作为上电极。
CN201610010259.3A 2016-01-07 2016-01-07 一种减小氧化铪栅介质漏电流的方法 Pending CN105679661A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610010259.3A CN105679661A (zh) 2016-01-07 2016-01-07 一种减小氧化铪栅介质漏电流的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610010259.3A CN105679661A (zh) 2016-01-07 2016-01-07 一种减小氧化铪栅介质漏电流的方法

Publications (1)

Publication Number Publication Date
CN105679661A true CN105679661A (zh) 2016-06-15

Family

ID=56299507

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610010259.3A Pending CN105679661A (zh) 2016-01-07 2016-01-07 一种减小氧化铪栅介质漏电流的方法

Country Status (1)

Country Link
CN (1) CN105679661A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447508A (zh) * 2020-11-24 2021-03-05 湘潭大学 一种通过等离子体技术增强氧化铪(HfO2)基铁电薄膜铁电性能的方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080233764A1 (en) * 2004-04-09 2008-09-25 Tsuyoshi Takahashi Formation of Gate Insulation Film
CN102226270A (zh) * 2011-04-29 2011-10-26 中国科学院上海微系统与信息技术研究所 沉积栅介质的方法、制备mis电容的方法及mis电容
CN103065954A (zh) * 2013-01-16 2013-04-24 苏州大学 一种HfO2薄膜/HfSiNO界面层/Si衬底栅介质的制备方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080233764A1 (en) * 2004-04-09 2008-09-25 Tsuyoshi Takahashi Formation of Gate Insulation Film
CN102226270A (zh) * 2011-04-29 2011-10-26 中国科学院上海微系统与信息技术研究所 沉积栅介质的方法、制备mis电容的方法及mis电容
CN103065954A (zh) * 2013-01-16 2013-04-24 苏州大学 一种HfO2薄膜/HfSiNO界面层/Si衬底栅介质的制备方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HIROYA IKEDA, TOMOKAZU GOTO ET AL.: "Local Leakage Current of HfO2 Thin Films Local Leakage Current of HfO2 Thin Films", 《JPN. J. APPL. PHYS.》 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447508A (zh) * 2020-11-24 2021-03-05 湘潭大学 一种通过等离子体技术增强氧化铪(HfO2)基铁电薄膜铁电性能的方法

Similar Documents

Publication Publication Date Title
Wang et al. A physical model for the hysteresis phenomenon of the ultrathin ZrO 2 film
Taoka et al. Impact of Fermi level pinning inside conduction band on electron mobility of In x Ga 1− x As MOSFETs and mobility enhancement by pinning modulation
TW201836006A (zh) 半導體元件製造方法
JP2003179049A (ja) 絶縁膜形成方法、半導体装置及びその製造方法
CN103451611B (zh) 适用于栅介质层的低漏电流HfO2薄膜的制备方法
Perera et al. Effects of post annealing on removal of defect states in silicon oxynitride films grown by oxidation of silicon substrates nitrided in inductively coupled nitrogen plasma
CN105529257A (zh) 一种优化堆叠栅介质与锗界面的方法
US9159779B2 (en) Method of fabricating semiconductor device
CN105679661A (zh) 一种减小氧化铪栅介质漏电流的方法
KR101455263B1 (ko) 기판의 산화물 제거 방법 및 이를 이용한 반도체 소자 제조 방법
CN102064111A (zh) 一种利用等离子体释放费米能级钉扎的方法
US7365403B1 (en) Semiconductor topography including a thin oxide-nitride stack and method for making the same
US7022626B2 (en) Dielectrics with improved leakage characteristics
Cao et al. HfO2/GeOxNy/Ge gate stacks with sub-nanometer capacitance equivalent thickness and low interface trap density by in situ NH3 plasma pretreatment
US9466495B2 (en) Chemical dielectric formation for semiconductor device fabrication
Liang et al. Annealing effect on electrical properties of high-k MgZnO film on silicon
Choi et al. Impact of CF 4/O 2 Plasma Passivation on Endurance Performance of Zr-Doped HfO 2 Ferroelectric Film
CN107248527A (zh) 高K/AlN/低In组分InGaAs的MOS电容制备方法
JP2011119712A (ja) 酸化物半導体の評価方法、半導体装置の作製方法
CN113497130A (zh) 电子器件、其制造方法、和存储设备
Simchi et al. Passivation of InSb surface for manufacturing infrared devices
Cheng et al. Improved electrical and surface characteristics of metal-oxide-semiconductor device with gate hafnium oxynitride by chemical dry etching
Kumar Ohmic contacts to homoepitaxially grown p-type and n-type germanium
Chen et al. Electrical characteristics of thin HfO2 gate dielectrics prepared using different pre-deposition surface treatments
Kang et al. Effects of Microwave Annealing on High-k Dielectric HfO2 Thin Films

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20160615

RJ01 Rejection of invention patent application after publication