CN105679648A - 用于转移层的处理 - Google Patents
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Abstract
用于转移层的处理。本发明涉及一种用于使用临时衬底(5)将有源层(2)转移至最终衬底(4)的处理,所述有源层(2)包括具有特定表面形貌的第一侧(1),所述处理包括以下步骤:将所述有源层(2)的所述第一侧(1)结合到所述临时衬底(5)的一侧的第一步骤;将所述有源层(2)的第二侧(6)结合到所述最终衬底(4)的第二步骤;以及,将所述有源层(2)和所述临时衬底(5)分开的第三步骤,所述处理的特征在于,所述临时衬底(5)的所述一侧具有与所述有源层(2)的所述第一侧(1)的所述表面形貌互补的表面形貌,使得在结合的所述第一步骤中,所述临时衬底(5)的所述表面形貌封装所述有源层(2)的所述第一侧(1)的所述表面形貌。
Description
技术领域
本发明涉及用于转移包括特定表面形貌的有源层(activelayer)的处理。
背景技术
这种层的制造越来越涉及用于将各种厚度的层从一个载体转移至另一个载体的技术。
在微电子领域的许多应用中,可能希望将例如集成电子部件的所谓有源层转移至衬底,或者将存在于第一衬底的表面上的半导体层转移至第二衬底。
有源层,如本发明的上下文中的理解,由于其尺寸(特别是其厚度)及其脆性,不能被认为是自支撑。
因此,为了传送有源层,并且具体地,将其转移至最终衬底,必须确保将其固定至被称为处理衬底(handlesubstrate)或临时衬底(temporarysubstrate)的转移衬底。然后,这样的衬底使需要被移动和/或转移的层能够被处理。
可以证明,使用临时衬底将有源层转移至最终衬底是困难的,因为有源层的第一侧包括形成针对有源层的第一侧的非均匀表面形貌的电子部件,诸如电路和接触焊盘,通常称为“结合焊盘”。该表面形貌使得很难确保将临时衬底固定至有源层的第一侧。
使(其表面形貌不平坦的)有源层第一侧能够被结合至临时衬底的现有技术解决方案主要在于校平和/或平坦化有源层的面,以获得适用于结合(例如直接结合)的规则表面形貌。然而,这些方法实施时都有缺点和难点。
文件FR2926671A1中描述的一个已知的解决方案主要在于在有源层上形成粘合材料层,并且特别是在有源层的具有不规则表面形貌的面上,以使得所述粘合材料层平坦化有源层的表面形貌,目的是通过粘合材料层将有源层结合至最终衬底。该解决方案的缺点是必须添加层,这使得处理复杂并且增加其制造成本。此外,粘合材料层与形成有源层的表面形貌的电子部件相接触。该接触可能损坏元件。
文件JP11-297972中描述的另一个方案主要在于使用一个位于另一个上的多个层覆盖电子部件,该多个层的最后一层被蚀刻,以便获得用于结合步骤的预期平坦程度。因此,该蚀刻步骤可能在结构中产生污染和应力。此外,电子部件也直接接触第一层,可能损坏电子部件。最后,该解决方案需要与存在沉积层一样多的沉积处理,使得处理复杂化且实施昂贵。
此外,上面提及的已知现有技术解决方案中描述的层的添加会导致增加稳定和/或加强这些层到载体的结合所需的热处理的数目。因此,这些解决方案增加了制造处理的热预算,可能使某些电气元件脆化(fragilizing)并增加这些制造处理的成本。
此外,并且根据预期结构的制造处理,这些层的添加使在随后的制造步骤中接近其上放置有添加的层的有源层的面复杂化。
已知的现有技术解决方案需要对有源层的至少一侧的各种类型的处理,以便使其针对结合足够平坦。根据所实施的处理的类型,污染或所施加的应变会导致降低有源层的质量和操作性能。
发明内容
本发明旨在通过提供用于使用临时衬底将有源层转移至最终衬底的处理来减轻现有技术的这些限制,所述有源层包括具有特定表面形貌的第一侧,所述处理包括:
-将所述有源层的所述第一侧结合到所述临时衬底的一侧的第一步骤;
-将所述有源层的第二侧结合到所述最终衬底的第二步骤;以及
-将所述有源层和所述临时衬底分开的第三步骤。
根据本发明的处理值得一提的是,所述临时衬底的所述一侧具有与所述有源层的所述第一侧的表面形貌互补的表面形貌,使得在结合的所述第一步骤中,所述临时衬底的表面形貌封装(encapsulate)所述有源层的表面形貌。
通过这种方式实施该处理使得所述有源层的所述第一侧在所述有源层不经过任何处理或修改的情况下能够被结合至所述临时衬底的所述一侧,因此防止污染或不必要的应力。此外,通过所述临时衬底的互补的表面形貌封装所述有源层的表面形貌使得放置在所述有源层上的电子部件能够受到保护,从而防止任何接触。
附图说明
根据以下结合附图给出的本发明的具体的并且非限制性实施方式的描述,本发明将会更好的被理解,在附图中:
图1是根据本发明的有源层的一侧的照片;
图2是根据本发明的另一个有源层的一侧的示意图以及根据本发明的临时衬底的一侧的示意图;
图3是根据本发明的转移处理的示意图;以及
图4是根据本发明的转移处理的另一个实施方式的示意图。
具体实施方式
现在将结合图1至4来描述根据本发明的并且使得能够缓解上述问题的转移处理的多个可能的实施方式。对于有源层和临时衬底的各种表示通用的元件使用相同的附图标记来表示。
图1是有源层2的其上放置诸如电子电路和接触焊盘这样的电子部件3的第一侧1的照片。通过非限制性示例,有源层2可以由硅、AlN、塑料、玻璃等制成。电子部件的数目和它们互相间隔的距离根据有源层2的预期功能和制造处理来设定。因此,电子部件3形成有源层2的第一侧1的特定表面形貌。然后,如图3所示,有源层2的第一侧1的特定表面形貌包括平坦部分和由电子部件限定的至少一个非平坦部分。
非平坦部分还可以由特定的处理而产生,或者由部件的沉积而产生,该部件不一定是电子部件。
图3示意性地逐步示出根据本发明的转移处理,该处理主要在于通过将最终衬底4的一侧结合到该有源层2的第二侧6而将诸如图1中所例示的有源层2这样的有源层2转移至最终衬底4。有源层2使用临时衬底5来转移,在第一结合步骤中,有源层2的第一侧1被结合至临时衬底5的一侧,同时考虑有源层2的第一侧1的表面形貌。有源层2的第一侧1和临时衬底5的所述一侧之间的结合是例如直接结合。通过示例,临时衬底5可以由锗、硅、二氧化硅、碳化硅、砷化镓或石英制成。
直接结合本身是公知的技术。这种结合的原理基于将两个表面直接接触,即不使用特定的材料(粘合剂、蜡、焊料等)。这种操作需要将要被结合的表面(至少部分)足够平坦,没有颗粒或污染物,以使它们相互足够接近以使得能够开始接触,这通常发生在小于几纳米的距离处。在这种情况下,两个表面之间的吸引力足够高以至于产生直接结合(由要被结合的两个表面的原子或分子之间的吸引的范德瓦斯(VanDerWaals)力、电子相互作用的总和引起的结合)。
因此,这种结合不可能获得,除非有源层2的第一侧1和/或临时衬底5的所述一侧被修改,以使要被结合的这些侧1、5(至少部分)足够平坦且没有颗粒或污染物。在本实例中,将只修改临时衬底5的所述一侧。
因此,本发明的转移处理包括在临时衬底5的所述一侧上产生与有源层2的第一侧1的表面形貌互补的表面形貌,以使得在放置于有源层2的第一侧1上的电子部件3不会接触到临时衬底5的情况下,临时衬底5的表面形貌在第一结合步骤中封装有源层2的第一侧1的表面形貌。
为此,如图2所示,有源层2的第一侧1的表面形貌的图形被产生以便收集与放置在有源层2的第一侧1上的电子部件3的几何结构和尺寸相关的数据。然后,互补的表面形貌可以通过临时衬底5的蚀刻来产生,因此形成凹部7,再现事先确定的几何结构和尺寸。这个操作可以通过任一种已知的现有蚀刻处理来实施,诸如湿法蚀刻或反应离子蚀刻(RIE),而且例如,使用激光,或者适用于临时衬底5的材料的任意其它解决方案。
此外,为了在电子部件3不会接触到临时衬底5的情况下使临时衬底5的表面形貌封装有源层2的第一侧1的表面形貌,用于产生临时衬底5的互补性表面形貌的尺寸相对于放置在有源层2的第一侧1上的电子部件3的尺寸被增加至少5%。
因此,临时衬底5的厚度比有源层2的第一侧1的表面形貌的最大高度h大至少5%。
临时衬底5的表面形貌可以(如上所示以及诸如图3中所示)通过几何结构和尺寸增加5%地复制放置在有源层2的第一侧1上的电子部件3、或者可替代地(诸如图4所示)通过制造其深度和宽度与电子部件3的最大高度h和最大宽度1至少增加5%相对应的凹部7(例如矩形)来产生,以便紧密地匹配有源层2的第一侧1的表面形貌。
在将有源层2的第一侧1直接结合到临时衬底5的所述一侧的第一步骤中,仅仅有源层2的第一侧1的平坦部分被结合上。为了获取足以使有源层2能够被操纵并转移的结合力,有源层2的第一侧1的平坦部分的面积(即结合的面积)大于非平坦部分的面积。因此,有源层2的第一侧1和临时衬底5的所述一侧之间的结合面积表示有源层2的第一侧1的总面积的至少50%。换句话说,有源层2的第一侧1中的、临时衬底5的所述一侧要结合到的平坦区域大于有源层2的第一侧1的非平坦区域。
根据有源层2的第一侧1和临时衬底5的所述一侧之间的结合面积的尺寸,稳定和/或加强热处理对改进结合也可以是必要的,以便获取至少700mJ/m2的结合能。在这种情况下,为了防止电子部件3被损坏,热处理的温度将低于500℃。
一旦第一结合步骤已经被实施,有源层2的第二侧6在第二结合步骤中(例如通过直接结合)被结合至最终衬底4的一侧。
根据实施方式,在第一和第二步骤之间,在有源层2的第二侧6上实施薄化的步骤,例如通过机械抛光或适用于有源层2的材料且现有技术中已知的任意其它技术,以获得厚度介于2um到10um之间的有源层2。
最后,在第三步骤中,临时衬底5和有源层2被分开,以便获得期望的结构2、4。存在许多使层能够从衬底分开的已知现有处理。非限制性地,衬底5和层2可以例如通过将刀片插在临时衬底5和有源层2之间来分开。假定将有源层2的第一侧1结合到临时衬底5的所述一侧的第一步骤没有在这两侧的整体上实施,则因此临时衬底5和有源层2的分开(在第三步骤中)更容易。
因此,根据本发明的转移处理使得具有特定表面形貌的有源层能够在不需要必须处理所述层的情况下被转移,因此在转移期间防止任何污染或应变,同时保护电子部件。此外,临时衬底可以被重复利用来转移具有如下一侧的层,即,所述一侧的表面形貌与该临时衬底的表面形貌相匹配。
Claims (9)
1.一种用于使用临时衬底(5)将有源层(2)转移至最终衬底(4)的处理,所述有源层(2)包括具有特定表面形貌的第一侧(1),所述处理包括以下步骤:
-将所述有源层(2)的所述第一侧(1)结合到所述临时衬底(5)的一侧的第一步骤;
-将所述有源层(2)的第二侧(6)结合到所述最终衬底(4)的第二步骤;以及
-将所述有源层(2)和所述临时衬底(5)分开的第三步骤;
所述处理的特征在于,所述临时衬底(5)的所述一侧具有与所述有源层(2)的所述第一侧(1)的所述表面形貌互补的表面形貌,使得在结合的所述第一步骤中,所述临时衬底(5)的所述表面形貌封装所述有源层(2)的所述第一侧(1)的所述表面形貌。
2.根据权利要求1所述的转移处理,其中,所述临时衬底(5)的所述表面形貌通过蚀刻按照预设几何结构和预设尺寸来产生。
3.根据权利要求2所述的转移处理,其中,所述临时衬底(5)的所述蚀刻几何结构和尺寸以增加至少5%的方式与所述有源层(2)的所述第一侧(1)的所述表面形貌的几何结构和尺寸相对应。
4.根据权利要求2所述的转移处理,其中,所述临时衬底(5)的所述蚀刻形成凹部(7),所述凹部(7)例如是矩形,所述凹部(7)的深度和宽度以增加至少5%的方式分别与产生于所述有源层(2)的所述第一侧(1)的所述表面形貌的最大高度(h)和最大宽度(1)相对应。
5.根据权利要求1所述的转移处理,其中,在所述第一步骤和所述第二步骤之间,在所述有源层(2)的第二侧(6)上实施薄化所述有源层(2)的步骤。
6.根据权利要求1所述的转移处理,其中,所述有源层(2)的所述第一侧(1)的所述特定表面形貌包括至少一个平坦部分和至少一个非平坦部分。
7.根据权利要求6所述的转移处理,其中,当所述有源层(2)的所述第一侧(1)被结合至所述临时衬底(5)的所述一侧时,仅所述有源层(2)的所述第一侧(1)的所述平坦部分被结合。
8.根据权利要求6或7所述的转移处理,其中,所述有源层(2)的所述第一侧(1)的所述平坦部分的面积大于所述非平坦部分的面积。
9.根据权利要求1所述的转移处理,其中,将所述有源层(2)的所述第一侧(1)结合至所述临时衬底(5)的一侧是通过在低于500℃的温度下的热处理加强的直接结合。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4321613A (en) * | 1978-05-31 | 1982-03-23 | The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland | Field effect devices and their fabrication |
CN1392214A (zh) * | 2001-06-14 | 2003-01-22 | 索尼化学株式会社 | 剥离膜以及使用剥离膜的粘合膜 |
CN1721160A (zh) * | 2004-06-10 | 2006-01-18 | Tdk股份有限公司 | 压模、刻印方法及信息记录媒体制造方法 |
JP2010062414A (ja) * | 2008-09-05 | 2010-03-18 | Sumco Corp | 裏面照射型固体撮像素子用ウェーハの製造方法 |
CN103249562A (zh) * | 2010-12-09 | 2013-08-14 | 旭化成株式会社 | 微细结构积层体、微细结构积层体的制作方法以及微细结构体的制造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11297972A (ja) | 1998-04-10 | 1999-10-29 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2003142666A (ja) | 2001-07-24 | 2003-05-16 | Seiko Epson Corp | 素子の転写方法、素子の製造方法、集積回路、回路基板、電気光学装置、icカード、及び電子機器 |
JP2007158231A (ja) | 2005-12-08 | 2007-06-21 | Seiko Epson Corp | 基板の加工方法、保護基板及び電子機器 |
JP5499428B2 (ja) * | 2007-09-07 | 2014-05-21 | 株式会社Sumco | 貼り合わせウェーハの製造方法 |
FR2926671B1 (fr) | 2008-01-17 | 2010-04-02 | Soitec Silicon On Insulator | Procede de traitement de defauts lors de collage de plaques |
FR2938202B1 (fr) * | 2008-11-07 | 2010-12-31 | Soitec Silicon On Insulator | Traitement de surface pour adhesion moleculaire |
KR101144842B1 (ko) * | 2010-06-08 | 2012-05-14 | 삼성코닝정밀소재 주식회사 | 접합기판 제조방법 |
US8202786B2 (en) * | 2010-07-15 | 2012-06-19 | Infineon Technologies Austria Ag | Method for manufacturing semiconductor devices having a glass substrate |
KR101354491B1 (ko) * | 2012-01-26 | 2014-01-23 | 전북대학교산학협력단 | 고효율 발광다이오드 제조방법 |
KR101291092B1 (ko) | 2012-04-06 | 2013-08-01 | 주식회사 씨티랩 | 반도체 소자 구조물을 제조하는 방법 |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4321613A (en) * | 1978-05-31 | 1982-03-23 | The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland | Field effect devices and their fabrication |
CN1392214A (zh) * | 2001-06-14 | 2003-01-22 | 索尼化学株式会社 | 剥离膜以及使用剥离膜的粘合膜 |
CN1721160A (zh) * | 2004-06-10 | 2006-01-18 | Tdk股份有限公司 | 压模、刻印方法及信息记录媒体制造方法 |
JP2010062414A (ja) * | 2008-09-05 | 2010-03-18 | Sumco Corp | 裏面照射型固体撮像素子用ウェーハの製造方法 |
CN103249562A (zh) * | 2010-12-09 | 2013-08-14 | 旭化成株式会社 | 微细结构积层体、微细结构积层体的制作方法以及微细结构体的制造方法 |
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