CN105654906B - 像素电路及其驱动方法、显示面板以及显示装置 - Google Patents
像素电路及其驱动方法、显示面板以及显示装置 Download PDFInfo
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Abstract
本发明的实施例提供像素电路及其驱动方法、显示面板以及显示装置。像素电路包括复位模块、数据写入模块、存储模块、补偿和保持模块、驱动模块以及发光器件。复位模块与存储模块以及发光器件连接,被配置为复位存储模块以及发光器件。数据写入模块与驱动模块连接,被配置为用于提供数据电流。补偿和保持模块与驱动模块以及存储模块连接,被配置为产生用于驱动模块的控制电压,其中控制电压是基于数据电流的函数。存储模块与驱动模块连接,被配置为存储控制电压。驱动模块与发光器件连接,被配置为根据控制电压产生驱动电流。发光器件被配置为由驱动电流驱动而发光。像素电路可以在不增加发光器件功耗的情况下,提高发光效率。
Description
技术领域
本发明涉及显示技术,尤其涉及像素电路及其驱动方法、显示面板以及显示装置。
背景技术
目前典型的量子点发光二极管(QLED)结构包括电子传输层、空穴传输层以及量子点发光层。空穴传输层以及电子传输层可以由有机小分子、有机聚合物或者无机金属氧化物构成。空穴传输层与电子传输层的设置能够使量子点发光二极管的发光效率从最初的低于0.1%提升到约10%,但是空穴传输层与量子点发光层之间最高占据分子轨道(HighestOccupied Molecular Orbital,HOMO)能级的不匹配使得量子点电荷注入效率仍然普遍偏低,并且量子点注入电荷不平衡,量子点呈现非电中性。与传统的有机电致发光二极管(OLED)比较,量子点电致发光二极管(QLED)的电荷注入不平衡的缺点,限制了其发光寿命和效率。
现有技术中,主要采用以下三种方式对于该问题进行改善。第一种方式是提高空穴传输层的HOMO能级以与量子点发光材料的HOMO能级尽可能匹配。第二种方式是通过设置空穴增强层来增加空穴的迁移率与注入效率。第三种方式是通过设置电子阻挡层来减缓电子的注入速率,提升电子与空穴的复合效率。在第一种方式中,难以合成或找到构成该空穴传输层所需的材料。在第二种方式中,需要设置多层空穴传输层,增加了工艺制作的难度。在第三种方式中,并不能增加被激发的光子,因此难以提升发光效率。
发明内容
本发明的实施例提供了像素电路及其驱动方法、显示面板以及显示装置,用于提高发光器件的发光效率。
根据本发明的第一个方面,提供了一种像素电路,包括:复位模块、数据写入模块、存储模块、补偿和保持模块、驱动模块以及发光器件。复位模块与存储模块以及发光器件连接。数据写入模块与驱动模块连接。补偿和保持模块与驱动模块以及存储模块连接。存储模块与驱动模块连接,被配置为存储控制电压。驱动模块与发光器件连接。
在本发明的实施例中,复位模块被配置为复位存储模块以及发光器件。数据写入模块被配置为用于提供数据电流。补偿和保持模块被配置为产生用于驱动模块的控制电压,其中控制电压是基于数据电流的函数。并且,补偿和保持模块还被配置为用于保持控制电压。存储模块被配置为存储控制电压。驱动模块被配置为根据控制电压产生驱动电流。发光器件被配置为由驱动电流驱动而发光。
在本发明的实施例中,补偿和保持模块包括第三晶体管,第三晶体管的控制极与第二电压线连接,第一极与第一电压线连接,第二极与驱动模块以及存储模块连接。
在本发明的实施例中,复位模块包括第四晶体管,第四晶体管的控制极与第二电压线连接,第一极与存储模块以及发光器件连接,第二极与第三电压线连接。
在本发明的实施例中,驱动模块包括第二晶体管,第二晶体管的第一极与第一电压线连接,并且存储模块被连接在第二晶体管的控制极和第二极之间。
在本发明的实施例中,数据写入模块包括第一晶体管,第一晶体管的控制极与第二电压线连接,第一极与驱动模块连接,第二极与数据电流线连接。
在本发明的实施例中,存储模块包括电容,并且,驱动模块被连接在电容的第一端和第二端之间。
在本发明的实施例中,晶体管是N型MOS管。
在本发明的实施例中,晶体管是P型MOS管。
根据本发明的第二个方面,提供了一种用于驱动上述像素电路的方法,包括第一阶段以及第二阶段。在第一阶段中,通过数据写入模块提供数据电流,并且使驱动模块、数据写入模块、补偿和保持模块和复位模块导通,以使得补偿和保持模块产生控制电压,存储模块存储控制电压,其中控制电压是基于数据电流的函数。在第二阶段,使驱动模块导通,并且使数据写入模块、补偿和保持模块、和复位模块截止,以使得驱动模块根据存储模块存储的控制电压产生驱动电流,发光器件在驱动电流的驱动下发光。
根据本发明的第三个方面,提供了一种显示面板,包括上述像素电路。
根据本发明的第四个方面,提供了一种显示装置,包括上述显示面板。
根据本发明的实施例的像素电路及其驱动方法、显示面板以及显示装置,能够使得驱动模块在驱动发光器件时提供与数据电流相等的驱动电流,在不增加发光器件功耗的情况下,提高了驱动电流。驱动电流的提高增加了注入到发光器件的电荷,提高了发光效率,克服了传统的电压补偿电路为了增加流入发光二极管的驱动电流需要增加发光器件功耗的弊端。
附图说明
为了更清楚地说明本发明的实施例的技术方案,下面将对实施例的附图进行简要说明,应当知道,以下描述的附图仅仅涉及本发明的一些实施例,而非对本发明的限制,其中:
图1是根据本发明的第一实施例的像素电路1的框图;
图2是根据本发明的第二实施例的用于驱动像素电路1的方法;
图3是图1所示实施例的像素电路1的示意性的电路图;
图4是图3所示像素电路1的信号时序图。
具体实施方式
为了使本发明的实施例的目的、技术方案和优点更加清楚,下面将结合附图,对本发明的实施例的技术方案进行清楚、完整的描述。显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。基于所描述的本发明的实施例,本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例,也都属于本发明保护的范围。
图1是根据本发明的第一实施例的像素电路1的框图。如图1所示,像素电路1包括:复位模块2、数据写入模块3、存储模块4、补偿和保持模块5、驱动模块6以及发光器件Di。复位模块2与存储模块4以及发光器件Di连接。数据写入模块3与驱动模块6连接。补偿和保持模块5与驱动模块6以及存储模块4连接。存储模块4与驱动模块6连接。驱动模块6与发光器件Di连接。
复位模块2被配置为复位存储模块4以及发光器件Di。数据写入模块3被配置为用于提供数据电流。补偿和保持模块5被配置产生用于驱动模块的控制电压,其中控制电压是基于数据电流的函数。并且,补偿和保持模块5还被配置为保持控制电压。存储模块4被配置为存储控制电压。驱动模块6被配置为根据控制电压产生驱动电流。发光器件Di被配置为由驱动电流驱动而发光。
图2是根据本发明的第二实施例的用于驱动像素电路1的方法。如图2所示,本发明的第二实施例提供了驱动上述像素电路1的方法,包括第一阶段以及第二阶段。在第一阶段中,通过数据写入模块3提供数据电流,并且使驱动模块6、数据写入模块3、补偿和保持模块5和复位模块2导通,以使得补偿和保持模块5产生控制电压,存储模块4存储控制电压,其中控制电压是基于数据电流的函数。在第二阶段,使驱动模块6导通,并且使数据写入模块3、补偿和保持模块5、和复位模块2截止,以使得驱动模块6根据存储模块4存储的控制电压产生驱动电流,发光器件Di在驱动电流的驱动下发光。
根据本发明的实施例,提供了能够进行电流补偿驱动的像素电路1。在该像素电路1中,通过数据写入模块3向像素电路1写入数据电流时,存储模块4存储控制电压。并且,在补偿和保持模块5的作用下,该控制电压与数据电流相关,能够使驱动模块6产生与数据电流相等的驱动电流。因此,驱动模块6在基于存储模块4存储的电压驱动发光器件Di时能够提供与数据电流相等的驱动电流。根据本发明的实施例,在不增加发光器件Di功耗的前提下增大了驱动电流,提高了发光效率,从而克服了传统的电压补偿电路为了增加流入发光二极管的驱动电流需要增加发光器件Di功耗的弊端。
图3是图1所示实施例的像素电路1的示意性的电路图。如图3所示,数据写入模块3包括第一晶体管,第一晶体管的控制极与第二电压线连接,第一极与驱动模块6连接,第二极与数据电流线连接。驱动模块6包括第二晶体管,第二晶体管的第一极与第一电压线连接,并且存储模块4被连接在第二晶体管的控制极和第二极之间。补偿和保持模块5包括第三晶体管,第三晶体管的控制极与第二电压线连接,第一极与第一电压线连接,第二极与驱动模块6连接。复位模块2包括第四晶体管,第四晶体管的控制极与第二电压线连接,第一极与存储模块4和驱动模块6连接,第二极与第三电压线连接。存储模块4包括电容,并且,驱动模块6被连接在电容的第一端和第二端之间。
具体而言,第一晶体管TR1的第一极与第二晶体管TR2的第二极连接,第二极与数据电流线Data连接,控制极与第二电压线EM连接。第二晶体管TR2的第一极与第一电压线Vdd连接,并且电容C被连接在第二晶体管TR1的控制极和第二极之间。第三晶体管TR3的控制极与第二电压线EM连接,第一极与第一电压线Vdd连接,第二端与第二晶体管TR2的控制极连接。第四晶体管TR4的控制极与第二电压线EM连接,第一极与第三电压线VGL连接,第二极与第二晶体管TR2的第二极连接。电容C被连接在第二晶体管TR2的控制极和第二极之间。发光器件Di的阳极与第二晶体管TR2的第二极连接,阴极与第四电压端Ca连接。
晶体管可以是N型MOS管,也可以是P型MOS管,在使用不同类型的晶体管时,电路结构相同,为了使晶体管导通而施加的控制电压不同。以下,以晶体管均为N型MOS管为例说明图2所示像素电路1的工作过程。
图4是图3所示像素电路1工作时的信号时序图。如图4所示,像素电路1工作过程包括第一阶段和第二阶段。
在第一阶段t1,在第二电压线EM施加高电平电压V2,此高电平的电压使得与第二电压线EM连接的晶体管TR1、TR3以及TR4导通。在第一电压线Vdd上施加低电平的电压VL,在发光器件Di阴极上施加低电平的电压Vcom,并且使得VL<Vcom,没有电流流过发光器件Di,发光器件Di截止而不发光。在数据电流线Data上施加牵引电流,由于第一晶体管TR1导通,第三晶体管TR3导通使得第二晶体管TR2形成二极管连接,流过第二晶体管TR2的电流A受流过数据电流线Data的牵引电流控制,与牵引电流相等,并且电流A沿着图示箭头方向流动。因为第二晶体管TR2栅源极电压与流过漏极和源极之间的电流成固定的函数关系,所以第二晶体管TR2栅源极电压变化为与电流A相关的Vgs,也由牵引电流控制。电容C逐渐充电,并且最终在电容C两端存储电压Vgs。此外,第三晶体管TR3源漏极之间的内部电容也存储了此时第二晶体管TR2的源漏极的电压Vgd。
此外,在第三电压线VGL上施加低电平的电压V3,由于第四晶体管TR4导通,第二晶体管TR2的第二极、电容C的第二端以及发光器件Di的阳极的被复位为电压V3,低电平的电压V3的作用在于消除电容C、第二晶体管TR2中残留电荷对于电流A的影响,并且能够更可靠地使发光器件Di截止。
在第二阶段t2,在第二电压线EM上施加低电平的电压V2’,此低电平的电压使得晶体管TR1、TR3以及TR4截止。此时在第一电压线Vdd施加高电平的电压VH(VH>Vcom),发光器件Di导通,电流流过发光器件Di发光。由于电容C上的电压不会变化,所以第二晶体管TR2栅极和源极的电压与第一阶段t1中的Vgs相同,并且第三晶体管TR3截止时,由于其内部电容的作用,对于第二晶体管TR2栅漏极电压Vgd具有保持的作用,所以流过第二晶体管TR2的驱动电流与第一阶段t1中流过第二晶体管TR2的电流A相等。
根据本发明的实施例,通过调节第一阶段t1中数据电流线Data上的牵引电流值,可以改变第二阶段t2中流入发光二极管的驱动电流,进而使得发光器件Di具有最佳发光效率。因此,本发明的实施例提供的像素电路1可以在不改变发光器件Di的结构的情况下,提高发光效率。这对于量子点电致发光器件的效果更为明显,在使用量子点电致发光器件时,采用本发明的实施例提供的像素电路1增加了注入发光器件Di的电流,提高了空穴注入速率与注入效率,进而提高了空穴与电子的复合几率,提高了发光器件Di的发光效率。本发明的实施例提供的像素电路1克服了传统的电压补偿电路中,只要增加驱动电路就会增加器件功耗的缺点。
根据本发明的第三实施例,提供了一种显示面板,包括上述像素电路1。
根据本发明的第四实施例,提供了一种显示装置,包括上述显示面板。显示装置可以是电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框以及导航仪等任何具有显示功能的产品或部件。
需要说明的是,在上述描述中,高电平、低电平仅仅表示该电压可以实现的功能,并没有对于电压值进行具体的限制,例如在第二电压线EM上施加的高电平的电压V2只要使得晶体管TR1、TR3以及TR4导通即可,而低电平的电压V2’只要使得晶体管TR1、TR3以及TR4截止即可。在第一电压线Vdd、第三电压线VGL和发光器件Di的阴极分别施加的低电平的电压VL、V3和Vcom只要使得发光器件Di截止,而电流A能够按照图2中所示的方向流动即可。在第一电压线Vdd上施加的高电平的电压VH和在发光器件Di的阴极施加的低电平的电压Vcom只要使得发光器件Di导通即可。
此外,在晶体管是P型MOS管时,用于使晶体管导通的电压发生改变,简单来说,在第一阶段t1中,在第二电压线EM上施加低电平的电压V2使得晶体管TR1、TR3以及TR4导通。而在第二阶段t2中,在第二电压线EM上施加高电平的电压V2’使得晶体管TR1、TR3以及TR4截止。
此外,晶体管的第一极是指源极和漏极中的一个,第二极是指源极和漏极中的另一个。对于每个晶体管,第一极和第二极都是可以单独确定的,也就是说不同晶体管的第一极可以相同,也可以不同,同理,第二极可以相同,也可以不同。因此,使用第一极和第二极的描述仅仅是为了更方便的说明本发明的原理,并不是对于本发明的限定。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。
Claims (8)
1.一种像素电路,包括:复位模块、数据写入模块、存储模块、补偿和保持模块、驱动模块以及发光器件;
所述复位模块与所述存储模块以及所述发光器件连接;
所述数据写入模块与所述驱动模块连接;
所述补偿和保持模块与所述驱动模块以及所述存储模块连接;
所述存储模块与所述驱动模块连接;
所述驱动模块与所述发光器件连接;
其中,
所述复位模块被配置为复位所述存储模块以及所述发光器件;
所述数据写入模块被配置为用于提供数据电流;
所述补偿和保持模块被配置为产生用于所述驱动模块的控制电压,其中所述控制电压是基于所述数据电流的函数;并且,所述补偿和保持模块还被配置为用于保持所述控制电压;
所述存储模块被配置为存储所述控制电压;
所述驱动模块被配置为根据所述控制电压产生驱动电流;
所述发光器件被配置为由所述驱动电流驱动而发光;
其中,所述补偿和保持模块包括第三晶体管,所述第三晶体管的控制极与第二电压线连接,第一极与第一电压线连接,第二极与所述驱动模块以及所述存储模块连接;
其中,所述复位模块包括第四晶体管,所述第四晶体管的控制极与第二电压线连接,第一极与所述存储模块以及所述发光器件连接,第二极与第三电压线连接;
其中,所述数据写入模块包括第一晶体管,所述第一晶体管的控制极与第二电压线连接,第一极与驱动模块连接,第二极与数据电流线连接。
2.如权利要求1所述的像素电路,其中,所述驱动模块包括第二晶体管,所述第二晶体管的第一极与第一电压线连接,并且所述存储模块被连接在所述第二晶体管的控制极和第二极之间。
3.如权利要求1所述的像素电路,其中,所述存储模块包括电容,并且,所述驱动模块被连接在所述电容的第一端和第二端之间。
4.如权利要求1至3中任一项所述的像素电路,其中,晶体管是N型MOS管。
5.如权利要求1至3中任一项所述的像素电路,其中,晶体管是P型MOS管。
6.一种用于驱动如权利要求1至5中任一项的像素电路的方法,包括第一阶段以及第二阶段;
在第一阶段中,通过所述数据写入模块提供数据电流,并且使所述驱动模块、所述数据写入模块、所述补偿和保持模块和所述复位模块导通,以使得所述补偿和保持模块产生控制电压,所述存储模块存储控制电压,其中控制电压是基于数据电流的函数;
在第二阶段,使所述驱动模块导通,并且使所述数据写入模块、所述补偿和保持模块、和所述复位模块截止,以使得所述驱动模块根据所述存储模块存储的控制电压产生驱动电流,发光器件在驱动电流的驱动下发光。
7.一种显示面板,包括如权利要求1至5中任一项所述的像素电路。
8.一种显示装置,包括如权利要求7所述的显示面板。
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US10446082B2 (en) | 2019-10-15 |
WO2017128624A1 (zh) | 2017-08-03 |
US20180053469A1 (en) | 2018-02-22 |
EP3413295A4 (en) | 2019-08-14 |
CN105654906A (zh) | 2016-06-08 |
EP3413295A1 (en) | 2018-12-12 |
US20180301089A9 (en) | 2018-10-18 |
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