CN105609477B - 用于制造功率半导体模块的方法 - Google Patents
用于制造功率半导体模块的方法 Download PDFInfo
- Publication number
- CN105609477B CN105609477B CN201510564791.5A CN201510564791A CN105609477B CN 105609477 B CN105609477 B CN 105609477B CN 201510564791 A CN201510564791 A CN 201510564791A CN 105609477 B CN105609477 B CN 105609477B
- Authority
- CN
- China
- Prior art keywords
- connection
- module housing
- connection conductor
- conductor
- housing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000000034 method Methods 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000001465 metallisation Methods 0.000 claims abstract description 27
- 239000004020 conductor Substances 0.000 claims description 89
- 239000000463 material Substances 0.000 claims description 11
- 239000000919 ceramic Substances 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 6
- 238000005245 sintering Methods 0.000 claims description 3
- 238000001746 injection moulding Methods 0.000 claims description 2
- 230000011218 segmentation Effects 0.000 claims 8
- 239000000203 mixture Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000005476 soldering Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 229910001369 Brass Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 239000010951 brass Substances 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4817—Conductive parts for containers, e.g. caps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4885—Wire-like parts or pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
- H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K5/00—Casings, cabinets or drawers for electric apparatus
- H05K5/10—Casings, cabinets or drawers for electric apparatus comprising several parts forming a closed casing
- H05K5/13—Casings, cabinets or drawers for electric apparatus comprising several parts forming a closed casing assembled by screws
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13062—Junction field-effect transistor [JFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Geometry (AREA)
- Inverter Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Connections By Means Of Piercing Elements, Nuts, Or Screws (AREA)
Abstract
本发明的一方面涉及一种功率半导体模块。其具有模块壳体(6)、以及具有介电的绝缘载体(20)和上金属化层(21)的电路载体(2),该上金属化层被施加在介电的绝缘载体(20)的上侧(20t)上。半导体构件(1)被设置在电路载体(2)上。此外,功率半导体模块具有导电的连接块(5),其与电路载体(2)和/或半导体构件(1)固定地和导电地相连接并且具有螺纹(50),该螺纹从模块壳体(6)的外侧是可达到的。
Description
技术领域
本发明涉及一种用于制造功率半导体模块的方法。
背景技术
功率半导体模块为其模块外部的电接触而需要连接端。在传统的半导体模块中,为此通常使用连接片,其具有脚区域,在该脚区域其与半导体模块的电路载体焊接,以及连接端区域,在连接端区域从模块壳体突出。由于这种连接片的热容量,通过脚区域的焊接来连接电路载体的强的热负载,这能够导致,电路载体和/或通过其预装入电路载体的电构件被损坏或毁坏。
半导体模块的电连接端的另一个问题在于电感。当电的连接端例如用于为设置在半导体模块中的可控的半导体开关(例如IGBT、MOSFET等)引入控制信号、例如门极控制电压时,则由于电连接端的电感能够出现开关故障,这导致可控的半导体开关延迟地或者提早地接通或者关断。
替代连接片通常使用单个连接引脚,其分别具有第一端,该第一端被设置在模块壳体的内部,以及第二端,该第二端从模块壳体中突出。第一端在模块壳体中与开关载体的金属化结构相连接,而第二端接通至模块外部的导体卡。为了使第二端与模块外部的导体卡相连接,通常将第二端压入导体卡的对应的连接开口中。在此,导体卡被压紧在从模块壳体突出的第二端上,这显然要求相应的高的力,该力通过连接引脚被传递至开关载体。该力导致开关载体的机械负载,通过其能够损坏开关载体。此外,第二端必须相对彼此以较高的精确度定位,使得其在将导体卡安装在半导体模块时对准接触开口。然而这种精确的定位关联高的耗费。例如,两端的定向必须在半导体模块的实质完成后被检查并且在必要时通过弯曲来校正,因为导体卡在其它情况下不能够安装。当模块壳体具有带有开口的壳体盖时,出现一个相似的问题,连接引脚必须穿过该开口。除此之外将单个连接引脚安装在电路载体上也是十分耗费的,因为该单个连接引脚必须分别被定位在电路载体的预定的位置处并且在那与电路载体相连接。
此外,电连接端的模块内部的电连接需要用于相应的连接导线的大量空间。一方面半导体模块包含大量其他的元件、例如焊线或母线,使得在安置连接导线时必须绕路,另一方面连接导线必须包含至半导体模块的其他元件的最小间距,以例如避免电压飞弧和漏电流。
由DE 10 2011 087 353 A1已知一种具有壳体的半导体装置,具有安装在其上的半导体元件的衬底位于该壳体中。与衬底钎焊在一起的主电极从壳体向外引出并且在其外侧处弯曲,从而使得主电机平行于壳体上侧延伸并且由此覆盖在壳体上侧处插入壳体的螺母。在其背向该壳体的一侧处螺母与主电极焊接在一起。
在DE 10 2006 051 454 A1中描述了一种半导体装置,具有基板和处于该基板上的绝缘的衬底,以及布置在该绝缘的衬底上的布线图案层。在该布线图案层上钎焊有IGBT芯片和二极管芯片。主接头和中间芯片接头用于模块外部电布线,它们分别与布线图案层中的一个或芯片中的一个钎焊在一起。为了制造壳体,该布置以树脂来浇注成型。
DE 10 2011 075 154 A1描述了一种具有母壳体的半导体装置,在母壳体内侧具有多个安全元件,螺旋接线柱能够被旋拧到安全元件中,使得螺旋接线柱中的每个具有三个插头部段。在插头部段中的每个处连接一个弯曲的部段,以及紧接着的一个接线柱底部部段,在接线柱底部部段处,螺旋接线柱与半导体载体衬底钎焊在一起。
在DE 10 2012 212 119 A1以及类似的在JP 2011 108 817 A1中,描述了一种具有散热基板和芯片安装衬底的功率半导体装置。在芯片安装衬底上布置有开关装置和续流二极管。此外弯曲的电极被焊接在芯片安装衬底的条形导体上。绝缘材料有散热基板开始延伸直到经过开关装置和续流二极管,其中电极的触点端部从绝缘材料向外伸出。
发明内容
本发明的任务在于,提供一种用于简单制造功率半导体模块的方法,其具有至少一个电连接端,该连接端能以简单的方式被连接并且其能够没有功率半导体的组件的毁坏危险地制造。
该任务通过根据权利要求1所述的用于制造功率半导体模块的方法来完成。本发明的设计方案和改进是从属权利要求的主题。
在一种用于制造功率半导体模块的方法中提供具有螺纹的导电的连接块、具有第一分段和第二分段的连接导体以及模块壳体。电路载体具有介电的绝缘载体,以及上金属化层,所述上金属化层被施加在所述介电的绝缘载体的上侧上。以所述半导体构件装配所述电路载体并且在所述第一分段处制造在所述连接块和所述连接导体之间的固定的并且导电的连接。此外,在所述第二分段处制造在所述电路载体或所述半导体构件与所述连接导体之间的材料连接的和导电的连接。将所述连接块和以所述半导体构件装配的所述电路载体如此设置在模块壳体处,使得所述半导体构件被设置在所述模块壳体中并且所述螺纹从所述模块壳体的外侧是可达到的。其中具有所述连接导体和所述连接块的单元能够如此地固定在所述壳体或者壳体部分处,使得所述第二分段在将预装配的所述电路载体安装在所述壳体或者所述壳体部分时达到正确的目标位置,从而仅需要制造在所述第二分段和在其上实现所述电路载体的电路之间的连接,而无需实现所述第二分段相对于电路的另外的定位。
所述功率半导体模块还具有另外的导电的连接块和另外的连接导体。所述另外的导电的连接块具有另外的螺纹,并且所述另外的螺纹从所述模块壳体的外侧是可达到的。所述另外的连接导体具有另外的第一分段,在所述另外的第一分段处所述另外的连接导体在另外的第一连接位置处与所述另外的连接块固定且导电地相连接,所述另外的连接导体还具有另外的第二分段,在所述另外的第二分段处所述另外的连接导体在另外的第二连接位置处与所述电路载体和/或与所述半导体构件材料连接地和导电地相连接;并且其中,所述连接导体和所述另外的连接导体在至少30mm的长度上并行引导,并且在所述连接导体和所述另外的连接导体并行引导的区域中具有最高5mm的间距。
附图说明
本发明的该些或者其他方面将在下文中根据参照所附附图的多个实施例进行阐述。其中:
图1示出了两个分别具有螺纹的连接块的透视图,该些连接块分别材料连接地并且导电地与连接导体相连接;
图2示出了半导体模块的截面图,该半导体模块包含两个分别具有内螺纹的连接块,其中每个连接块借助于连接导体材料连接地并且导电地与电路载体相连接;
图3示出了两个在图1中所示的、分别材料连接地并且导电地与连接导体相连接的连接块的不同的图示;
图4A示出了模块壳体的分段的透视顶视图,在图1和图3中示出的连接导体喷射到该模块壳体中;
图4B示出了根据图4A的结构的侧视图;
图4C示出了根据图4A的结构的透视底视图;
图5示出了半导体模块的截面图,该半导体模块包含两个分别具有外螺纹的连接块,其中每个连接块借助于连接导体材料连接地并且导电地与电路载体相连接;以及
图6示出了两个半导体模块的透视顶视图,其中每个半导体模块包含多个具有内螺纹的连接块,在该些连接块处螺纹连接导体盘并且因此导电地与半导体模块相连接。
在附图中的图示不是按比例的。如果不另外说明,在附图中相同的附图标记表示相同的或相同作用的元件。
具体实施方式
图1示出了两个导电的连接块5的总览图。每个连接块5具有带有螺纹轴a的螺纹50,在此仅示例性地为内螺纹。此外,对于每个连接块5存在具有第一分段41和第二分段42的连接导体4。在其第一分段41处,每个连接导体4在第一连接位置处与隶属的连接块5固定地并且导电地相连接。该第一连接位置能够例如位于连接块5的相对于螺纹50的侧面,然而也能够位于其他位置。
在连接块5和连接导体4之间的连接能够是材料连接并且例如被构造为钎焊连接(硬钎焊连接或者软钎焊连接)或者焊接连接(例如通过激光焊接制造)。在钎焊连接的情况下,使用的焊料或者邻接连接导体4或者邻接连接块5,并且在焊接连接的情况下连接导体4邻接连接块5。
在连接块5和连接导体4之间的连接也能够被构造为铆接并且例如以摇摆铆接方法(Taumelnietverfahren)制作。在此,连接导体4在其第一分段41处从其相对于内螺纹的底侧插入连接块5的预制的孔或者别的开口中,使得连接导体4的构造在第一分段41处的自由端在连接块5的另外的孔中突出,该另外的孔形成内螺纹的开口或者用于该内螺纹。该内螺纹能够在执行摇摆铆接方法之前或之后在另外的孔的区域中产生。
在制造在连接块5和连接导体4之间的连接之前,连接导体4能够适应于半导体模块的预定的结构而弯曲,之后在该半导体模块中构造该连接导体。在此连接导体4能够例如由金属片冲孔并且然后弯曲成期望的最终形状,在该最终形状中该连接导体也具有在其半导体模块中构造的状态。
在连接块5和连接导体4之间的连接能够基本上在连接导体4弯曲之前或之后实现,然而也在两个弯曲步骤之间实现,在该两个弯曲步骤中连接导体4被分别地弯曲。
第二分段42用于将相应的连接导体4与半导体模块100的元件、例如电路载体2或者半导体芯片1电地和机械地相连接。相应的连接能够例如通过钎焊、通过含金属粉末的膏体的烧结(例如含有银粉末的膏体)、通过焊接或者通过导通粘结剂的导电粘结来制成。在此图2作为示例示出了通过半导体模块100的横截面。
半导体模块100具有电绝缘的模块壳体6,以及电路载体2,其与模块壳体6例如通过粘结、材料连接进行连接。
模块壳体6能够例如包含壳体框架61,以及壳体盖62,其设置在壳体框架61之上。
电路载体2具有带有上侧20t的介质绝缘载体20,在该介质绝缘载体上施加有上金属化层21,以及可选的下金属化层22,其被施加在介质绝缘载体20的背对上侧20t的下侧20b上。只要存在上金属化层21和下金属化层22,其能够位于绝缘载体20的彼此相对的侧上。上金属化层21能够根据需求被结构化,使得其具有分段211、212、213和214,这些分段能够用于电接线和/或用于芯片安装。介质绝缘载体20能够被用于,将上金属化层21和下金属化层22彼此电绝缘。
电路载体2能够是陶瓷基底,在此绝缘载体20被构造为薄的层,其具有陶瓷或者由陶瓷组成。用于上金属化层21和——只要存在——下金属化层22的材料适合为导电良好的金属,例如铜或者铜合金、铝或者铝合金,然而也能够是任意其他的金属或者合金。只要绝缘载体20具有陶瓷或者由陶瓷组成,该陶瓷能够为例如氧化铝(Al2O3)或者氮化铝(AIN)或者氮化硅(Si3N4)或者氧化锆(ZrO2),或者为复合陶瓷,其除了至少一个所谓的陶瓷材料之外还具有至少一个另外的、与之不同的陶瓷材料。例如电路载体2能够被构造为DCB-基底(DCB:直接铜键合)、DAB-基底(DAB:直接铝键合)、AMB-基底(AMB:活性金属钎)或者IMS-基底(IMS:绝缘金属基底)。上金属化层21和——只要存在——下金属化层22能够彼此独立地分别具有在0.05mm至2.5mm范围内的厚度。绝缘载体20的厚度能够例如在0.1mm至2mm的范围内。然而比给出的厚度更大的或者更小的厚度也同样是可能的。
电路载体2能够装配有一个或者多个电子构件1。基本上能够使用任意的电子构件1。尤其地,这种电子构件1能够包含任意有源和无源的电子构件。这也是可能的,在电子构件1中集成一个或多个有源的电子构件以及一个或多个无源的电子构件。每个电子构件1具有第一电极11和至少一个第二电极12。
例如电子构件1能够被构造为半导体芯片或者具有半导体主体10。电极11和12于是能够分别为芯片金属化结构,其被施加在半导体主体10之上。
构件1能够例如包含二极管,或者可控的半导体开关,其能够通过控制输入端13(例如门极输入端或基极输入端)受控,例如MOSFET(金氧半场效晶体管)、IGBT(绝缘栅双极型晶体管)、晶闸管、JFET(结型场效应管)、HEMT(高电子迁移率晶体管)。构件1的第一电极11和第二电极12能够例如为所涉及的构件的阳极或阴极、阴极或阳极、源极或漏极、漏极或源极、发射极或集电极或者集电极或发射极。
在所示出的示例中,构件1在其电极12材料连接地和导电地与上金属化层21的分段相连接。相应的连接能够例如通过钎焊、含金属粉末的膏体的烧结(例如含有银粉末的膏体)或者通过导电粘结来制成。分别根据在电路载体2上待实现的电路的需求,电子构件1能够以任意的方式导通至电路载体2和/或待制造的功率半导体模块的其他元件。在此在图2中仅示出了的例如键合线3,其通过键合方式在第一键合位置处键合至上金属化层21的分段,以及在第二键合位置处键合至构件1的第一电极11。
由此,如果使用一个或多个连接块5,在电路载体2上实现的电子电路能够从半导体模块100的外侧、即从模块壳体6的外侧根据螺纹连接来电接触,其螺纹50分别从模块壳体6的外侧是可到达的。螺纹50、在此示例性地仅为内螺纹,能够例如被用于,将导体卡、实心的金属的总线导轨、扁平带导体、连接孔等使用螺纹50地与连接块5螺纹连接。
如根据图2示出的半导体模块100所示的,能够通过使用连接导体4来实现在连接块5和在电路载体2上实现的电路之间的模块内的电连接,其参照图1所示在其第一分段41处固定地并且导电地与连接块5相连接,并且在其第二分段42处导电地与在电路载体2上实现的电路相连接。
连接导体4能够在其第二分段处通过基本上任意的连接技术导电地与在电路载体上实现的电路相连接。在所示的示例中,连接导体4分别在其第二分段42处与电路载体2的上金属化层21的分段相连接。这些连接能够例如被构造为材料连接,例如为钎焊连接、为使用导电粘结剂的粘结连接、为焊接连接(例如通过激光焊接或者通过超声波焊接来制造)。在钎焊或者粘结连接的情况下,焊剂或者导通粘结剂被用作连接装置,其既邻近第二分段42又邻近上金属化层21。
同样例如是可能的,连接导体4在其第二分段42处以同样的方式替代与上金属化层21地与构件1的第一电极11相连接。
同样如图2所示,第一连接块5(两个示出的连接块5中的左边的)通过第一连接导体4以所阐述的方式电导通至控制输入端13,其仅示例性地如前所述地在上金属化层21的分段213和键合线3之上实现,而第二连接块5(两个示出的连接块5中的右边的)通过第一连接导体4、同样以所阐述的方式电导通至构件1的负载连接端,其在半导体模块100的运行过程中具有用于控制的参考电势。如前所述,该负载连接端能够为第一负载连接端11。其导电地并且仅示例性地通过键合线3与上金属化层21的分段212相连接,在其上也固定有第二连接导体4的第二分段42。第二连接块5能够例如为用于构件1的控制的辅助连接端、例如辅助发射极连接端。
为了制造半导体模块100,能够预制具有连接块5和连接导体4的单元,该连接导体4如参照图1所示地在其第一分段处与连接块5固定地并且导电地相连接。
此外,电路载体2能够可选地预装配有一个或多个电子构件1并且然后与壳体6或者壳体框架61或者壳体侧壁相连接。接着,具有连接块5和与其相连接的连接导体5的预制的单元与在电路载体2上实现的电路导电地连接,例如通过连接导体4在其第二分段42处如所述地钎焊、焊接或者导电粘结至上金属化层21或者第一电极11。
为了实现连接导体4的第二分段42在其与电路相连接之前就位于正确的位置,具有连接导体4和连接块5的单元能够如此地固定在壳体6或者壳体部分(例如壳体框架61或者壳体侧壁)处,使得连接导体4的第二分段42在将装配的电路载体2安装在壳体6或者壳体部分时达到正确的目标位置,从而仅需要制造在第二分段和电路之间的连接,而无需实现第二分段42相对于电路(即相对于预定的固定位置)的另外的定位。
具有连接导体4和连接块5的单元的在壳体6或者壳体部分处的固定能够由此实现,即单元被插入(例如夹在)预制的壳体6或者预制的壳体部分的支架60中或者正好在制造壳体6或壳体部分时(通过注塑)被注入其中,使得壳体6或壳体部分具有集成的支架60。借助于相应数量的支架60,壳体6或壳体部分能够装配有两个或者多个单元,其中每个具有连接块5和与其连接的连接导体4。
为了在两个或者更多这种单元的情况下,实现低电感的导体引导,多个单元的多个连接导体4的两个分段能够通过路线40彼此并行地走向,如例如在图1中所示,其示出了在装置中的两个这样的单元,其中该装置也位于完成的半导体模块100中,以及在图2和接下来的附图中。路线40具有至少30mm的长度L40,例如大约33mm。在此,该长度L40沿着并行走向的分段的延伸方向并且居中地位于其间地来确定。并行走向的分段能够直线地和/或弯曲地延伸。只要存在弯曲,长度L40也沿着弯曲地来确定。在路线40的范围中,并行走向的分段具有被选择为小于或者等于5mm、小于或者等于1mm或者仅小于或者等于0.5mm的间距d40。通过所阐述的分段式的并行引导,设置在两个单元的连接块5之间的用于控制构件1的控制电压能够低电感地并且以小的易受干扰性地供给构件1。
在一个或两个单元中,其中连接导体4的两个分段并行地引导,相应的连接导体4能够在其连接块5处具有背对相同的单元的分段45,其连接至线路分段40。至该分段45,其他单元的连接导体4不具有与此并行引导的分段,从而产生提高的电感。因此这是有利的,尽可能短地保持分段45。因此,例如分段45的每个位置不以至上侧20t的并行方向地、比间距L45远地从线路分段40离开。间距L45能够被选择为例如小于37mm,或者仅小于2mm。
根据另外的方面,这有利地用于实现连接导体4的低电感的引导,当其具有与上侧20t并行延伸的分段时,其能够例如具有至少30mm的长度,并且其与上金属化层21的间距h4小于或者等于9mm。该准则不仅适用于单个单元的连接导体4,也尤其适用于具有用于每个并行引导的分段的连接导体4的并行引导的分段的两个单元的连接导体4的情况。
图3示出了已在图1中示出的多个单元的不同的视图,同样地在装置中,其中该些单元也能够位于完成的半导体模块100中。
相应地,图4A、4B和4C示出了具有侧壁61的模块壳体6的下部的同样的分段的总览的顶视图、侧视图或透视图,在该侧壁处两个根据图1和图3阐述的单元借助于支架60如前所述地进行固定。
虽然连接块6的螺纹50在给定的实施例中被构造为内螺纹,然而其也能够被构造为外螺纹。对此的示例根据在图5中示出的半导体模块100示出,其结构此外对应于根据图2的半导体模块100。能够理解,在半导体模块100中也能够使用至少一个连接块5,其螺纹50被构造为内螺纹,以及至少一个另外的连接块5,其螺纹50被构造为外螺纹。
当连接块5和连接导体4具有良好的导电性能时,这在本发明中是基本上有利的。例如连接块5能够例如由铜合金组成或者具有至少90%比重的铜的组分。同样地,连接块5能够有其他材料组成或者具有其它材料。合适的材料的示例是无铅的黄铜(例如CuZn39Pb3)、加工黄铜、不锈钢(例如根据DIN EN 10088-3 X8CrNiS18-9)、钢(也能够是表面镀镍的)或者青铜(例如CuSn6或者CuPb1P)。连接导体4能够由金属、例如由铜或者铜合金组成和/或具有至少90%比重的铜的组分。
在本发明的所有变型中,螺纹的螺纹轴a能够可选地垂直于绝缘载体20的上侧20t地延伸。
图6还示出了两个半导体模块100的总览图,电路板200被施加在其上并且在每个半导体模块100中在多个连接块5中使用连接螺钉205——其分别与连接块的内螺纹进行螺纹连接——与所涉及的半导体模块100机械地并且电地相连接。以相应的方式,自然也能够仅有单个的半导体模块100与电路板200相连接。在所示的多个半导体模块100中,螺纹5被分别构造为内螺纹。然而,在半导体模块100中、在一个、多个或者所有的连接块5处,螺纹50也能够基本上被构造为外螺纹。只要电路板200与连接块5螺纹连接,其螺纹50为外螺纹,则替代连接螺钉50而使用螺母,其与外螺纹进行螺纹连接。
替代与电路板200地,半导体模块100能够以相似的方式与金属的总线导轨、与扁平带导体或者与连接孔进行螺纹连接并且由此电导通。
Claims (10)
1.一种用于制造功率半导体模块的方法,其中,所述方法具有以下步骤:
以所述半导体构件(1)装配电路载体(2),所述电路载体具有介电的绝缘载体(20)以及上金属化层(21),所述上金属化层被施加在所述介电的绝缘载体(20)的上侧(20t)上;
在具有螺纹(50)的导电连接块(5)与连接导体(4)的第一分段(41)之间制造固定的并且导电的连接;
在所述电路载体(2)或所述半导体构件(1)与所述连接导体(4)的第二分段(42)之间制造材料连接的和导电的连接;
将所述连接块(5)和以所述半导体构件(1)装配的所述电路载体(2)如此设置在所述模块壳体(6)处,使得所述半导体构件(1)被设置在所述模块壳体(6)中并且所述螺纹(50)从所述模块壳体(6)的外侧是可达到的,其中
具有所述连接导体(4)和所述连接块(5)的单元能够如此地固定在所述模块壳体(6)或者壳体部分处,使得所述第二分段(42)在将预装配的所述电路载体(2)安装在所述模块壳体(6)或者所述模块壳体部分时达到正确的目标位置,从而仅需要制造在所述第二分段(42)和在其上实现所述电路载体(2)的电路之间的连接,而无需实现所述第二分段(42)相对于电路的另外的定位;并且其中,所述功率半导体模块还具有:
另外的导电的连接块(5),所述另外的导电的连接块(5)具有另外的螺纹,并且所述另外的螺纹(50)从所述模块壳体(6)的外侧是可达到的;以及
另外的连接导体(4),所述另外的连接导体具有另外的第一分段(41),在所述另外的第一分段处所述另外的连接导体(4)在另外的第一连接位置处与所述另外的连接块(5)固定且导电地相连接,所述另外的连接导体还具有另外的第二分段(42),在所述另外的第二分段处所述另外的连接导体(4)在另外的第二连接位置处与所述电路载体(2)和/或与所述半导体构件(1)材料连接地和导电地相连接;并且其中,所述连接导体(4)和所述另外的连接导体(4)在至少30mm的长度(L40)上并行引导,并且在所述连接导体(4)和所述另外的连接导体(4)并行引导的区域中具有最高5mm的间距,其中通过注塑来制造并且在此借助于支架(60)来设置所述模块壳体(6)或者所述模块壳体(6)的一部分(61),所述连接导体(4)在制造所述模块壳体(6)或者所述模块壳体(6)的一部分(61)之后被插入所述支架中。
2.根据权利要求1所述的方法,其中,通过借由注塑来制造所述模块壳体(6)以及在此将所述连接导体(4)注入所述模块壳体(6)中,来实现提供所述连接导体(4)和提供所述模块壳体(6)。
3.根据权利要求1或2所述的方法,其中,所述连接导体(4)在所述第一连接位置处钎焊、超声波焊接、激光焊接或者铆接至所述连接块(5)。
4.根据权利要求1或2所述的方法,其中,所述连接导体(4)在所述第二连接位置处钎焊、烧结、激光焊接、超声波焊接或者导电粘结至所述电路载体(2)或者所述半导体构件(1)。
5.根据权利要求1或2所述的方法,其中,所述连接导体(4)以分段方式注入或者插入所述模块壳体(6)或所述模块壳体(6)的一部分之中,并且因此与所述模块壳体(6)或者所述模块壳体(6)的所述一部分固定地连接。
6.根据权利要求1或2所述的方法,其中,所述绝缘载体(20)具有陶瓷。
7.根据权利要求1或2所述的方法,其中,所述螺纹为内螺纹或者外螺纹。
8.根据权利要求1或2所述的方法,其中,所述螺纹具有螺纹轴,所述螺纹轴垂直于所述上侧(20t)地延伸。
9.根据权利要求1或2所述的方法,其中,所述连接块(5)是一体成型的。
10.根据权利要求1或2所述的方法,其中,所述连接块(5)由统一的材料或者同类的材料组合物组成。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102014115847.4 | 2014-10-30 | ||
DE102014115847.4A DE102014115847B4 (de) | 2014-10-30 | 2014-10-30 | Verfahren zur Herstellung eines Leistungshalbleitermoduls |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105609477A CN105609477A (zh) | 2016-05-25 |
CN105609477B true CN105609477B (zh) | 2019-10-11 |
Family
ID=55753578
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510564791.5A Active CN105609477B (zh) | 2014-10-30 | 2015-09-07 | 用于制造功率半导体模块的方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US10020237B2 (zh) |
CN (1) | CN105609477B (zh) |
DE (1) | DE102014115847B4 (zh) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6515886B2 (ja) * | 2016-07-08 | 2019-05-22 | 株式会社豊田自動織機 | 半導体モジュール |
EP3555914B1 (en) * | 2016-12-16 | 2021-02-03 | ABB Schweiz AG | Power semiconductor module with low gate path inductance |
US10212838B2 (en) | 2017-01-13 | 2019-02-19 | Cree Fayetteville, Inc. | High power multilayer module having low inductance and fast switching for paralleling power devices |
US11696417B2 (en) | 2017-01-13 | 2023-07-04 | Wolfspeed, Inc. | High power multilayer module having low inductance and fast switching for paralleling power devices |
US10917992B2 (en) | 2017-01-13 | 2021-02-09 | Cree Fayetteville, Inc. | High power multilayer module having low inductance and fast switching for paralleling power devices |
US10749443B2 (en) | 2017-01-13 | 2020-08-18 | Cree Fayetteville, Inc. | High power multilayer module having low inductance and fast switching for paralleling power devices |
USD954667S1 (en) | 2017-01-13 | 2022-06-14 | Wolfspeed, Inc. | Power module |
JP6760127B2 (ja) | 2017-02-24 | 2020-09-23 | 三菱電機株式会社 | 半導体装置、半導体装置の製造方法 |
USD903590S1 (en) | 2018-09-12 | 2020-12-01 | Cree Fayetteville, Inc. | Power module |
DE102019206263B4 (de) * | 2019-05-02 | 2022-06-30 | Abb Schweiz Ag | Halbleiterbauteil, Kraftfahrzeug und Verfahren zur Herstellung eines Halbleiterbauteils |
EP3736858A1 (en) | 2019-05-06 | 2020-11-11 | Infineon Technologies AG | Power semiconductor module arrangement |
EP3736855A1 (en) | 2019-05-06 | 2020-11-11 | Infineon Technologies AG | Power semiconductor module arrangement and method for producing the same |
EP3736854A1 (en) * | 2019-05-06 | 2020-11-11 | Infineon Technologies AG | Power semiconductor module arrangement |
JP7346178B2 (ja) * | 2019-09-05 | 2023-09-19 | 株式会社東芝 | 半導体装置 |
USD942403S1 (en) | 2019-10-24 | 2022-02-01 | Wolfspeed, Inc. | Power module having pin fins |
DE102020111573B4 (de) | 2020-04-28 | 2023-09-14 | Semikron Elektronik Gmbh & Co. Kg | Leistungselektronische Anordnung mit Gleichspannungsverbindungselement und Verfahren zur Herstellung |
JP7353233B2 (ja) * | 2020-05-14 | 2023-09-29 | 三菱電機株式会社 | 半導体装置 |
EP4220704A1 (en) * | 2022-01-27 | 2023-08-02 | Infineon Technologies AG | Printed circuit board, power semiconductor module arrangement comprising a printed circuit board, and method for assembling the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5825085A (en) * | 1995-09-01 | 1998-10-20 | Mitsubishi Denki Kabushiki Kaisha | Power semiconductor device, armoring case thereof and method for manufacturing the same |
US5920119A (en) * | 1996-02-22 | 1999-07-06 | Hitachi, Ltd. | Power semiconductor module employing metal based molded case and screw fastening type terminals for high reliability |
US6060772A (en) * | 1997-06-30 | 2000-05-09 | Kabushiki Kaisha Toshiba | Power semiconductor module with a plurality of semiconductor chips |
US6521983B1 (en) * | 2000-08-29 | 2003-02-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device for electric power |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007235004A (ja) | 2006-03-03 | 2007-09-13 | Mitsubishi Electric Corp | 半導体装置 |
JP5295933B2 (ja) | 2009-11-17 | 2013-09-18 | 日本インター株式会社 | パワー半導体モジュール |
JP5211364B2 (ja) | 2010-05-07 | 2013-06-12 | 三菱電機株式会社 | 半導体装置 |
JP2012134300A (ja) | 2010-12-21 | 2012-07-12 | Mitsubishi Electric Corp | 半導体装置 |
JP5555206B2 (ja) | 2011-07-11 | 2014-07-23 | 株式会社 日立パワーデバイス | 半導体パワーモジュール |
-
2014
- 2014-10-30 DE DE102014115847.4A patent/DE102014115847B4/de active Active
-
2015
- 2015-09-07 CN CN201510564791.5A patent/CN105609477B/zh active Active
- 2015-10-28 US US14/925,274 patent/US10020237B2/en active Active
-
2017
- 2017-02-06 US US15/424,995 patent/US10008392B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5825085A (en) * | 1995-09-01 | 1998-10-20 | Mitsubishi Denki Kabushiki Kaisha | Power semiconductor device, armoring case thereof and method for manufacturing the same |
US5920119A (en) * | 1996-02-22 | 1999-07-06 | Hitachi, Ltd. | Power semiconductor module employing metal based molded case and screw fastening type terminals for high reliability |
US6060772A (en) * | 1997-06-30 | 2000-05-09 | Kabushiki Kaisha Toshiba | Power semiconductor module with a plurality of semiconductor chips |
US6521983B1 (en) * | 2000-08-29 | 2003-02-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device for electric power |
Also Published As
Publication number | Publication date |
---|---|
US10020237B2 (en) | 2018-07-10 |
US10008392B2 (en) | 2018-06-26 |
US20160126154A1 (en) | 2016-05-05 |
DE102014115847B4 (de) | 2018-03-08 |
DE102014115847A1 (de) | 2016-05-04 |
CN105609477A (zh) | 2016-05-25 |
US20170148644A1 (en) | 2017-05-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105609477B (zh) | 用于制造功率半导体模块的方法 | |
US6476481B2 (en) | High current capacity semiconductor device package and lead frame with large area connection posts and modified outline | |
US7615854B2 (en) | Semiconductor package that includes stacked semiconductor die | |
US11239132B2 (en) | Semiconductor power device with corresponding package and related manufacturing process | |
US10070528B2 (en) | Semiconductor device wiring pattern and connections | |
US9202765B2 (en) | Semiconductor device | |
US9129931B2 (en) | Power semiconductor module and power unit device | |
US11596077B2 (en) | Method for producing a semiconductor module arrangement | |
US8040707B2 (en) | Power converter | |
US20230121335A1 (en) | Power Module with Press-Fit Contacts | |
US9754862B2 (en) | Compound semiconductor device including a multilevel carrier | |
US11244922B2 (en) | Semiconductor device | |
US9373566B2 (en) | High power electronic component with multiple leadframes | |
US11315850B2 (en) | Semiconductor device | |
CN111354709B (zh) | 半导体装置及其制造方法 | |
US11728250B2 (en) | Semiconductor package with connection lug | |
CN115117011A (zh) | 功率半导体模块和生产功率半导体模块的方法 | |
EP2178117A1 (en) | Power semiconductor module with double side cooling | |
US20230170286A1 (en) | Terminal Element or Bus Bar, and Power Semiconductor Module Arrangement Comprising a Terminal Element or Bus Bar | |
US20240079297A1 (en) | Semiconductor Package with Balanced Impedance | |
US20230197584A1 (en) | Mounting structure for semiconductor module | |
US12125772B2 (en) | Method of forming a semiconductor package with connection lug | |
CN116438648A (zh) | 半导体装置 | |
CN119110995A (zh) | 半导体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |