CN105575880A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN105575880A CN105575880A CN201410528396.7A CN201410528396A CN105575880A CN 105575880 A CN105575880 A CN 105575880A CN 201410528396 A CN201410528396 A CN 201410528396A CN 105575880 A CN105575880 A CN 105575880A
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Abstract
The invention provides a semiconductor device manufacturing method comprising the following steps: providing a wafer, wherein the wafer includes a semiconductor substrate, a device disposed on the semiconductor substrate, and an interlayer dielectric layer formed on the semiconductor substrate and covering the device; forming a negative photoresist layer on the interlayer dielectric layer; pre-exposing the negative photoresist layer in an ugly die area at the edge of the wafer; exposing and developing the remaining unexposed negative photoresist layer to form a patterned negative photoresist layer; etching the interlayer dielectric layer with the patterned negative photoresist layer as a mask to form an opening exposing the semiconductor substrate; etching part of the semiconductor substrate exposed by the opening to form a through-silicon via; and removing the negative photoresist layer. According to the manufacturing method of the invention, formation of a through-silicon via pattern in the ugly die area at the edge of the wafer is avoided, the root causes of the stripping problem at the edge of the wafer are reduced, the risk that copper pollutes an Al process machine is reduced greatly, and the reliability and yield of products are improved.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to the manufacture method in particular to a kind of semiconductor device.
Background technology
Silicon through hole (ThroughSiliconVia is called for short TSV) technology is one of key technology of 3D packaging technology.TSV is by making vertical conducting between chip and chip, between wafer and wafer, realizes the state-of-the-art technology interconnected between chip.Encapsulate bonding from IC in the past and use the superimposing technique of salient point different, TSV can make chip maximum in the density that three-dimensional is stacking, and overall dimension is minimum, and greatly improves the performance of chip speed and low-power consumption.
Stage residing for TSV manufacture craft is different, can be divided into: front through hole (via-first), middle through hole (via-middle) and rear through hole (via-last) three kinds of technological processes, wherein, via-first produces TSV manufacturing etching on the bare silicon wafer before CMOS; Via-middle is that on wafer, etching produces TSV after manufacture CMOS but before back-end process (BEOL), and via-last is after back-end process, produces TSV at the back-etching of thinned wafer.
Under normal circumstances, via-middle technique needs after contact hole CT etching, filling, mechanical lapping, carry out TSV etching, Cu plating filling, mechanical lapping, metal line layer M1 deposition and back-end process.The method introduced TSV processing procedure before metal line layer M1 deposits, and can realize better merging with various technique in Fab, be a kind of method that current industry is commonly used the most.
Current TSV lithographic process uses positive photoresistance, so the invalid chip (uglydie) of crystal round fringes also can expose the pattern of TSV, and after the copper metal plating filling process of TSV, and can by the Cu H of crystal round fringes 2mm
2sO
4wash off, the TSV within final crystal round fringes 2mm width can become hollow bore (hollowTSV), as shown in Figure 1A.But said process will cause following two kinds of serious hidden danger:
1) due to H
2sO
4cu can only be removed, the root that the impurity that comes off after the Ta/TaN barrier layer stayed and SA-TEOS dielectric layer will become produces, as shown in Figure 1B;
2) if Cu side washing is insufficient, as shown in Figure 1 C, the Cu filled in the TSV through hole of crystal round fringes does not wash off completely, after metal line layer M1 etches, Cu will be stripped out, and not only produces serious defect, also can pollute the board of Al line simultaneously, cause serious loss.
Therefore, the removal of the TSV pattern of chip region invalid in crystal round fringes 2mm is become a problem demanding prompt solution.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to overcome current Problems existing, the invention provides a kind of manufacture method of semiconductor device, comprising:
There is provided wafer, described wafer comprises Semiconductor substrate and is positioned at the device in described Semiconductor substrate, and is formed at the interlayer dielectric layer described Semiconductor substrate covering described device;
Described interlayer dielectric layer forms negative photoresist layer;
Pre-exposure is carried out to the described negative photoresist layer of the invalid chip area of described crystal round fringes;
Remaining unexposed described negative photoresist layer is exposed and developed, to form the negative photoresist layer of patterning, meanwhile, the described negative photoresist layer in the invalid chip area of described crystal round fringes can not form pattern;
With the negative photoresist layer of described patterning for mask, etch described interlayer dielectric layer, form opening and expose described Semiconductor substrate;
The described Semiconductor substrate of the part exposed in described opening is etched, to form silicon through hole;
Remove described negative photoresist layer.
Further, the width range of the invalid chip area of described crystal round fringes is 0.5 ~ 4mm.
Further, the thickness range of described negative photoresist layer is 30000 ~ 60000 dusts.
Further, described negative photoresist layer is the resinoid organic solvent of compound and thermoprene containing having photobehavior.
Further, between described interlayer dielectric layer and described negative photoresist layer, also hard mask layer is formed with.
Further, in described interlayer dielectric layer, be also formed with the contact embolism be electrically connected with described device.
Further, described manufacture method is applicable to the making of silicon through hole, is also applicable to the making of interconnection structure and via layer.
In sum, according to manufacture method of the present invention, adopt the method for negative photoresistance and crystal round fringes pre-exposure, avoid forming silicon through-hole pattern at the invalid chip area of crystal round fringes, the root that the stripping problem not only reducing crystal round fringes produces, also greatly reduce the risk of Cu-W ore deposit Al process work bench, and then improve reliability and the yield of product.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
The schematic diagram of the hollow TSV that Figure 1A is formed after showing crystal round fringes side washing;
Figure 1B shows the schematic diagram that Ta/TaN barrier layer and SA-TEOS dielectric layer come off;
Fig. 1 C show Cu side washing insufficient time silicon through hole in the schematic diagram of residual copper;
Fig. 2 A-2D shows the cutaway view of the device that each step obtains in the technical process of existing a kind of TSV photoetching/etching;
Fig. 3 shows the process chart making TSV according to one embodiment of the present invention;
Fig. 4 A-4F shows the cutaway view of the device that one embodiment of the present invention obtains to each step in the technical process making TSV;
Fig. 5 shows the common W embolism of D18/D16 technology and peels off defect schematic diagram;
Fig. 6 shows the schematic diagram that defect generation peeled off by W embolism.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can be used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms be only used for differentiation element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of the element of shown in description figure or feature and other element or feature for convenience of description.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprises the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be comprised.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the technical scheme of the present invention's proposition.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Below, with reference to figure 2A-2D, the technical process of existing a kind of TSV photoetching/etching is described further.
First, as shown in Figure 2 A, provide wafer, described wafer comprises Semiconductor substrate 200 and is formed at the device 201 in Semiconductor substrate, and to be formed in described Semiconductor substrate 200 and to cover the interlayer dielectric layer 202 of described device 201.Described interlayer dielectric layer 202 is also formed with silicon nitride layer 203.
Described silicon nitride layer 203 is formed the photoresist layer 204 of patterning, and described photoresist layer 204 is positive photoresistance.Particularly, spin coating photoresist layer above silicon nitride layer, carries out exposure imaging to form the photoresist layer 204 with TSV through hole pattern to described photoresist layer.Wherein, also expose TSV pattern at the invalid chip area of crystal round fringes.
As shown in Fig. 2 B-2C, with the photoresist layer 204 of patterning for mask, etch silicon nitride layer 203, interlayer dielectric layer 202 and part semiconductor substrate 200 successively, to form silicon through hole 205a and 205b, wherein silicon through hole 205b is positioned at the invalid chip area of crystal round fringes.
As shown in Figure 2 D, the photoresist layer of patterning is removed.
But adopting above-mentioned technique, the invalid chip area of crystal round fringes (the maximum side washing of other photoresist layers, as 2mm) also can expose the pattern of TSV.And after the copper metal plating filling process of TSV, can by the Cu H of crystal round fringes 2mm width
2sO
4wash off, the TSV within final crystal round fringes 2mm width can become hollow bore (hollowTSV), but said process will cause following two kinds of serious hidden danger:
1) due to H
2sO
4cu can only be removed, the Ta/TaN barrier layer stayed and SA-TEOS dielectric layer will become the root that the impurity that comes off produces;
2) if Cu side washing is insufficient, the Cu filled in the TSV through hole of crystal round fringes does not wash off completely, and after metal line layer M1 etches, Cu will be stripped out, and not only produces serious defect, also can pollute the board of Al line simultaneously, causes serious loss.
Existence in view of the above problems, the present invention proposes a kind of new manufacture method, to avoid the pattern exposing TSV at the invalid chip area of crystal round fringes.
[exemplary embodiment]
Below in conjunction with Fig. 3 and Fig. 4 A-4F, the manufacture method of semiconductor device of the present invention is described in detail.
Wherein, Fig. 3 shows the process chart making TSV according to one embodiment of the present invention; Fig. 4 A-4F shows the cutaway view of the device that one embodiment of the present invention obtains to each step in the technical process making TSV.
Perform step 301, provide wafer, described wafer comprises Semiconductor substrate and is positioned at the device in Semiconductor substrate, and is formed at the interlayer dielectric layer described Semiconductor substrate covering described device.
As shown in Figure 4 A, described Semiconductor substrate 400 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Semiconductor substrate 400 can be defined active area.
Described device 401 can comprise multiple independent circuit element, such as: transistor, diode, resistor, capacitor, inductor etc.; Also can be other the active and passive semiconductor devices formed by multiple ic manufacturing process.Be described for transistor for described device 401 in Fig. 4 A, it does not limit the scope of the invention at this.
Described interlayer dielectric layer 402 is formed in Semiconductor substrate 400, covers described device 401, isolates with the interconnection structure of follow-up formation to make device 401.Described interlayer dielectric layer 402 can be single or multiple lift structure, it can be silicon oxide layer particularly, comprise the material layer having doping or unadulterated silica utilizing thermal chemical vapor deposition (thermalCVD) manufacturing process or high-density plasma (HDP) manufacturing process to be formed, the silex glass (USG) of such as undoped, phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer also can be the tetraethoxysilane (BTEOS) of spin cloth of coating-type glass (spin-on-glass, SOG) of doped with boron or Doping Phosphorus, the tetraethoxysilane (PTEOS) of Doping Phosphorus or doped with boron.
The contact embolism 403 be electrically connected with described device 401 is also formed in described interlayer dielectric layer 402.The material of described contact embolism 403 can comprise tungsten, copper etc., and it is for interface unit and interconnection structure.The concrete formation method of described contact embolism 403 is known for those skilled in the art, does not repeat them here.
Further, described interlayer dielectric layer 402 is also formed with hard mask layer 404, to protect interlayer dielectric layer 402.Exemplarily, described hard mask layer 404 is nitride layer, such as silicon nitride.
Wherein corresponding outside phantom line segments in Fig. 4 A region is the invalid chip area 40 of crystal round fringes, and exemplarily, the width range of the invalid chip area 40 of described crystal round fringes is 0.5 ~ 4mm, is preferably 2mm.But do not limit to and have above-mentioned width range, also can have certain change according to the not equal actual conditions of wafer size.
Perform step 302, described hard mask layer forms negative photoresist layer.
Continue with reference to figure 4A, exemplarily, described hard mask layer 404 applies one deck negative photoresist layer 405.Any method well known to those skilled in the art can be adopted to carry out the coating of negative photoresist layer 405, and such as spin coating or curtain apply.Alternatively, the thickness range of described negative photoresist layer is from about 30000 to about 60000 dusts.Negative photoresistance is the resinoid organic solvent of compound and thermoprene containing having photobehavior, and general photosensitive compound is diaryl azide.
Also can comprise the step of soft baking (SoftBaking) afterwards further, to remove solvent, strengthen the adhesion of negative photoresist layer 405, the stress in release negative photoresist layer, prevents photoresistance contaminated equipment.
Perform step 303, pre-exposure is carried out to the negative photoresist layer of the invalid chip area of crystal round fringes.
Before carrying out pre-exposure, also comprise the step of carrying out aiming at, any applicable method can be adopted to aim at, and therefore not to repeat here.
With reference to figure 4B, expose, utilize reticle make segment beam through, be irradiated on the negative photoresist layer 405 of the invalid chip area 40 of crystal round fringes, react with negative photoresist layer 405, thus the negative photoresist layer 405 realizing the invalid chip area 40 of crystal round fringes carries out pre-exposure.
Alternatively, the step of rear baking (PostExposureBake, PEB) can also be carried out after exposure, to reduce standing wave effect.In one example, hotplate methodology is adopted to carry out the step of rear baking.Alternatively, the temperature of rear baking is 105 ~ 115 DEG C, and the time is 60 seconds.
Perform step 304, remaining unexposed negative photoresist layer is exposed and developed, to form the negative photoresist layer of patterning.
With reference to figure 4C, utilize reticle make segment beam through, be irradiated on unexposed negative photoresist layer 405, react with negative photoresist layer 405, thus the negative photoresist layer 405 be not exposed is exposed.
Negative photoresist layer 405 after exposure is developed, developer solution is sprayed onto the surface of negative photoresist layer 405.When photoresistance is for negative photoresistance, toluene or dimethylbenzene can be selected as developer solution.Negative photoresistance irradiates through light and produces reaction of building bridge, and through overlapping, sclerosis, exposed portion and unexposed portion produce the difference of solubility, utilize developer solution to be dissolved at unexposed position and remove, carry out the video picture of pattern, form the negative photoresist layer 405 with silicon through-hole pattern.
Due in step 303, pre-exposure has been carried out to the negative photoresist layer 405 of the invalid chip area 40 of crystal round fringes, and use negative photoresist layer 405 due to the present invention, what negative photoresist layer 405 was developed dissolving is unexposed region, and all exposed at the negative photoresist layer 405 of the invalid chip area 40 of crystal round fringes, there is not unexposed negative photoresist layer 405, therefore, in the exposure of this step and developing process, the negative photoresist layer in the invalid chip area 40 of crystal round fringes can not form silicon through-hole pattern.
Also can comprise further afterwards and hard step of drying is carried out to negative photoresist layer 405.Hard baking can remove solvent unnecessary in negative photoresist layer, strengthens the adhesive force between negative photoresist layer and substrate, improves the corrosion stability of negative photoresist layer 405 in etching process afterwards and protective capability simultaneously.
Perform step 305, with the negative photoresist layer of described patterning for mask, etch described hard mask layer and interlayer dielectric layer successively, form opening and expose described Semiconductor substrate.
With reference to figure 4D, with the described negative photoresist layer 405 with silicon through-hole pattern for mask, etch described mask layer 404 and interlayer dielectric layer 402 successively, form opening 406a and expose described Semiconductor substrate 400.Dry etching or wet etching can be selected to etch described mask layer 404 and interlayer dielectric layer 402.Dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Dry etching is carried out preferably by one or more RIE step.It should be noted that, described through-silicon via structure does not destroy existing device 401 and contacts embolism 403, namely described through-silicon via structure is arranged in and does not comprise device 401 and the interlayer dielectric layer 402 contacting embolism 403, therefore the etching needle of this step is to not comprising device 401 and the interlayer dielectric layer 402 contacting embolism 403.
Perform step 306, the described Semiconductor substrate of the part exposed is etched, to form silicon through hole in described opening.
As shown in Figure 4 E, the described Semiconductor substrate 400 of the part exposed in described opening 406a is etched, to form silicon through hole 406.In a specific embodiment of the present invention, can adopt the etch process of dry etching execution to Semiconductor substrate, dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Such as using plasma etching, etching gas can adopt based on oxygen (O
2-based) gas.Concrete, adopt lower radio-frequency (RF) energy also can produce low pressure and highdensity plasma gas to realize dry etching.As an example, using plasma etching technics, the etching gas of employing is based on oxygen (O
2-based) gas, the range of flow of etching gas can be 50 cc/min (sccm) ~ 150 cc/min (sccm), and reative cell internal pressure can be 5 millitorrs (mTorr) ~ 20 millitorr (mTorr).Wherein, the etching gas of dry etching can also be bromize hydrogen gas, carbon tetrafluoride gas or gas of nitrogen trifluoride.It should be noted that above-mentioned engraving method is only exemplary, be not limited to the method, those skilled in the art can also select other conventional methods.
Only etch part semiconductor substrate 400, final formation runs through the silicon through hole 406 of interlayer dielectric layer 402 and part semiconductor substrate 400.
Perform step 307, with reference to figure 4F, remove negative photoresist layer.Any method well known to those skilled in the art can be adopted to remove negative photoresist layer, the method etc. of such as ashing.
So far complete the chemical etching step to silicon through hole, the plating can also carrying out copper metal is afterwards filled, and the techniques such as mechanical lapping, to form final through-silicon via structure, do not repeat them here.
In another aspect of this invention, manufacture method of the present invention, is not only applicable to the manufacture craft of silicon through hole, can also be applied to interconnection structure and via layer, to solve the generation that crystal round fringes tungsten plug peels off defect, and then promotes yield.
Particularly, be illustrated in figure 5 the common W embolism of D18/D16 technology and peel off defect.Be illustrated in figure 6 the principle that defect generation peeled off by W embolism.
Owing to first can apply photoresist layer on interlayer dielectric layer in the process of every layer of metal level formation of interconnection structure, recycling EBR and WEE, removes the photoresistance of crystal round fringes, then carries out the etching of metal level groove.Exemplarily, as shown in Figure 6, when forming the first metal layer 601 or intermediate metal layer 602, utilize EBR and WEE, removal crystal round fringes is about the photoresistance in 2.8mm width range; When forming top layer metallic layer 603, removal crystal round fringes is about the photoresistance in 1mm width range.After the photoresistance removal of crystal round fringes, the interconnection structure/through hole of crystal round fringes can come out, and will produce the problem that W embolism is peeled off, cause metal crossover, finally cause the reduction of yield after the etch process of metal level groove.And utilize manufacture method of the present invention to can be good at solving the problem.
In sum, according to manufacture method of the present invention, adopt the method for negative photoresistance and crystal round fringes pre-exposure, avoid forming silicon through-hole pattern at the invalid chip area of crystal round fringes, the root that the stripping problem not only reducing crystal round fringes produces, also greatly reduce the risk of Cu-W ore deposit Al process work bench, and then improve reliability and the yield of product.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (7)
1. a manufacture method for semiconductor device, comprising:
There is provided wafer, described wafer comprises Semiconductor substrate and is positioned at the device in described Semiconductor substrate, and is formed at the interlayer dielectric layer described Semiconductor substrate covering described device;
Described interlayer dielectric layer forms negative photoresist layer;
Pre-exposure is carried out to the described negative photoresist layer of the invalid chip area of described crystal round fringes;
Remaining unexposed described negative photoresist layer is exposed and developed, to form the negative photoresist layer of patterning, meanwhile, the described negative photoresist layer in the invalid chip area of described crystal round fringes can not form pattern;
With the negative photoresist layer of described patterning for mask, etch described interlayer dielectric layer, form opening and expose described Semiconductor substrate;
The described Semiconductor substrate of the part exposed in described opening is etched, to form silicon through hole;
Remove described negative photoresist layer.
2. manufacture method according to claim 1, is characterized in that, the width range of the invalid chip area of described crystal round fringes is 0.5 ~ 4mm.
3. manufacture method according to claim 1, is characterized in that, the thickness range of described negative photoresist layer is 30000 ~ 60000 dusts.
4. manufacture method according to claim 1, is characterized in that, described negative photoresist layer is the resinoid organic solvent of compound and thermoprene containing having photobehavior.
5. manufacture method according to claim 1, is characterized in that, between described interlayer dielectric layer and described negative photoresist layer, be also formed with hard mask layer.
6. manufacture method according to claim 1, is characterized in that, is also formed with the contact embolism be electrically connected with described device in described interlayer dielectric layer.
7. manufacture method according to claim 1, is characterized in that, described manufacture method is applicable to the making of silicon through hole, is also applicable to the making of interconnection structure and via layer.
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