CN119626901A - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN119626901A CN119626901A CN202411300702.1A CN202411300702A CN119626901A CN 119626901 A CN119626901 A CN 119626901A CN 202411300702 A CN202411300702 A CN 202411300702A CN 119626901 A CN119626901 A CN 119626901A
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Abstract
The embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, forming a dielectric layer on the substrate, forming an initial groove in the dielectric layer, performing at least one etching treatment on the dielectric layer exposed by the initial groove until a target groove with a set depth is formed in the dielectric layer, wherein any one etching treatment comprises the steps of forming a flattening coating with a mask opening on the dielectric layer, wherein the mask opening exposes the initial groove, and removing the dielectric layer exposed by the initial groove along the depth direction by adopting a directional etching process by taking the flattening coating as a mask. By adopting the technical scheme, the electrical property of the semiconductor structure can be improved.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
With the rapid development of semiconductor technology, performance requirements of semiconductor devices are higher and higher, integration level of semiconductor devices is higher and higher, and accordingly, the size of individual devices is smaller and smaller.
In view of the feature of extending the chip area in the longitudinal direction, the deep trench structure is widely used in various semiconductor devices to improve the integration level of the semiconductor devices.
However, the electrical performance of the semiconductor devices currently being formed remains to be improved.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, and improving the electrical performance of the semiconductor structure.
The embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, forming a dielectric layer on the substrate, forming an initial groove in the dielectric layer, performing at least one etching treatment on the dielectric layer exposed by the initial groove until a target groove with a set depth is formed in the dielectric layer, wherein any one etching treatment comprises the steps of forming a flattening coating with a mask opening on the dielectric layer, wherein the mask opening exposes the initial groove, and removing the dielectric layer exposed by the initial groove along the depth direction by adopting a directional etching process by taking the flattening coating as a mask.
Optionally, the directional etching process includes a gas etching process;
And in the process of removing the dielectric layer exposed from the initial groove along the depth direction by adopting the gas etching process, the polymer remained on the side wall of the initial groove is used as an etching barrier layer.
Optionally, the etching gas of the gas etching process comprises C4F8, CHF3, ar and O2, the etching power is 2200 to 2600W, the etching time is 700 to 900s, and the pressure is 200mT to 250mT.
Optionally, the step of forming a planarization coating with a mask opening on the dielectric layer includes:
forming a planarization coating on the dielectric layer, wherein the initial groove is filled with the planarization coating;
forming a first barrier layer with a first opening on the planarization coating, wherein the first opening exposes the top of the planarization coating, and the position of the first opening is opposite to the position of the initial groove;
and removing the planarization coating exposed by the first opening along the side wall of the first barrier layer, and forming the mask opening in the planarization coating.
Optionally, the material of the planarization coating includes at least one of SiON, si3N4, siC, SOC, and TiO 2;
the material of the first barrier layer includes at least one of photoresist and titanium nitride.
Optionally, the method for forming a semiconductor structure further includes:
Forming a protective layer on the planarization coating layer before the step of forming a first barrier layer with a first opening on the planarization coating layer, wherein the first barrier layer is positioned above the protective layer, and the first opening exposes the top of the protective layer;
In the step of removing the planarization coating layer exposed by the first opening along the sidewall of the first barrier layer, the protective layer exposed by the first opening is also removed.
Optionally, the protective layer is formed on the planarization coating using a low temperature oxidation process.
Optionally, a dry etching process is used to remove the protective layer exposed by the first opening and the planarization coating layer located below the protective layer.
Optionally, the material of the protective layer comprises silicon oxide.
Optionally, the any etching process further includes:
And removing the planarization coating on the dielectric layer after removing the dielectric layer exposed by the initial groove along the depth direction by adopting a directional etching process.
Optionally, an ashing process is used to remove the planarizing coating on the dielectric layer.
Optionally, the step of forming an initial trench in the dielectric layer includes:
Forming a second barrier layer with a second opening on the dielectric layer, wherein the second opening exposes the top of the dielectric layer;
And removing the dielectric layer with partial thickness exposed by the second opening along the side wall of the second barrier layer, and forming the initial groove in the dielectric layer.
Optionally, the set depth is greater than 10 microns.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
According to the method for forming the semiconductor structure, the initial groove is formed in the dielectric layer, and the target groove with the set depth can be formed in the dielectric layer by performing at least one etching treatment on the dielectric layer exposed by the initial groove. For any etching treatment, when the planarization coating is used as a mask and a directional etching process is adopted, the dielectric layer exposed out of the initial groove along the depth direction can be removed, the damage to the side wall of the initial groove is reduced, the flatness of the side wall of the target groove is improved, the probability of subsequent generation of holes is reduced or avoided, and therefore the electrical performance of the semiconductor structure can be improved.
Drawings
Fig. 1 to 8 are schematic structural views corresponding to each step of a semiconductor structure.
Detailed Description
The performance of current semiconductor structures is to be improved. This is because an isotropic etching process is employed in forming the deep trench structure. When the dielectric layer is etched in the depth direction, the side wall of the dielectric layer is also etched, so that a ripple effect (scalping) of the side wall of the dielectric layer is caused, and side wall ripples are formed on the side wall of the dielectric layer. At present, the sidewall corrugation can form surface roughness of more than 100nm, so that holes are generated when the deep trench structure is filled later, and the electrical performance of the semiconductor structure is reduced.
The invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, forming a dielectric layer on the substrate, forming an initial groove in the dielectric layer, performing at least one etching treatment on the dielectric layer exposed by the initial groove until a target groove with a set depth is formed in the dielectric layer, wherein any one etching treatment comprises the steps of forming a flattening coating with a mask opening on the dielectric layer, wherein the mask opening exposes the initial groove, and removing the dielectric layer exposed by the initial groove along the depth direction by using the flattening coating as a mask and adopting a directional etching process.
By adopting the scheme, for any etching treatment, when the planarization coating is used as a mask and a directional etching process is adopted, the dielectric layer exposed out of the initial groove along the depth direction can be removed, the damage to the side wall of the initial groove is reduced, the flatness of the side wall of the target groove is improved, the probability of generating holes subsequently is reduced or avoided, and therefore the electrical performance of the semiconductor structure can be improved.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Referring to fig. 1, a substrate 100 is provided, and a dielectric layer 102 is formed on the substrate 100.
In this embodiment, the substrate 100 may provide a process operation basis for the formation process of the semiconductor structure. The semiconductor structure may include, among other things, a Complementary Metal Oxide Semiconductor (CMOS), an Integrated Circuit (IC), a microelectromechanical system (MEMS), any other electronic component, or a combination of electronic components.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
In some embodiments, the substrate may further include a substrate, a plurality of discrete fins located above the substrate, and an isolation structure located on the substrate where the fins are exposed, the isolation structure may cover a portion of a sidewall of the fins, and a top of the isolation structure is lower than a top of the fins.
In this embodiment, the isolation structure serves to electrically isolate adjacent fins.
In some embodiments, the material of the isolation structure may be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.
In this embodiment, the material of the isolation structure may be silicon oxide.
Dielectric layer 102 may provide spatial locations for subsequently formed initial trenches and target trenches.
In this embodiment, a chemical vapor deposition process may be used to form the dielectric layer 102 on the substrate 100.
In this embodiment, the material of the dielectric layer 102 may include a low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less), an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant of less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride, and the like.
In one particular embodiment, the material of the dielectric layer 102 may include silicon oxide.
Referring to fig. 2 and 3, an initial trench 106 is formed within the dielectric layer 102.
The initial trench 106 is used to provide a process window for forming a target trench.
In this embodiment, the step of forming the initial trench 106 in the dielectric layer 102 includes:
referring to fig. 2, a second barrier layer 104 having a second opening K1 is formed on the dielectric layer 102, the second opening K1 exposing the top of the dielectric layer 102.
The second barrier layer 104 may function to protect the dielectric layer 102 from damage to other portions of the dielectric layer 102 during the process of forming the second opening K1.
In this embodiment, the second barrier layer 104 having the second opening K1 is formed by using a photolithography process.
Specifically, a second barrier material layer (not shown) is formed on the dielectric layer 102, a photoresist (not shown) having a pattern opening is formed on the second barrier material layer, and the second barrier material layer is patterned to form a second barrier layer 104.
In this embodiment, chemical vapor deposition (e.g., plasma enhanced PECVD, ion beam deposition IBD, sputtering, etc.) is used to deposit the second barrier material layer.
In this embodiment, the material of the second barrier layer 104 may include at least one of photoresist, silicon nitride, titanium nitride, and titanium oxide.
In one particular embodiment, the material of the second barrier layer 104 includes photoresist. The photoresist may include a positive photoresist or a negative photoresist, and the present invention is not particularly limited herein.
Referring to fig. 3, along the sidewall of the second barrier layer 104, the dielectric layer 102 exposed by the second opening K1 is removed to form an initial trench 106 in the dielectric layer 102, where the initial trench 106 is formed by the bottom of the dielectric layer 102 and the sidewall of the dielectric layer 102.
In this embodiment, the dielectric layer 102 with a partial thickness exposed by the second opening K1 is removed by using a dry etching method.
In this embodiment, the depth of the initial trench 106 is not too large, which would easily affect the formation quality of the target trench, for example, if the depth of the initial trench 106 is too large, the thickness of the removed dielectric layer 102 is thicker, which may damage the sidewall of the dielectric layer 102, which may easily result in poor smoothness of the sidewall of the finally formed target trench, and the depth of the initial trench 106 is not too small, which would result in too long time for forming the target trench. For this reason, in the present embodiment, the depth of the initial trench 106 is 5 micrometers to 8 micrometers.
It should be noted that the second barrier layer 104 is also removed after the initial trench 106 is formed, or the second barrier layer 104 is also consumed during the formation of the initial trench 106 (e.g., when the material of the second barrier layer 104 is photoresist), and the second barrier layer 104 is entirely consumed when the initial trench 106 is formed.
Referring to fig. 4 to 8, at least one etching process is performed on the dielectric layer 102 exposed by the initial trench 106 until a target trench 120 having a set depth is formed in the dielectric layer 102, wherein any one etching process includes forming a planarization coating 108 having a mask opening K2 on the dielectric layer 102, the mask opening K2 exposing the initial trench 106, and removing the dielectric layer 102 exposed by the initial trench 106 in the depth direction by using the planarization coating 108 as a mask and adopting a directional etching process.
According to the embodiment of the invention, the dielectric layer 102 exposed by the initial groove 106 is etched at least once, and in the etching process, the dielectric layer 102 exposed by the initial groove 106 in the depth direction can be removed by adopting a directional etching process, so that the damage to the side wall of the dielectric layer 102 can be reduced, the flatness of the side wall of the target groove can be improved, the probability of generating holes subsequently can be reduced or avoided, and the electrical performance of the semiconductor structure can be improved.
The steps of forming the target trench 120 according to the present embodiment will be described in detail with reference to the accompanying drawings.
Referring to fig. 4 to 6, the step of forming the planarization coating 108 having the mask opening K2 on the dielectric layer 102 includes:
referring to fig. 4, a planarizing coating layer 108 is formed on the dielectric layer 102, the planarizing coating layer 108 filling the initial trench 106.
The planarizing coating 108 can act as a mask to remove the dielectric layer 102 exposed by the initial trench 106 to form a trench having a greater depth.
In this embodiment, a chemical vapor deposition process is used to form a planarizing coating 108 over the dielectric layer 102 that fills the initial trench 106.
In this embodiment, the planarization coating 108 may include a bottom anti-reflection layer Barc, and the material of the bottom anti-reflection layer may include at least one of SiON, si3N4, siC, SOC, and TiO 2.
Referring to fig. 5, a first barrier layer 112 having a first opening K3 is formed on the planarization coating layer 108, the first opening K3 exposes the top of the planarization coating layer 108, and the position of the first opening K3 is opposite to the position of the initial trench 106.
The first barrier layer 112 may function to protect the planarization coating 108 from damage to other portions of the planarization coating 108 during formation of the first opening K3.
In this embodiment, a photolithography process is used to form the first barrier layer 112 having the first opening K3.
Specifically, a first barrier material layer (not shown) is formed on the planarization coating layer 108, a photoresist (not shown) is formed on the first barrier material layer, and the first barrier material layer is patterned to form a first barrier layer 112 having a first opening K3.
In this embodiment, chemical vapor deposition (e.g., plasma enhanced PECVD, ion beam deposition IBD, sputtering, etc.) is used to form the first barrier material layer.
In this embodiment, the material of the first barrier layer 112 includes at least one of photoresist, silicon nitride, titanium nitride and titanium oxide.
In one particular embodiment, the material of the first barrier layer 112 includes photoresist. The photoresist may include a positive photoresist or a negative photoresist, and the present invention is not particularly limited herein.
In this embodiment, the width of the first opening K3 along the direction parallel to the surface of the substrate 100 is the same as the width of the initial trench 106 along the direction parallel to the surface of the substrate 100, and the sidewall of the first opening K3 is collinear with the sidewall of the initial trench 106 along the normal direction of the surface of the substrate 100.
Referring to fig. 6, the planarization coating 108 exposed by the first opening K3 is removed along the sidewall of the first barrier layer 112, and a mask opening K2 is formed in the planarization coating 108.
Mask opening K2 provides a process window for removing dielectric layer 102.
In this embodiment, the planarization coating 108 exposed by the first opening K3 is removed using a dry etching method. The etching gas used in the dry etching method comprises CF4, CHF3, ar and O2, the etching power is 2200-2600W, the etching time is 250-350 s, and the pressure is 200 mT-250 mT.
It should be noted that the first barrier layer 112 may be removed after the mask opening K2 is formed, or the first barrier layer 112 may be consumed (e.g., when the material of the first barrier layer 112 is photoresist) during the formation of the mask opening K2, and the first barrier layer 112 is consumed entirely when the mask opening K2 is formed.
Referring next to fig. 5 and 6, a protective layer 110 is formed on the planarizing coating layer 108 prior to the step of forming a first barrier layer 112 having a first opening K3 on the planarizing coating layer 108.
The protection layer 110 is used for protecting the planarization coating 108 from damage to the surface of the planarization coating 108 due to the consumption of the first barrier layer 112 during the formation of the mask opening K2.
In this case, the first barrier layer 112 may be located over the protective layer 110, and the first opening K3 exposes the protective layer 110.
In this embodiment, a low temperature oxidation process may be used to form the protective layer 110 on the planarizing coating layer 108.
Accordingly, the material of the protective layer 110 may include silicon oxide. The silicon oxide is selected as the material of the protective layer 110, so that the process compatibility can be improved, the process risk can be reduced, and compared with an organic material, the silicon oxide material has higher hardness and higher density, so that the protective effect of the protective layer 110 on the surface of the planarization coating 108 can be improved.
In one particular embodiment, the material of the protective layer 110 may include silicon oxide. The silicon oxide material has good adhesion with the substrate 100, which is beneficial to improving the stability and the processing effect of the subsequent process, and the silicon oxide is the silicon oxide commonly used in the semiconductor process, so that the difficulty and the process cost for forming the protective layer 110 can be reduced, and the process compatibility can be improved.
In the step of removing the planarization coating 108 exposed by the first opening K3 along the sidewall of the first barrier layer 112, the protective layer 110 exposed by the first opening K3 is also removed.
That is, the passivation layer 110 exposed by the first opening K3 is removed, and then the planarization coating 108 under the passivation layer 110 is removed. Accordingly, the sidewalls of mask opening K2 may include sidewalls of protective layer 110 and planarizing coating layer 108.
In this embodiment, a dry etching process is used to remove the passivation layer 110 exposed by the first opening K3 and the planarization coating 108 under the passivation layer 110.
Referring to fig. 7, after forming the planarization coating 108 having the mask opening K2 on the dielectric layer 102, the dielectric layer 102 exposed in the depth direction of the initial trench 106 is removed by using the planarization coating 108 as a mask and using a directional etching process to form a trench 114.
In this embodiment, the directional etching process includes a gas etching process, and in the process of removing the dielectric layer 102 exposed in the depth direction of the initial trench 106 by using the gas etching process, a polymer is also generated, and the polymer remaining on the sidewall of the initial trench 106 can serve as an etching barrier layer to protect the sidewall of the initial trench 106.
Specifically, during the process of removing the dielectric layer 102 exposed in the depth direction of the initial trench 106 by using the gas etching process, the sidewalls of the initial trench 106 may be etched. Because the polymer located in the initial trench 106 is used as the protective layer, and the target trench is formed by adopting a plurality of etching processes, in the one-time gas etching process, the thickness of the removed dielectric layer 102 is smaller, the time required for etching is shorter, the damage to the side wall of the dielectric layer 102 is smaller, and the side wall of the dielectric layer 102 still has better smoothness.
In this embodiment, the etching gas of the gas etching process includes C4F8, CHF3, ar, and O2, the etching power is 2200 to 2600W, the etching time is 700s to 900s, and the pressure is 200mT to 250mT.
Referring next to fig. 7, either etching process further includes removing the planarizing coating 108 over the dielectric layer 102 after removing the dielectric layer 102 with the initial trench 106 exposed in the depth direction using a directional etching process.
In this embodiment, an ashing process is used to remove the planarizing coating 108 over the dielectric layer 102. The ashing process can remove the planarization coating 108 in time, so that the organic material of the planarization coating 108 is not easy to pollute the machine.
Referring to fig. 3 to 7 in combination, in this embodiment, in the first etching process, the dielectric layer 102 exposed by the initial trench 106 is removed, the thickness of the removed dielectric layer 102 is smaller, and the depth of the formed trench 114 still does not reach the set depth, so that the dielectric layer 102 may be removed continuously in the steps of the method shown in fig. 3 to 7.
For example, referring to fig. 8, the etching process is continued on the dielectric layer 102 where the trench 114 is exposed until a target trench 120 having a set depth is formed in the dielectric layer 102.
It should be noted that, as the depth of the trench gradually deepens, the etched depth gradually decreases when the etching process is performed, which is beneficial to reducing the operation difficulty and improving the smoothness of the sidewall. In this embodiment, the target trench 120 with a depth of more than 10 μm can be formed by setting the depth to be more than 10 μm, that is, by adopting the above method.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (13)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411300702.1A CN119626901A (en) | 2024-09-18 | 2024-09-18 | Method for forming semiconductor structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411300702.1A CN119626901A (en) | 2024-09-18 | 2024-09-18 | Method for forming semiconductor structure |
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| CN119626901A true CN119626901A (en) | 2025-03-14 |
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| CN202411300702.1A Pending CN119626901A (en) | 2024-09-18 | 2024-09-18 | Method for forming semiconductor structure |
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