CN105575809B - A kind of manufacturing method of grooved MOSFET - Google Patents
A kind of manufacturing method of grooved MOSFET Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000010410 layer Substances 0.000 claims abstract description 70
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims abstract description 52
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 238000000576 coating method Methods 0.000 claims abstract description 45
- 239000011248 coating agent Substances 0.000 claims abstract description 44
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- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 30
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- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 46
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 24
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- 239000004065 semiconductor Substances 0.000 claims description 22
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- 230000003647 oxidation Effects 0.000 claims description 11
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- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 229910003978 SiClx Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of manufacturing method of grooved MOSFET; by before removing anti-reflection coating after formation of the groove; one layer of silicon oxide protective layer is first formed on the side wall of the groove and bottom; then it reuses and is heated to the phosphoric acid of certain temperature and carrys out erosion removal anti-reflection coating, the trenched side-wall and bottom can be caused to damage to avoid the phosphoric acid；After removing anti-reflection coating; remove the silicon oxide protective layer; the gate oxide then formed in the groove quality with higher; it is not in leakage channel that is damaged and forming grid and source electrode during test or use, so that the problem of entire trenched MOSFET devices failure.
Description
Technical field
The invention belongs to the manufacturing fields of semiconductor devices, are related to a kind of manufacturing method of grooved MOSFET.
Background technique
MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide
Semiconductcor field effect transistor) it is fast with its switching speed, frequency performance is good, input impedance is high, driving power is small, good temp characteristic,
The advantages that without second breakdown problem, is widely used in 4C (i.e. Communication, Computer, Consumer, Car: logical
Letter, computer, consumer appliances, automobile) etc. in fields.
Vertical-type grooved MOSFET is that some MOSFET devices are formed in the groove generated in the substrate, makes it
Have many advantages, such as high density of integration, high current ability, low on-resistance and excellent turn-off characteristic.Due to above-mentioned size and performance
Advantage, vertical-type grooved MOSFET is more widely used rapidly.The electric current of vertical-type grooved MOSFET is with vertical
Direction flowing through substrate, grid, which is located in the groove of semiconductor substrate and usually by filling polysilicon, to be formed.
The manufacturing process of existing grooved MOSFET is as shown in Figures 1 to 6, includes at least following steps:
1) it as shown in Figure 1, providing semi-conductive substrate 100, is sequentially formed from bottom to top in the semiconductor substrate 100
Epitaxial layer 101, polysilicon layer 102, hard exposure mask 103, anti-reflection coating 104 and the photoresist 105 with the first opening 106；Institute
The bottom that anti-reflection coating 104 is formed in the photoresist 105 is stated, for reducing the photoresist 105 during exposure
The reflection of the light of bottom improves the efficiency of exposure so that most of energy of exposure is all absorbed by the photoresist 105.
2) as shown in Fig. 2, etching the anti-reflection coating with the photoresist 105 with the first opening 106 for exposure mask
104 and the hard exposure mask 103 formed second opening 107；The removal photoresist 105 with the first opening 106
3) as shown in figure 3, etching the polysilicon layer 102 and the epitaxial layer 101, in the polysilicon layer 102 and portion
Divide in the epitaxial layer 101 and forms groove 108；
4) as shown in figure 4, removing the anti-reflection coating 104；
5) as shown in figure 5, forming gate oxidation in the side wall of second opening 107, the side wall of the groove 108 and bottom
Layer (GOX) 109, forms polysilicon gate 110 on the gate oxide 109；
6) as shown in fig. 6, removing the hard exposure mask 103, and source electrode is formed in the polysilicon layer 102 of the groove two sides
111。
In above-mentioned preparation process, formed in the polysilicon layer 102 and the epitaxial layer 101 groove 108 with
Afterwards, the method for the anti-reflection coating 104 is removed are as follows: using being heated to the phosphoric acid solution of certain temperature come described in erosion removal
Anti-reflection coating 104.However, the phosphoric acid solution while anti-reflection coating 104, can also erode one described in erosion removal
The silicon on a little 108 surfaces of groove, forms some pit equivalent damages on the surface of the groove 108.And in the groove 108
The process conditions requirement for forming the gate oxide 109 is very strict, and 108 surface of groove is caused to damage by the phosphoric acid corrosion
The place of wound must will affect the formation of the gate oxide 109, so that comparing in the gate oxide 109 that the place haveing damage is formed
It is weaker.In subsequent test and during use, the gate oxide 109 compared with weakness is easy breakage and falls and form grid
The leakage channel of pole and source electrode, so that entire trenched MOSFET devices failure.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of manufactures of grooved MOSFET
Method, in the manufacturing process for solving existing grooved MOSFET while using phosphoric acid corrosion removal anti-reflection coating,
A part of silicon of meeting erosion removal flute surfaces forms pit equivalent damage in the flute surfaces, so that subsequent in the groove
The gate oxide formed on surface is weaker, is easy damaged during test or use and causes entire plough groove type
The problem of MOSFET element fails.
In order to achieve the above objects and other related objects, the present invention provides a kind of manufacturing method of grooved MOSFET, institute
The method of stating includes at least:
1) semiconductor substrate is provided, epitaxial layer is sequentially formed on the semiconductor substrate, polysilicon layer, hard exposure mask, resists
Reflectance coating and the photoresist being open with first；
2) it using the photoresist with the first opening as exposure mask, etches the anti-reflection coating and the hard exposure mask forms second
Opening, second opening expose the polysilicon layer；The removal photoresist with the first opening；
3) polysilicon layer and the part epitaxial layer, the shape in the polysilicon layer and the part epitaxial layer are etched
At groove；
4) silicon oxide protective layer is formed in the side wall of second opening, the side wall of the groove and bottom；
5) anti-reflection coating is removed；
6) silicon oxide protective layer is removed；
7) gate oxide is formed in the side wall of second opening, the side wall of the groove and bottom, in the gate oxidation
Polysilicon gate is formed on layer.
Preferably, polysilicon layer described in step 1) is intrinsically polysilicon layer.
Preferably, the vertical sectional shape of the groove formed in step 3) is U-shaped.
Preferably, the method that the silicon oxide protective layer is formed in step 4) is thermal oxidation method.
Preferably, silicon oxide protective layer described in step 4) with a thickness of 5nm~15nm.
Preferably, the anti-reflection coating is removed using phosphoric acid solution in step 5).
Optionally, the phosphoric acid solution is to be heated to 155 DEG C~165 DEG C, the phosphoric acid that mass percent is 82%~88%
Solution.
Preferably, the silicon oxide protective layer is removed using hydrofluoric acid solution in step 6).
Preferably, the hydrofluoric acid solution is the hydrofluoric acid solution that molar concentration is 1%~3%, the hydrofluoric acid removal
The time of the silicon oxide protective layer is 1~30 minute.
Preferably, step 7) further includes removing the hard exposure mask, and the shape in the polysilicon layer of the groove two sides later
The step of at source electrode.
As described above, the manufacturing method of grooved MOSFET of the invention, has the advantages that in the present invention in shape
At before removing anti-reflection coating after groove, one layer of silicon oxide protective layer is first formed on the side wall of the groove and bottom, so
It reuses afterwards and is heated to the phosphoric acid of certain temperature and carrys out erosion removal anti-reflection coating, it can be to avoid the phosphoric acid to the channel side
Wall and bottom cause to damage；After removing anti-reflection coating, the silicon oxide protective layer is removed, is then formed in the groove
Gate oxide quality with higher, be not in damaged during test or use and form letting out for grid and source electrode
Reveal channel, so that the problem of entire trenched MOSFET devices failure.
Detailed description of the invention
Fig. 1-6 is shown as structural schematic diagram of the manufacturing method in each step of grooved MOSFET in the prior art.
Fig. 7 is shown as the flow chart of the manufacturing method of grooved MOSFET of the invention.
Fig. 8-15 is shown as the structural schematic diagram of the manufacturing method of grooved MOSFET of the invention in each step.
Component label instructions
100,200 semiconductor substrate
101,201 epitaxial layer
102,202 polysilicon layer
103,203 hard exposure mask
104,204 anti-reflection coating
105,205 photoresist
106,206 first opening
107,207 second opening
108,208 groove
109,210 gate oxide
110,211 polysilicon gate
111,212 source electrode
209 silicon oxide protective layers
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
It please refers to figure and please refers to Fig. 7 to Figure 15.It should be noted that diagram provided in the present embodiment is only with signal side
Formula illustrates basic conception of the invention, though it is only shown with related component in the present invention rather than when according to actual implementation in schema
Component count, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind
Become, and its assembly layout kenel may also be increasingly complex.
Such as Fig. 7 to Figure 15, the present invention provides a kind of manufacturing method of grooved MOSFET, and the method includes at least:
1) semiconductor substrate 200 is provided, sequentially forms epitaxial layer 201, polysilicon layer in the semiconductor substrate 200
202, hard exposure mask 203, anti-reflection coating 204 and the photoresist 205 with the first opening 206；
2) using the photoresist with the first opening 206 as exposure mask, the anti-reflection coating 204 and the hard exposure mask are etched
203 form the second opening 207, and second opening 207 exposes the polysilicon layer 202；Removal is described to have the first opening
206 photoresist 205；
3) polysilicon layer 202 and the part epitaxial layer 201 are etched, described in the polysilicon layer 202 and part
Groove 208 is formed in epitaxial layer 201；
4) silicon oxide protective layer 209 is formed in the side wall of second opening 207, the side wall of the groove 208 and bottom；
5) anti-reflection coating 204 is removed；
6) silicon oxide protective layer 209 is removed；
7) gate oxide 210 is formed in the side wall of second opening 207, the side wall of the groove 208 and bottom, in institute
State formation polysilicon gate 211 on gate oxide 210.
In step 1), the S1 step and Fig. 8 of Fig. 7 are please referred to, semiconductor substrate 200 is provided, in the semiconductor substrate
Epitaxial layer 201, polysilicon layer 202, hard exposure mask 203, anti-reflection coating 204 and with the first opening 206 are sequentially formed on 200
Photoresist 205.
Specifically, the material of the semiconductor substrate 200 can be silicon, SiGe, silicon-on-insulator (silicon
Oninsulator, SOI), germanium on insulator SiClx (silicon germanium on insulator, SGOI) or insulator
Upper germanium (germanium on insulator, GOI).Preferably, in the present embodiment, the material of the semiconductor substrate 200 is
Silicon.
Specifically, the epitaxial layer 201 can be with the upper surface of semiconductor substrate 200 described in covering part or covering entire half
The upper surface of conductor substrate 200, it is preferable that in the present embodiment, the epitaxial layer 201 covers the upper of entire semiconductor substrate 200
Surface.In the case where the material of the semiconductor substrate 200 is preferably silicon, the epitaxial layer 201 includes silicon.It is partly led described
The method that the epitaxial layer 201 is formed in body substrate 200 includes but are not limited to Epitaxial deposition.
Specifically, the material of the polysilicon layer 202 can be polysilicon or polycide etc., the side formed
Method can be Low Pressure Chemical Vapor Deposition (LPCVD, Low Pressure Chemical Vapor Depostion).This implementation
In example, using Low Pressure Chemical Vapor Deposition, the polysilicon layer is deposited on the epitaxial layer 201 using silicomethane as gas source
202.Preferably, in the present embodiment, the polysilicon layer 202 is intrinsically polysilicon layer.
Specifically, the hard exposure mask 203 can be silicon dioxide/silicon nitride/silica (Oxide/nitride/
Oxide, ONO) storehouse composition, or silicon oxide layer (LTO, the Low formed at low temperature using chemical vapour deposition technique
Temperature Oxide)。
Specifically, the anti-reflection coating 204 can use conventional coating process coating in the table of the hard exposure mask 203
On face.The material of the anti-reflection coating 204 can be the anti-reflection coating based on Si, such as silicon oxynitride or silicon nitride etc..
One layer of anti-reflection coating 204, the antireflection are first coated with before being coated with the photoresist 205 on the hard exposure mask 203
Coating 204 is used to reduce the reflection of the light of 205 bottom of photoresist during exposure, so that most of energy of exposure
It is all absorbed by the photoresist 205, improves the efficiency of exposure.
Specifically, being coated in the anti-reflection coating 204 after the photoresist 205, by photoetching process described
First opening 206 is formed on photoresist 205, opening of first opening 206 for defining the subsequent groove 208 is big
It is small.
In step 2), the S2 step and Fig. 9 of Fig. 7 are please referred to, using the photoresist with the first opening 206 as exposure mask, erosion
It carves the anti-reflection coating 204 and the hard exposure mask 203 forms the second opening 207, second opening 207 exposes described more
Crystal silicon layer 202；The removal photoresist 205 with the first opening 206.
Specifically, described can be covered in the reflectance coating 204 and firmly using dry etch process or wet-etching technology
Second opening 207 is formed on film 203, second opening 207 will be etched in the subsequent process the ditch as foundation
Slot 208.
In step 3), the S3 step and Figure 10 of Fig. 7 are please referred to, etches the polysilicon layer 202 and the part extension
Layer 201 forms groove 208 in the polysilicon layer 202 and the part epitaxial layer 201.
Specifically, the etching work that can be combined using conventional dry etching technics, wet-etching technology or dry method wet process
Skill is sequentially etched the polysilicon layer 202 and the epitaxial layer 201, the shape in the polysilicon layer 202 and the epitaxial layer 201
At the groove 208.
Specifically, the vertical sectional shape of the groove 208 is U-shaped.The bottom of the groove 208 is located at the epitaxial layer
In 201.
In step 4), the S4 step and Figure 11 of Fig. 7 are please referred to, in side wall, the groove of second opening 207
Silicon oxide protective layer 209 is formed on 208 side wall and bottom.
Specifically, the silicon oxide protective layer can be formed in the side wall of the groove 208 and bottom using thermal oxidation method
209, the thermal oxidation method can be steam in-situ synthesized (situ stream-generated, ISSG) either fast speed heat
Oxidizing process (RTO), the temperature range for forming the silicon oxide protective layer 209 is 650~1100 DEG C, and the silica of formation is protected
Sheath 209 with a thickness of 5~15nm.
It should be noted that being formed in the side wall of second opening 207, the side wall of the groove 208 and bottom described
The method of silicon oxide protective layer 209 is not limited solely to above-mentioned thermal oxidation method, and the method for same and similar effect may be implemented in other
It uses here.
Due to being using the phosphoric acid solution for being heated to certain temperature when subsequent removal anti-reflection coating 204
Carry out erosion removal, the phosphoric acid solution can react with silicon, but not react with silica, therefore in removal institute
One layer of silicon oxide protective layer is first formed on the side wall of the groove 208 and bottom surface before stating anti-reflection coating 204
209, the silicon of 208 side wall of groove and bottom surface can be protected not fallen by phosphoric acid corrosion well, and then guarantee it is subsequent
The quality of the gate oxide formed thereon.
In step 5), the S5 step and Figure 12 of Fig. 7 are please referred to, the anti-reflection coating 204 is removed.
Specifically, after the side wall of the groove 208 and bottom form the silicon oxide protective layer 209, it is molten using phosphoric acid
Corrosion removes the anti-reflection coating 204.Used phosphoric acid solution is to be heated to 155 DEG C~165 DEG C, and mass percent is
82%~88% phosphoric acid solution removes the anti-reflection coating.Preferably, in the present embodiment, used phosphoric acid solution is to add
Heat is to 160 DEG C, the phosphoric acid solution that mass fraction is 85%.
Specifically, deionized water can be used and rinse institute after removing the anti-reflection coating 204 using phosphoric acid solution
Surface and the groove 208 of hard exposure mask 203 are stated, is remained in 203 surface of hard exposure mask and the groove 208 with removal
Phosphoric acid solution.Preferably, the temperature of used deionized water is 60 DEG C~80 DEG C.Specific cleaning method can be existing half
Any one of the method for all cleaning wafers in semiconductor process.
In step 6), the S6 step and Figure 13 of Fig. 7 are please referred to, the silicon oxide protective layer 209 is removed.
Specifically, can be using all dry etch process for removing silicon, wet etching in existing semiconductor technology
The one kind for the technique that technique or dry method wet process combine removes the silicon oxide protective layer 209.Preferably, in the present embodiment,
The silicon oxide protective layer 209 is removed using wet-etching technology.It is further preferable that using described in hydrofluoric acid solution erosion removal
Silicon oxide protective layer 209, the molar concentration of used hydrofluoric acid solution are preferably 1%~3%, and the time of erosion removal is 1
~30 minutes.
Specifically, after using silicon oxide protective layer 209 described in hydrofluoric acid solution erosion removal, it is also necessary to using go from
Sub- water cleans surface and the groove 208 of the hard exposure mask 203, to remove 203 surface of hard exposure mask and the groove 208
The interior remaining hydrofluoric acid solution, specific cleaning method can be the method for all cleaning wafers in existing semiconductor technology
Any one of.After completing cleaning process using deionized water, it is also necessary to surface and the groove to the hard exposure mask 203
208 are dried, and specific drying means can be to be placed directly within drying under hot environment, can also be by volatile substances
It is dried to remove deionized water, for example, is dried using isopropanol (IPA, Isopropyl Alcohol).
In step 7), the S7 step and Figure 14 of Fig. 7 are please referred to, in side wall, the groove of second opening 207
Gate oxide 210 is formed on 208 side wall and bottom, and polysilicon gate 211 is formed on the gate oxide 210.
Specifically, the material of the gate oxide 210 can be silica, silica/silicon nitride or silica/nitridation
Silicon/oxidative silicon (Oxide/Nitride/Oxide, ONO).
Specifically, can by it is well known in the prior art it is any deposition or etching technics the groove 208 side wall
With the gate oxide 210 is formed on bottom.For example, the gate oxide 210 can be formed by depositing operation, it is described heavy
Product technique includes chemical vapor deposition (CVD) technique, such as SACVD (subatmospheric CVD) or high-density plasma oxide
(HDP) or atomic layer deposition (ALD) technique.
Specifically, thermal oxidation method, which also can be used, forms the gate oxide 210,.Specific method are as follows: in hot environment
Under, semiconductor structure exposure is formed to the gate oxide 210 of required thickness in an oxygen-containing environment.The thermal oxidation method technique
Usually realized in boiler tube.The thermal oxidation method can be steam in-situ synthesized either furnace oxidation method, form the grid
The temperature range of oxide layer 210 be 650~1100 DEG C, the gate oxide 210 of formation with a thickness of 6~50nm.
It should be noted that further including the removal hard exposure mask 203 after step 7), and described as shown in figure 15
The step of source electrode 212 are formed in the polysilicon layer 202 of 208 two sides of groove.Specifically, forming the technique of the source electrode 212 as this
Common process known to the technical staff of field, is described again here.
In conclusion before removing anti-reflection coating after formation of the groove in the present invention, first in the side wall of the groove and
One layer of silicon oxide protective layer is formed on bottom, is then reused and is heated to the phosphoric acid of certain temperature and carrys out erosion removal anti-reflective coating
Layer, can cause to damage to avoid the phosphoric acid to the trenched side-wall and bottom；After removing anti-reflection coating, the oxygen is removed
SiClx protective layer, the gate oxide then formed in the groove quality with higher, during test or use
It is not in leakage channel that is damaged and forming grid and source electrode, so that entire trenched MOSFET devices failure is asked
Topic.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (10)
1. a kind of manufacturing method of grooved MOSFET, which comprises the following steps:
1) semiconductor substrate is provided, sequentially forms epitaxial layer, polysilicon layer, hard exposure mask, antireflection on the semiconductor substrate
Coating and the photoresist being open with first；
2) it using the photoresist with the first opening as exposure mask, etches the anti-reflection coating and the hard exposure mask forms second and opens
Mouthful, second opening exposes the polysilicon layer；The removal photoresist with the first opening；
3) polysilicon layer and the part epitaxial layer are etched, forms ditch in the polysilicon layer and the part epitaxial layer
Slot；
4) silicon oxide protective layer is formed in the side wall of second opening, the side wall of the groove and bottom；
5) anti-reflection coating is removed；
6) silicon oxide protective layer is removed；
7) gate oxide is formed in the side wall of second opening, the side wall of the groove and bottom, on the gate oxide
Form polysilicon gate.
2. the manufacturing method of grooved MOSFET according to claim 1, it is characterised in that: polysilicon described in step 1)
Layer is intrinsically polysilicon layer.
3. the manufacturing method of grooved MOSFET according to claim 1, it is characterised in that: institute formed in step 3)
The vertical sectional shape for stating groove is U-shaped.
4. the manufacturing method of grooved MOSFET according to claim 1, it is characterised in that: form the oxygen in step 4)
The method of SiClx protective layer is thermal oxidation method.
5. the manufacturing method of grooved MOSFET according to claim 1, it is characterised in that: silica described in step 4)
Protective layer with a thickness of 5nm~15nm.
6. the manufacturing method of grooved MOSFET according to claim 1, it is characterised in that: molten using phosphoric acid in step 5)
Liquid removes the anti-reflection coating.
7. the manufacturing method of grooved MOSFET according to claim 6, it is characterised in that: the phosphoric acid solution is heating
To 155 DEG C~165 DEG C, the phosphoric acid solution that mass percent is 82%~88%.
8. the manufacturing method of grooved MOSFET according to claim 1, it is characterised in that: use hydrofluoric acid in step 6)
Solution removes the silicon oxide protective layer.
9. the manufacturing method of grooved MOSFET according to claim 8, it is characterised in that: the hydrofluoric acid solution is to rub
The hydrofluoric acid solution that your concentration is 1%~3%, the time that the hydrofluoric acid removes the silicon oxide protective layer is 1~30 minute.
10. the manufacturing method of grooved MOSFET according to claim 1, it is characterised in that: further include after step 7)
The hard exposure mask is removed, and in the polysilicon layer of the groove two sides the step of formation source electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410531557.8A CN105575809B (en) | 2014-10-10 | 2014-10-10 | A kind of manufacturing method of grooved MOSFET |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410531557.8A CN105575809B (en) | 2014-10-10 | 2014-10-10 | A kind of manufacturing method of grooved MOSFET |
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| Publication Number | Publication Date |
|---|---|
| CN105575809A CN105575809A (en) | 2016-05-11 |
| CN105575809B true CN105575809B (en) | 2019-02-01 |
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| US6518148B1 (en) * | 2001-09-06 | 2003-02-11 | Taiwan Semiconductor Manufacturing Company, Ltd | Method for protecting STI structures with low etching rate liners |
| CN101101877A (en) * | 2007-07-20 | 2008-01-09 | 哈尔滨工程大学 | A method of manufacturing a trench gate power semiconductor device |
| CN102361007A (en) * | 2011-11-02 | 2012-02-22 | 上海宏力半导体制造有限公司 | Method for etching groove and semiconductor device |
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| US6518148B1 (en) * | 2001-09-06 | 2003-02-11 | Taiwan Semiconductor Manufacturing Company, Ltd | Method for protecting STI structures with low etching rate liners |
| CN101101877A (en) * | 2007-07-20 | 2008-01-09 | 哈尔滨工程大学 | A method of manufacturing a trench gate power semiconductor device |
| CN102361007A (en) * | 2011-11-02 | 2012-02-22 | 上海宏力半导体制造有限公司 | Method for etching groove and semiconductor device |
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