CN105489647B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a method for manufacturing a semiconductor device. The method includes: providing a semiconductor substrate; forming a first semiconductor layer on part of the substrate; forming a second semiconductor layer on the substrate and the first semiconductor layer; Isolation is formed, wherein the first semiconductor layer includes a first part located in part of the active region and a second part extending toward the end of the gate, the first part is as wide as the active region in the gate width direction and has a width in the gate length direction greater than or equal to the gate length; forming a device structure on the active region of the second semiconductor layer, the gate of the device structure is located above the first part; forming a through etching hole in the second semiconductor layer above the second part; Etching and removing the first semiconductor layer through the etching hole to form a cavity; filling the cavity and the etching hole with a dielectric material to form a buried layer and an insulating hole respectively. The invention realizes the SOI-like device with a partially buried layer through the body substrate, and the thickness of the buried layer and the channel can be adjusted.

Description

A kind of semiconductor device and its manufacturing method

technical field

The invention belongs to the field of semiconductor manufacturing, and in particular relates to a semiconductor device and a manufacturing method thereof.

Background technique

With the continuous reduction of the feature size of the device, after entering the nanometer scale, especially the size below 22nm, the problems close to the limit of semiconductor physical devices come one after another, such as capacitance loss, leakage current increase, noise promotion, latch-up effect and short channel In order to overcome these problems, SOI (Silicon-On-Insulator, Silicon-On-Insulator) technology came into being.

The SOI substrate is divided into thick layer and thin layer SOI. The thickness of the top layer silicon of the thin layer SOI device is smaller than the width of the maximum depletion layer under the gate. When the thickness of the top layer silicon becomes thinner, the device changes from partially depleted (Partially Depletion) to fully depleted Fully Depletion transition, when the top silicon is less than 50nm, it is ultra-thin SOI (Ultra thin SOI, UTSOI), the SOI device is completely depleted, and the fully depleted device has a large current drive capability, a steep sub-threshold slope, The advantages of smaller short channel, narrow channel effect and complete elimination of Kink effect are especially suitable for high-speed, low-voltage, low-power circuit applications. Ultra-thin SOI has become an ideal solution for processes below 22nm.

However, currently, the cost of SOI substrates is relatively high, and the specifications of the provided SOI substrates are relatively simple, so the thickness of each layer cannot be adjusted according to the needs of the device.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art, and provide a semiconductor device and its manufacturing method, which can realize a SOI-like device with a partially buried layer by using a bulk substrate, and the thickness of the channel and the thickness of the buried layer can be adjusted.

To achieve the above object, the technical solution of the present invention is:

A method of manufacturing a semiconductor device, comprising the steps of:

Provide semiconductor substrates;

A first semiconductor layer is formed on a part of the substrate, a second semiconductor layer is formed on the substrate and the first semiconductor layer, isolation is formed on the substrate, wherein the first semiconductor layer includes a first part located in a part of the active region and The second part extending in the gate end direction, the first part has the same width as the active region in the gate width direction and the width in the gate length direction is at least equal to the gate length;

forming a device structure on the active region of the second semiconductor layer, the gate of the device structure is located on the first portion of the first semiconductor layer;

forming a through etch hole in the second semiconductor layer over the second portion of the first semiconductor layer;

removing the first semiconductor layer by etching holes to form cavities;

Dielectric material is filled in the cavity and the etching hole to form a buried layer and an insulating hole respectively.

Optionally, the step of forming the first semiconductor layer and the second semiconductor layer specifically includes:

forming a first mask layer on the substrate, and etching a partial thickness of the substrate;

performing selective epitaxial growth to form a first semiconductor layer;

removing the first mask layer;

performing epitaxial growth to form a second semiconductor layer;

performing etching to form isolation trenches;

fill the isolation trench to form isolation;

Wherein, the first semiconductor layer includes a first portion located in the active region and a second portion extending toward the end of the gate.

Optionally, the substrate is a silicon substrate, the first semiconductor layer is G _x Si _1-x , where 0<x<1, and the second semiconductor layer is silicon.

Optionally, the step of removing the first semiconductor layer by etching holes to form a cavity specifically includes:

The first semiconductor layer is etched and removed by using an etchant of HF, H ₂ O ₂ , CH ₃ COOH and H ₂ O to form a cavity.

Optionally, the step of filling the cavity and the etching hole with a dielectric material specifically includes:

ALD process or CVD process is used to fill the cavity with the first dielectric layer and form the first dielectric layer on the inner wall of the etching hole; and fill the etching hole with the second dielectric layer.

Optionally, the first semiconductor layer extends to part of the source and drain regions of the device structure in the substrate.

In addition, the present invention also provides a semiconductor device formed by the above method, including:

semiconductor substrate;

Buried layers on semiconductor substrates;

The buried layer and the second semiconductor layer on the substrate, wherein the buried layer includes a first part located in part of the active region and a second part extending toward the end of the gate, the first part is as wide as the active region in the gate width direction and The width in the direction of the gate length is greater than or equal to the gate length;

a device structure on the active region of the second semiconductor layer, the gate of the device structure is located above the first portion of the buried layer;

An insulating hole penetrating through the second semiconductor layer over the second portion of the buried layer.

Optionally, the buried layer is a first dielectric layer, and the dielectric material of the insulating hole includes the first dielectric layer on the inner wall of the hole and the second dielectric layer filling the hole.

Optionally, the first dielectric layer is a high-k dielectric material, and the second dielectric layer is silicon oxide.

Optionally, the buried layer extends to part of the source and drain regions of the device structure in the substrate.

In the manufacturing method of the semiconductor device of the present invention, the first and second parts of the first semiconductor layer are formed in part of the active region and along the gate direction of the active region, and then, through the first semiconductor layer on the second part Etch holes in the second semiconductor layer to remove the first semiconductor layer and refill the dielectric material, so that a SOI-like device with a partially buried layer can be realized through the bulk substrate, and at the same time, the thickness of the buried layer and the thickness of the channel can be determined by The thicknesses of the formed first and second semiconductor layers are adjusted separately to meet the requirements of different devices, and the process is simple and easy.

Description of drawings

In order to more clearly illustrate the technical solutions implemented by the present invention, the following will briefly introduce the accompanying drawings that need to be used in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those skilled in the art Ordinary technicians can also obtain other drawings based on these drawings on the premise of not paying creative work.

Fig. 1 shows the flowchart of the manufacturing method of semiconductor device of the present invention;

2-11A are top views and schematic cross-sectional structure diagrams along the directions of AA and BB in each manufacturing process of manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do it without departing from the meaning of the present invention. By analogy, the present invention is therefore not limited to the specific examples disclosed below.

Secondly, the present invention is described in detail in combination with schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, and it should not be limited here. The protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

Referring to Fig. 1, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate; forming a first semiconductor layer on a part of the substrate, and forming a second semiconductor layer on the substrate and the first semiconductor layer , isolation is formed on the substrate, wherein the first semiconductor layer includes a first part located in a part of the active region and a second part extending toward the end of the gate, the first part is as wide as the active region in the gate width direction and at the gate The width in the long direction is greater than or equal to the gate length; a device structure is formed on the active region of the second semiconductor layer, and the gate of the device structure is located on the first part of the first semiconductor layer; on the second part of the first semiconductor layer A through etching hole is formed in the second semiconductor layer; the first semiconductor layer is etched and removed through the etching hole to form a cavity; a dielectric material is filled in the cavity and the etching hole to form a buried layer and an insulating hole respectively.

In the manufacturing method of the present invention, the first and second parts of the first semiconductor layer are formed in part of the active region and along the gate direction of the active region, and then, through the second part on the second part Etching holes in the semiconductor layer to remove the first semiconductor layer and refilling the dielectric material can realize a SOI-like device with a partially buried layer through the bulk substrate. At the same time, the thickness of the buried layer and the channel thickness can be determined by the formed First, the thickness of the second semiconductor layer is adjusted separately to meet the requirements of different devices, and the process is simple and easy.

In order to better understand the technical solutions and technical effects of the present invention, a detailed description will be given below in conjunction with the flow chart of the semiconductor device manufacturing method of the present invention FIG. 1 and specific embodiments.

First, in step S01 , a semiconductor substrate 100 is provided, as shown in FIG. 2 and FIG. 2A (a schematic cross-sectional view along the line AA of FIG. 2 ).

In the embodiment of the present invention, the semiconductor substrate 100 may be a Si substrate, a Ge substrate or the like. In other embodiments, it may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., and may also be a stacked structure, such as Si/SiGe, etc. In this embodiment, the semiconductor substrate 100 is a bulk silicon substrate.

Next, in step S02, the first semiconductor layer 106 is formed on part of the substrate, the second semiconductor layer 108 is formed on the substrate 100 and the first semiconductor layer 106, and the isolation 110 is formed on the substrate, wherein the first semiconductor layer 106 It includes a first part 106-1 located in part of the active region and a second part 106-2 extending toward the end of the gate. The first part 106-1 is as wide as the active region in the gate width direction and has a width in the gate length direction Greater than or equal to the gate length, refer to Fig. 6, Fig. 6A and Fig. 6B (A- and BB-direction cross-sectional schematic diagrams of Fig. 6).

In this embodiment, the first semiconductor layer may be formed by selective epitaxy, and then the second semiconductor layer may be formed by an epitaxial growth process, so as to form a semiconductor layer with a crystal structure.

Specifically, first, a first mask layer 102 is deposited on the substrate 100, the first mask may be silicon oxide, silicon nitride, silicon oxynitride, or their stacked layers, and the first mask layer 102 Form a photoresist 104 on it, as shown in FIG. 2 and FIG. 2A; then, under the cover of the photoresist 104, etch the first mask layer 102 to form a patterned first mask layer, And remove the photoresist 104, under the cover of the first mask layer 102, further etch the substrate 100 with a certain thickness, and form the formation area for the subsequent formation of the first semiconductor layer on the substrate, as shown in Figure 3 and Figure 3 3A (A schematic cross-sectional view of AA in FIG. 3 ).

Next, perform selective epitaxial growth (EPI), and form a first semiconductor layer on the region after substrate etching, as shown in Figure 4 and Figure 4A (A-A cross-sectional schematic view of Figure 4), the first semiconductor layer can be is G _x Si _1-x , where 0<x<1, the thickness can be 1-200nm, typically 10nm or 20nm; then, the first mask layer 102 is removed, and the second semiconductor layer is epitaxially grown, thus , the second semiconductor layer 108 is formed on the substrate 100 and the first semiconductor layer 106, as shown in Figure 5 and Figure 5A (A schematic cross-sectional view of AA in Figure 5), the second semiconductor layer 108 can be Si, and the thickness can be 3-200nm, typically 10nm or 15nm.

Then, referring to FIG. 6 , the isolation 110 is formed on the substrate. Specifically, a patterned second mask (not shown) is first formed on the second semiconductor layer 108 and etched, and a part of the area is etched. Etching the second semiconductor layer and the substrate, etching the first and second semiconductor layers and the substrate in some areas, until the substrate is etched to a certain depth, forming isolation trenches, and filling the isolation trenches, and then removing the first two masks to form the isolation 110 .

In the present invention, the regions of the first and second semiconductor layers defined by the isolation 110, as shown in FIGS. There is a first part 106-1 formed in part of the active region 109, the first part 106-1 is as wide as the active region in the gate width direction and the width in the gate length direction is greater than or equal to the gate length, so that when forming the gate Finally, the first part in the gate length direction can separate the channel from the substrate, so that a buried layer can be formed at least below the channel. More preferably, the width of the first part in the gate length direction can be slightly larger than the gate length , and slightly extended to the source and drain regions. The second portion 106-2 is formed in the direction extending toward the end of the gate, that is, in the gate width direction. The second part may extend toward one end or both ends of the gate. In this embodiment, preferably, the second part 106-2 extends toward one end of the gate, and the end is the opposite end with which the gate contact is formed.

The epitaxial process can form a crystalline semiconductor layer, which is a higher quality semiconductor layer, so as to improve the performance of the subsequently formed device. Of course, other methods can be used to form the first and second semiconductor layers according to the specific requirements of the device.

Next, in step S03, a device structure 200 is formed on the active region 109 of the second semiconductor layer 108, and the gate 112 of the device structure is located on the first portion 106-1, referring to FIGS. 7 and 7A (direction AA of FIG. 7 Schematic diagram of the cross-section).

The device structure 200 can be formed according to a conventional process, and a gate-first or gate-last process can be used. In this embodiment, the gate-last process is used to form the device structure. First, a gate dielectric layer, a dummy gate (not shown) and its sidewalls are formed on the second semiconductor layer 108. The gate dielectric layer may be a thermal oxide layer. Or other suitable dielectric materials, such as silicon oxide, silicon nitride, etc., in one embodiment, may be silicon dioxide, which may be formed by thermal oxidation. The dummy gate can be amorphous silicon, polysilicon or silicon oxide, etc., and in one embodiment, it can be amorphous silicon. The sidewall 114 can have a single-layer or multi-layer structure, and can be made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluoride-doped silicon glass, low-k dielectric materials and combinations thereof, and/or other suitable materials In one embodiment, the spacer 114 may be a two-layer structure of silicon nitride and silicon oxide.

Then, the source and drain regions are formed on both sides of the dummy gate. In one embodiment, in this embodiment, ion implantation and activation are performed according to the desired device type to form the source and drain regions 116. Of course, in other embodiments, the The source and drain regions can be formed on the second semiconductor by means of epitaxial doping. And a metal silicide layer 118 is formed on the source and drain regions 116 .

Next, the interlayer dielectric layer is covered on both sides of the dummy gate, and the dummy gate and the gate dielectric layer are removed by wet etching, and the gate stack 112 is re-formed. The gate stack 112 includes a gate dielectric layer and a gate. The gate dielectric layer can be A high-k dielectric material (for example, a material with a high dielectric constant compared with silicon oxide) or other suitable dielectric materials, such as a high-k dielectric material such as a hafnium-based oxide, the gate can be a metal gate electrode can be a layer Or multi-layer structure, may include metal material or polysilicon or their combination, metal material such as Ti, TiAl _x , TiN, TaN _x , HfN, TiC _x , TaC _x and so on.

Thus, a device structure is formed on the second semiconductor layer, and the embodiment of forming the device structure here is only an example, and any desired device structure can be formed as required.

Thus, a device structure is formed on the active region of the second semiconductor layer, as shown in FIGS. 7 and 7A , the embodiment of forming the device structure here is only an example, and any desired device structure can be formed as required.

Then, in step S04 , a through etching hole 124 is formed in the second semiconductor layer 108 on the second portion 106 - 2 , as shown with reference to FIG. 8 and FIG. 8B (a schematic cross-sectional view taken along the line BB in FIG. 8 ).

After the device structure is formed, continue to cover the interlayer dielectric layer 120 on the device, as shown in FIG. 8A (the schematic cross-sectional view of AA in FIG. 8 ). In the present invention, the etching hole 124 is formed before the step of forming the contact hole. In this embodiment, the etching hole is formed in the second semiconductor layer 108 above the second part 106-2, and penetrates through the entire second semiconductor layer, so that the first semiconductor layer can be removed later by using the through etching hole. . Specifically, a third mask layer (not shown in the figure), such as photoresist, is formed on the interlayer dielectric layer 120. Under the cover of the third mask layer, the interlayer dielectric layer 120, the second The semiconductor layer 108 and the first semiconductor layer 106 may also further over-etch part of the substrate 100 to form an etching hole 124 and remove the third mask, as shown in FIG. 8B . In other embodiments, when forming the etching hole, etching may also be performed from the interlayer dielectric layer 120 until the first semiconductor layer is exposed, that is, the first semiconductor layer 106 is not etched, but is subsequently removed. The first semiconductor layer is removed together in the step of forming the cavity.

Next, in step S05 , the first semiconductor layer 106 is removed by etching the hole 124 to form a cavity 130 , as shown in FIGS. 9A and 9B (A-A and BB cross-sectional diagrams, top view refer to FIG. 8 ).

In this embodiment, the first semiconductor layer can be removed by wet etching, and the etchant can be a mixed solution of HF, H ₂ O ₂ , CH ₃ COOH and H ₂ O. In one embodiment, HF (49 %): H ₂ O ₂ (30%): CH ₃ COOH (99.8%): H ₂ O = 1:18:27:8 etchant, until all the first semiconductor layer is removed, thereby under the device structure , a cavity 130 is formed between the second semiconductor layer 108 and the substrate 100, as shown in FIGS. 9A and 9B.

Then, in step S06, a dielectric material is filled in the cavity 130 and the etching hole 124 to form the buried layer 131 and the insulating hole 133 respectively, as shown in FIGS.

In this embodiment, first, the filling of the first dielectric material can be performed by ALD (atomic layer deposition) or CVD (chemical vapor deposition) process, and the first dielectric material can be an oxide material or a high-k dielectric material or other Insulating dielectric material, when filling the cavity to form the first dielectric layer 131, the first dielectric layer is also deposited on the inner wall of the etching hole 124, as shown in Figure 10B (BB to sectional schematic diagram, top view omitted); then , fill the etching hole 124 with a second dielectric material, the second dielectric material can be a dielectric material such as silicon oxide, and planarize until the interlayer dielectric layer 120 is exposed, and form a second dielectric layer 132 in the etching hole, thereby Filling the cavity with the first dielectric material forms a buried layer 131 , and filling the etching hole 124 with the first and second dielectric materials forms an insulating hole 133 , as shown in FIG. 10B .

In the embodiment of the present invention, the formed first semiconductor layer 106 extends into the source and drain regions 116 along the gate length direction, so that after removing the first semiconductor layer and filling the dielectric material to form the buried layer 131, the buried layer extending to part of the source and drain regions 116 in the substrate. This makes the device not only has some of the advantages of ETSOI, but also avoids the process complexity and parasitic capacitance caused by RSD (Raised Source Drain) in the ETSOI process, and reduces the corrosion area of the first semiconductor layer. For easier control of the corrosion process.

In other embodiments, other methods can also be used to fill the cavity, for example, thermal oxidation can be used to oxidize, so that the oxide material of the substrate and the second semiconductor layer fills the cavity, and then, the hole is etched of filling.

Then, other necessary processes can be performed.

A fifth mask layer (not shown) can be formed on the interlayer dielectric layer 120 according to a conventional process, and under the cover of the fifth mask layer, the etching of the interlayer dielectric layer is performed to form a contact hole ( The figure is not shown); then, the metal material is filled and planarized until the interlayer dielectric layer 120 is exposed, so as to form the source-drain contact 142 and the gate contact 144, referring to FIGS. 11 and 11A (AA of FIG. 11 to the cross-sectional diagram).

So far, the semiconductor device according to the manufacturing method of the present invention is formed. 11, shown in FIG. 11A and FIG. 10B, the semiconductor device includes: a semiconductor substrate 100; a buried layer 131 on the semiconductor substrate 100; a second semiconductor layer 108 on the buried layer 131 and the substrate 100, wherein the buried Layer 131 includes a first portion 106-1 located in part of the active region and a second portion 106-2 extending toward the end of the gate. The first portion is as wide as the active region in the gate width direction and has a width greater than or Equal to the gate length; the device structure 200 on the active region of the second semiconductor layer 108, the gate 112 of the device structure is located above the first part 106-1 of the buried layer; above the second part 106-2 of the buried layer The insulating hole 133 penetrating through the second semiconductor layer 108 .

In an embodiment of the present invention, the buried layer 131 is a first dielectric layer, and the dielectric material of the dielectric material of the insulating hole 133 includes the first dielectric layer 131 on the inner wall of the etching hole and the second dielectric layer filling the etching hole 132. For example, the first dielectric layer may be a high-k dielectric material, and the second dielectric layer may be silicon oxide.

In an embodiment of the present invention, the buried layer 131 extends into part of the source and drain regions 116 of the device structure in the substrate 100 .

The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (10)

1. a kind of manufacturing method of semiconductor devices, which is characterized in that including step：

Semiconductor substrate is provided；

The first semiconductor layer is formed on section substrate, the second semiconductor layer, substrate are formed on substrate and the first semiconductor layer It is upper to form isolation, wherein, the first semiconductor layer includes the first portion being located in the active area of part and prolongs to grid end direction The second portion stretched, first portion is in grid width direction with active area with wide and long more than or equal to grid in the width of grid length direction；

Device architecture is formed on the active area of the second semiconductor layer, the grid of device architecture is located at the first of the first semiconductor layer On part；

The etched hole of perforation is formed in the second semiconductor layer on the second portion of the first semiconductor layer；

By the first semiconductor layer of etched hole erosion removal, to form cavity；

The filled media material in cavity and etched hole, to be respectively formed buried regions and insulated hole.

2. manufacturing method according to claim 1, which is characterized in that form the first semiconductor layer and the second semiconductor layer Step specifically includes：

The first mask layer, and the substrate of etched portions thickness are formed on substrate；

The epitaxial growth of making choice property forms the first semiconductor layer；

Remove the first mask layer；

Epitaxial growth is carried out, forms the second semiconductor layer；

It performs etching, to form isolated groove；

Isolated groove is filled, to form isolation；

Wherein, the first semiconductor layer includes the first portion being located in active area and the second portion extended to grid end.

3. manufacturing method according to claim 2, which is characterized in that the substrate be silicon substrate, first semiconductor Layer is Ge_xSi_1-x, wherein 0<x<1, second semiconductor layer is silicon.

4. manufacturing method according to claim 3, which is characterized in that by the first semiconductor layer of etched hole erosion removal, The step of to form cavity, specifically includes：

Using HF, H₂O₂、CH₃COOH and H₂The etching agent of O carries out the first semiconductor layer of erosion removal, to form cavity.

5. manufacturing method according to claim 1, which is characterized in that the step of filled media material in cavity and etched hole Suddenly specifically include：

Using ALD techniques or CVD techniques, first medium layer is filled up in the cavities and forms first on the inner wall of etched hole Dielectric layer；Second dielectric layer is filled up in etched hole.

6. manufacturing method according to claim 1, which is characterized in that first semiconductor layer extends to the device in substrate In the part source-drain area of part structure.

7. a kind of semiconductor devices, which is characterized in that including：

Semiconductor substrate；

Buried regions in Semiconductor substrate；

The second semiconductor layer on buried regions and substrate, wherein, buried regions includes the first portion being located in the active area of part and to grid The second portion of extreme portion's extension, first portion with width and are more than or wait in the width of grid length direction in grid width direction and active area It is long in grid；

Device architecture on the active area of the second semiconductor layer, the grid of device architecture are located on the first portion of buried regions；

The insulated hole of the second semiconductor layer of perforation on the second portion of buried regions.

8. semiconductor devices according to claim 7, which is characterized in that buried regions is first medium layer, the insulated hole Dielectric material includes the first medium layer on the inner wall of hole and the second dielectric layer in filling hole.

9. semiconductor devices according to claim 8, which is characterized in that the first medium layer is high K medium material, the Second medium layer is silica.

10. semiconductor devices according to claim 7, which is characterized in that the buried regions extends to the device junction in substrate In the part source-drain area of structure.