CN1901228A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. In this semiconductor device, a buried oxide film (12) is formed on a single crystal semiconductor substrate (11), and a first single crystal semiconductor layer (13) constituting a back gate electrode is formed on the buried oxide film (12). Then, a buried oxide film (14) is formed on the first single crystal semiconductor layer (13), and a second single crystal semiconductor layer (15a, 15b) separated by mesas is deposited on the buried oxide film (14), so that the first 2. The film thickness of the single crystal semiconductor layer (15a, 15b) is thicker than that of the first single crystal semiconductor layer 13, and an SOI transistor is formed on the second single crystal semiconductor layer (15a, 15b). In this way, it is possible to suppress a decrease in the crystallinity of the semiconductor layer forming the field effect transistor, and to arrange a low-resistance back gate electrode under the semiconductor layer forming the field effect transistor.

Description

Semiconductor device and method for manufacturing semiconductor device

technical field

The invention relates to a semiconductor device and a method for manufacturing the semiconductor device, which are particularly suitable for use in a method for forming a back gate electrode of an SOI (Silicon On Insulator) transistor.

Background technique

Field-effect transistors formed on SOI (Silicon On Insulator) substrates have drawn much attention for their usefulness due to their ease of element isolation, no latch up free, and small source/drain junction capacitance.

In addition, for example, in Patent Document 1, a method is proposed in which, in order to form a silicon thin film with good crystallinity and uniformity on a large-area insulating film, an amorphous or The polysilicon layer is irradiated in a pulse shape with an ultraviolet ray beam to form a polysilicon film in which approximately square single crystal grains are arranged in a checkerboard shape on the insulating film, and then the polysilicon film is polished by CMP (Chemical Mechanical Polishing). The surface is planarized.

[Patent Document 1]: Japanese Unexamined Patent Application Publication No. 10-261799

However, grain boundaries, microtwins, and other various minute defects exist in a silicon thin film formed on an insulating film. Therefore, a field effect transistor formed on such a silicon thin film has a problem of deterioration in transistor characteristics compared with a field effect transistor formed on a pure single crystal silicon thin film.

In addition, when stacking field effect transistors formed on a silicon thin film, the field effect transistors are located in the lower layer. Therefore, there is a problem that the flatness of the base insulating film on which the upper silicon thin film is formed is deteriorated, and the heat treatment conditions for forming the upper silicon thin film are restricted, and the crystallinity of the upper silicon thin film is lower than that of the lower silicon thin film.

Furthermore, in conventional semiconductor integrated circuits, when the channel length is shortened with miniaturization of transistors, the rise characteristic of the drain current in the subthreshold region is degraded. Therefore, there is a problem that while the low-voltage operation performance of the transistor is affected, the leakage current at off time is increased, which not only increases the power consumption during operation and standby, but also becomes the main cause of damage to the transistor.

Contents of the invention

Therefore, an object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device, which can suppress the deterioration of the crystallinity of the semiconductor layer forming the field effect transistor, and can dispose the semiconductor layer under the semiconductor layer forming the field effect transistor. Low resistance back gate electrode.

In order to solve the above problems, a semiconductor device according to an embodiment of the present invention includes: a back gate electrode formed of a first single crystal semiconductor layer formed on a first insulating layer; and a back gate electrode formed on the first single crystal semiconductor layer. a second insulating layer; a second single crystal semiconductor layer formed on the second insulating layer and having a film thickness thinner than that of the first single crystal semiconductor layer; a gate formed on the second single crystal semiconductor layer an electrode; and a source/drain layer formed on the second single crystal semiconductor layer and disposed on the sides of the gate electrode.

Therefore, the degree of freedom in arranging the back gate electrode can be increased, and the back gate electrode can be arranged without being restricted by the arrangement of the gate electrode, source/drain contact electrodes, and the like. Therefore, the design freedom of the field effect transistor can be improved, and the threshold voltage of the field effect transistor can be controlled by using the bias voltage of the back gate electrode, or the subthreshold characteristic can be improved by using the double gate structure.

In addition, by providing the back gate electrode on the back side of the single crystal semiconductor layer, the drain potential can be shielded by the back gate electrode. Therefore, even when the drain potential is applied from the surface of the silicon thin film of SOI, it is possible to prevent a high voltage from being generated at the interface between the bias layer of the drain or the high-concentration impurity diffusion layer and the buried oxide film. As a result, it is possible to prevent a local strong electric field from being generated at the interface between the bias layer of the drain or the high-concentration impurity diffusion layer and the buried oxide film, thereby achieving a higher withstand voltage of the SOI transistor.

In addition, the potential of the active region of the SOI transistor can be controlled through the back gate electrode, the threshold value of the SOI transistor can be controlled, and the rising characteristics of the drain current in the subthreshold region can be improved, and at the same time, the electric field at the channel end on the drain side can be eased . Therefore, the transistor can be operated in a low-voltage state, the leakage current can be reduced when it is turned off, and the power consumption during operation or standby can be reduced, and at the same time, the withstand voltage characteristic of the SOI field effect transistor can be improved.

In addition, by making the first single crystal semiconductor layer forming the back gate electrode thicker than the second single crystal semiconductor layer forming the SOI transistor, the resistance of the back gate electrode can be reduced. Therefore, the threshold position of the SOI transistor can be controlled at a low voltage, and the area of the back gate electrode can be increased, thereby reducing the number of contacts connected to the back gate electrode and suppressing an increase in chip size.

In addition, a semiconductor device according to an embodiment of the present invention further includes a wiring layer electrically connecting the back gate electrode and the gate electrode.

Therefore, the back gate electrode and the gate electrode can be regulated to have the same potential, and the controllability of the potential of the channel region can be improved. For this reason, increase in chip size can be suppressed, and leakage current at the time of off can be reduced. Therefore, it is possible to reduce power consumption during operation or standby, and to achieve a higher withstand voltage of the field effect transistor.

In addition, a method for manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a first single crystal semiconductor layer on a single crystal semiconductor substrate; A step of forming a second single crystal semiconductor layer whose rate is lower than that of the first single crystal semiconductor layer; forming a third single crystal semiconductor layer having the same composition as that of the first single crystal semiconductor layer on the second single crystal semiconductor layer. A step of forming a crystalline semiconductor layer: on the third single crystalline semiconductor layer, forming a fourth single crystalline film having the same composition as that of the second single crystalline semiconductor layer and having a film thickness thinner than that of the second single crystalline semiconductor layer A step of semiconductor layer; a step of forming a first groove penetrating through the first to fourth single crystal semiconductor layers and exposing the single crystal semiconductor substrate; forming the second and second grooves in the first groove. A step of supporting the fourth single crystal semiconductor layer on the support body on the single crystal semiconductor substrate; a step of forming a second groove for the first and third single crystal semiconductors on which the support body is formed At least a part of the layer is exposed from the second and fourth single crystal semiconductor layers; by selectively etching the first and third single crystal semiconductor layers through the second groove, the first and third single crystal semiconductor layers are respectively etched. 3 A step of removing the single crystal semiconductor layer and forming the first and second cavities; by thermally oxidizing the single crystal semiconductor substrate and the second and fourth single crystal semiconductor layers, forming A step of embedding oxide films in the first and second cavities; a step of forming a gate insulating film on the fourth single crystal semiconductor layer by thermally oxidizing the fourth single crystal semiconductor layer; forming a gate electrode on the fourth single crystal semiconductor layer through the gate insulating film; and performing ion implantation using the gate electrode as a mask, thereby forming A step of forming source/drain layers respectively disposed on sides of the gate electrodes.

Therefore, even when the second and fourth single crystal semiconductor layers are respectively stacked on the first and third single crystal semiconductor layers, the etchant can be brought into contact with the first and third single crystal semiconductor layers through the second groove. semiconductor layer, to remove the 1st and 3rd single crystal semiconductor layer, keep the 2nd and 4th single crystal semiconductor layer, meanwhile, can form the 1st and 1st single crystal semiconductor layer buried under the 2nd and 4th single crystal semiconductor layer respectively 2 Buried oxide film in the cavity. In addition, since the embedded support is formed in the first groove, even when the first and second cavities are respectively formed under the second and fourth single crystal semiconductor layers, the single crystal semiconductor substrate can The second and fourth single crystal semiconductor layers are supported thereon, and the fourth single crystal semiconductor layer can be stably supported by making the film thickness of the fourth single crystal semiconductor layer thicker than that of the second single crystal semiconductor layer.

Therefore, while reducing defects in the second and fourth single crystal semiconductor layers, the second and fourth single crystal semiconductor layers can be disposed on the buried oxide film, and the second single crystal semiconductor layer can be formed without using an SOI substrate. A low-resistance back gate electrode is disposed on the back side of the semiconductor layer, and an SOI transistor can be formed on the second single crystal semiconductor layer. As a result, the cost can be reduced, the leakage current of the SOI transistor at the time of off can be reduced, and a higher withstand voltage of the SOI transistor can be realized.

In addition, the method of manufacturing a semiconductor device according to an embodiment of the present invention is characterized in that the single crystal semiconductor substrate and the second and fourth single crystal semiconductor layers are made of Si, and the first and third single crystal semiconductor layers are made of Si. The crystalline semiconductor layer is SiGe.

Therefore, lattice matching can be realized between the single crystal semiconductor substrate and the first to fourth single crystal semiconductor layers, and the etching rate of the first and third single crystal semiconductor layers can be lower than that of the single crystal semiconductor substrate, the second and the second single crystal semiconductor layers. 4 large single crystal semiconductor layers. Therefore, the second and the fourth single crystal semiconductor layers with excellent crystal quality can be formed respectively on the first and the third single crystal semiconductor layers, so that without affecting the quality of the second and the fourth single crystal semiconductor layers, Insulation between the second and fourth single crystal semiconductor layers and the single crystal semiconductor substrate is realized.

In addition, the method of manufacturing a semiconductor device according to one embodiment of the present invention is characterized in that it includes a step of implanting impurity ions into the second single crystal semiconductor layer, and the travel distance of the impurity is set to be longer than the second single crystal semiconductor layer. A deeper position in the center of the film thickness direction of the second single crystal semiconductor layer.

Therefore, damage to the fourth single crystal semiconductor layer forming the SOI transistor can be suppressed, the resistance of the back gate electrode can be reduced, and the SOI transistor can be applied at a low voltage without deteriorating the characteristics of the SOI transistor. Threshold position for remote control.

Description of drawings

1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention.

2 is a diagram illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

3 is a diagram illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

4 is a diagram illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

5 is a diagram illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

6 is a diagram illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

7 is a diagram illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

8 is a diagram illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

9 is a diagram illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

10 is a diagram illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

11 is a diagram illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

12 is a diagram illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

In the figure: 11, 31 - single crystal semiconductor substrate; 12, 14, 32, 34 - buried oxide film; 13 - first single crystal semiconductor layer; 15a, 15b - second single crystal semiconductor layer; 33, 35, 51 , 52-single crystal semiconductor layer; 16a, 16b, 41-gate insulating film; 17a, 17b, 42-gate electrode; 18a, 18b-side wall; 19a, 19b, 43a-source layer; 20a, 20b, 43b -drain layer; 36, 37, 38-groove; 39-oxide film; 44-interlayer insulating layer; 45-buried insulator; 45a, 45b-back gate contact electrode; 46a-source contact electrode; 46b-drain pole contact electrode; 53-sacrificial oxide film; 54-anti-oxidation film; 56-support body; 57a, 57b-cavities.

Detailed ways

Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention.

In FIG. 1 , a buried oxide film 12 is formed on a single crystal semiconductor substrate 11 , and a first single crystal semiconductor layer 13 constituting a back gate electrode is formed on the buried oxide film 12 . Furthermore, a buried oxide film 14 is formed on the first single crystal semiconductor layer 13 . On the buried oxide film 14, second single crystal semiconductor layers 15a, 15b separated by mesas are stacked. In addition, Si can be used as the material of the single crystal semiconductor substrate 11, the first single crystal semiconductor layer 13, and the second single crystal semiconductor layers 15a, 15b. In addition, it is desirable that the film thickness of the second single crystal semiconductor layers 15 a and 15 b is thicker than the film thickness of the first single crystal semiconductor layer 13 .

Then, on the second single crystal semiconductor layer 15a, a gate electrode 17a is formed via the gate insulating film 16a, and side walls 18a are formed on the side surfaces of the gate electrode 17a. Simultaneously, on the second single crystal semiconductor layer 15a, the source layer 19a and the drain layer 20a arranged to sandwich the gate electrode 17a are formed. In addition, a gate electrode 17b is formed on the second single crystal semiconductor layer 15b via a gate insulating film 16b, and side walls 18b are formed on side surfaces of the gate electrode 17b. In addition, the source layer 19b and the drain layer 20b arranged to sandwich the gate electrode 17b are formed on the second single crystal semiconductor layer 15b.

Accordingly, SOI transistors can be formed on the second single crystal semiconductor layers 15a and 15b, respectively, and a back gate electrode can be arranged on the back side of the SOI transistors. Therefore, the degree of freedom in arranging the back gate electrodes can be increased, and the arrangement of the back gate electrodes can be made independent of the arrangement of the gate electrodes 17a and 17b, source/drain contacts, and the like.

Therefore, the design freedom of the SOI transistor can be improved, and the threshold voltage of the SOI transistor can be controlled by using the bias voltage of the back gate electrode, or its sub-threshold characteristic can be improved by using the double gate structure.

In addition, by disposing the back gate electrode on the back side of the first single crystal semiconductor layer 15a, 15b, the drain potential can be shielded by the back gate electrode. Therefore, even when a drain potential is applied from the surface of the silicon thin film of SOI, it is possible to prevent a high voltage from being generated at the interface between the drain layers 20 a , 20 b and the buried oxide film 14 . As a result, it is possible to prevent a local strong electric field from being generated at the interface between the drain layers 20a, 20b and the buried oxide film 14, thereby achieving a higher breakdown voltage of the SOI transistor.

Moreover, the potential of the active region (active region) of the SOI transistor can be controlled by the back gate electrode, the threshold value control of the SOI transistor can be performed, the rising characteristic of the drain current in the subthreshold region can be improved, and the drain layer 20a, 20b can be relaxed. The electric field at the channel end of the side. Therefore, the SOI transistor can be made to operate in a low voltage state, and the leakage current at the time of off can be reduced. The power consumption during operation or standby can be reduced, and at the same time, the withstand voltage characteristic of the SOI transistor can be improved.

In addition, by making the film thickness of the first single crystal semiconductor layer 13 forming the back gate electrode thicker than the film thickness of the second single crystal semiconductor layers 15a and 15b forming the SOI transistor, the resistance of the back gate electrode can be reduced. Therefore, the threshold position of the SOI transistor can be controlled with a low voltage, the area of the back gate electrode can be increased, the number of contacts connected to the back gate electrode can be reduced, and the increase in chip size can be suppressed.

2(a) to 12(a) are plan views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention. Figure 2(b) to Figure 12(b) are cross-sectional views cut along the A1-A1' line to A11-A11' line in Figure 2(a) to Figure 12(a) respectively, and Figure 2(c) ~ Fig. 12(c) are cross-sectional views cut along the line B1-B1' - line B11-B11' in Fig. 2(a) ~ Fig. 12(a), respectively.

In FIG. 2 , on a single crystal semiconductor substrate 31 , single crystal semiconductor layers 51 , 33 , 52 , and 35 are sequentially stacked by epitaxial growth. Here, the film thickness of the single crystal semiconductor layer 33 may be thicker than the film thickness of the single crystal semiconductor layer 35 . Furthermore, the single crystal semiconductor layers 51 and 52 may use a material whose etching rate is higher than that of the single crystal semiconductor substrate 31 and the single crystal semiconductor layers 33 and 35 . In particular, when the single crystal semiconductor substrate 31 is made of silicon, it is preferable to use SiGe as the material for the single crystal semiconductor layers 51 and 52 , and it is preferable to use Si as the material for the single crystal semiconductor layers 33 and 35 . Therefore, lattice matching can be formed between the single crystal semiconductor layers 51, 52 and the single crystal semiconductor layers 33, 35, and at the same time, the selectivity between the single crystal semiconductor layers 51, 52 and the single crystal semiconductor layers 33, 35 can be ensured. . In addition, the film thickness of the single crystal semiconductor layers 51, 33, 52, and 35 can be set to, for example, about 1 to 100 nm.

Further, a sacrificial oxide film 53 is formed on the surface of the single crystal semiconductor layer 35 by thermal oxidation of the single crystal semiconductor layer 35 . Then, an anti-oxidation film 54 is formed on the entire sacrificial oxide film 53 by CVD or the like. In addition, as the oxidation prevention film 54, for example, a silicon nitride film can be used.

Next, as shown in FIG. 3, the anti-oxidation film 54, the sacrificial oxide film 53, and the single crystal semiconductor layers 35, 52, 33, and 51 are patterned by using photolithography and etching techniques, and the monocrystalline semiconductor layers are formed along a predetermined direction. The groove 36 exposed from the crystalline semiconductor substrate 31. In addition, when the single crystal semiconductor substrate 31 is exposed, the etching of the surface of the single crystal semiconductor substrate 31 may be stopped, or the single crystal semiconductor substrate 31 may be over-etched to form a concave portion in the single crystal semiconductor substrate 31. . Furthermore, the arrangement position of the groove 36 may correspond to a part of the element isolation region of the single crystal semiconductor layer 33 .

Then, the anti-oxidation film 54, the sacrificial oxide film 53, and the single crystal semiconductor layers 35 and 52 are patterned by photolithography and etching to form a groove 37 overlapping with the groove 36 and wider than the groove 36. Here, the arrangement position of the groove 37 may correspond to the element isolation region of the semiconductor layer 35 .

In addition, instead of exposing the surface of the single crystal semiconductor layer 33 , the etching may be stopped on the surface of the single crystal semiconductor layer 52 , or the single crystal semiconductor layer 52 may be overetched to the middle of the single crystal semiconductor layer 52 . Here, by stopping the etching of the single crystal semiconductor layer 52 in the middle, it is possible to prevent the surface of the single crystal semiconductor layer 33 in the groove 36 from being exposed. Therefore, when the single crystal semiconductor layers 51, 52 are etched and removed, the time during which the single crystal semiconductor layer 33 in the groove 36 is exposed to the etching solution or etching gas can be reduced, and the single crystal semiconductor layer 33 in the groove 36 can be prevented from being destroyed. Overetched.

Next, as shown in FIG. 4, a support body 56 is formed on the entire surface of the single crystal semiconductor substrate 31 by CVD or the like, and the support body 56 is filled in the grooves 36, 37 to support the single crystal semiconductor layers 33, 35. on the single crystal semiconductor substrate 31 . Also, a silicon oxide film can be used as the material of the support body 56 .

Next, as shown in FIG. 5, the anti-oxidation film 54, the sacrificial oxide film 53, and the single crystal semiconductor layers 35, 52, 33, and 51 are patterned by using photolithography and etching techniques, so that A direction in which a groove 38 exposing the single crystal semiconductor substrate 31 is formed. Furthermore, when exposing the single crystal semiconductor substrate 31 , etching may be stopped on the surface of the single crystal semiconductor substrate 31 , or recesses may be formed in the single crystal semiconductor substrate 31 by overetching the single crystal semiconductor substrate 31 . In addition, the arrangement position of the groove 38 may correspond to the element isolation region of the single crystal semiconductor layers 33 and 35 .

Next, as shown in FIG. 6 , the single crystal semiconductor layers 51 and 52 are etched and removed by bringing the etchant into contact with the single crystal semiconductor layers 51 and 52 through the groove 38 , so that the single crystal semiconductor substrate 31 and the single crystal semiconductor layer 33 A cavity 57 a is formed between them, and a cavity 57 b is also formed between the single crystal semiconductor layers 33 and 35 .

Here, since the supports 56 are provided in the grooves 36, 37, the semiconductor layers 33, 35 can be supported on the single crystal semiconductor substrate 31 even when the single crystal semiconductor layers 51, 52 are removed, and, since In addition to the grooves 36 and 37, a groove 38 is provided separately so that the single crystal semiconductor layers 51 and 52 arranged under the single crystal semiconductor layers 33 and 35, respectively, can come into contact with the etching solution. Therefore, insulation between the single crystal semiconductor layers 33 , 35 and the single crystal semiconductor substrate 31 can be achieved without affecting the crystal quality of the single crystal semiconductor layers 33 , 35 .

In addition, when the single crystal semiconductor substrate 31 and the single crystal semiconductor layers 33 and 35 are Si materials, and the single crystal semiconductor layers 51 and 52 are SiGe materials, it is preferable to use hydrofluoric acid-nitric acid as the material for the single crystal semiconductor layers 51 and 52. etchant. Therefore, the selectivity ratio of Si and SiGe can be set between 1:100～1000, like this, promptly can remove single crystal semiconductor layer 51,52, can suppress again single crystal semiconductor substrate 31 and single crystal semiconductor layer 33,35 of over-etching.

Next, as shown in FIG. 7 , by thermally oxidizing the single crystal semiconductor substrate 31 and the single crystal semiconductor layers 33 and 35 , a buried oxide layer is formed in the cavity 57 a between the single crystal semiconductor substrate 31 and the single crystal semiconductor layer 33 . film 32, and a buried oxide film 34 is formed in the cavity 57b between the single crystal semiconductor layers 33 and 35 at the same time. Furthermore, when the embedded oxide films 32, 34 are formed by thermal oxidation of the single crystal semiconductor substrate 31 and the single crystal semiconductor layers 33, 35, in order to improve the embedded properties, it is preferable to use a low-temperature wet method that can provide a reaction limit. method of oxidation. Here, when the buried oxide films 32 and 34 are formed by thermal oxidation of the single crystal semiconductor substrate 31 and the single crystal semiconductor layers 33 and 35 , the single crystal semiconductor substrate 31 and the single crystal semiconductor layers 33 and 35 in the groove 38 is oxidized to form an oxide film 39 on the side walls in the trench 38 .

Thus, the thickness of the single crystal semiconductor layers 33 and 35 during epitaxial growth and the thickness of the buried oxide films 32 and 34 formed during thermal oxidation of the single crystal semiconductor layers 33 and 35 can be respectively specified in the device. The film thicknesses of the single crystal semiconductor layers 33 and 35 after isolation. Therefore, the film thickness of the single crystal semiconductor layers 33, 35 can be controlled with high precision, and the single crystal semiconductor layers 33, 35 can be made more compact while reducing the dispersion of the film thickness of the single crystal semiconductor layers 33, 35. Thin. Furthermore, since the oxidation preventing film 54 is provided on the single crystal semiconductor layer 35 , the surface of the single crystal semiconductor layer 35 can be prevented from being thermally oxidized, and the buried oxide film 34 can be formed on the rear side of the single crystal semiconductor layer 35 .

In addition, since the film thickness of the single crystal semiconductor layer 33 is made thicker than that of the single crystal semiconductor layer 35, even when the cavities 57a and 57b are respectively formed under the single crystal semiconductor layers 33 and 35, the single crystal semiconductor layer 33 and 35 are respectively formed. The semiconductor substrate 31 can also stably support the single crystal semiconductor layers 33, 35, and the film thicknesses of the single crystal semiconductor layers 33, 35 and the buried oxide films 32, 34 can be made more uniform.

Next, as shown in FIG. 8, the embedded insulator 45 is deposited on the support body 56 by a method such as CVD, and the groove 38 is filled with it. In addition, a silicon oxide film may be used as the material of the buried insulator 45 .

Next, as shown in FIG. 9, the embedded insulator 45 and the support body 56 are thinned by using CMP (Chemical Mechanical Polishing) or the like, and the anti-oxidation film 54 and the sacrificial oxide film 53 are removed, so that the single crystal semiconductor layer The surface of 35 is exposed. Then, impurities are introduced into the single crystal semiconductor layer 33 by performing ion implantation IP1 of impurities such as As, P, B, and BF ₂ in the single crystal semiconductor layer 33 . Here, the stroke distance Rp of the impurity ion-implanted into the single crystal semiconductor layer 33 is preferably set at a position deeper than the center of the single crystal semiconductor layer 33 in the film thickness direction.

In this way, damage to the single crystal semiconductor layer 35 forming the SOI transistor can be suppressed, and at the same time, the low resistance of the single crystal semiconductor layer 33 that functions as a back gate electrode can be realized, and the SOI transistor can be formed without deteriorating the characteristics of the SOI transistor. Next, a low voltage is used to control the threshold position of the SOI transistor.

Next, as shown in FIG. 10 , a gate insulating film 41 is formed on the surface of the single crystal semiconductor layer 35 by thermally oxidizing the surface of the single crystal semiconductor layer 35 . Then, a polysilicon layer is formed on the single crystal semiconductor layer 35 on which the gate insulating film 41 is formed by a method such as CVD. Then, the polysilicon layer is patterned by using photolithography and etching techniques to form the gate electrode 42 on the single crystal semiconductor layer 35 .

Next, as shown in FIG. 11, ion implantation IP2 of impurities such as As, P, B, and BF ₂ is performed in the single crystal semiconductor layer 35 by using the gate electrode 42 as a mask, thereby forming the The source layer 43a and the drain layer 43b are arranged with the gate electrode 42 sandwiched therebetween.

Next, as shown in FIG. 12 , an interlayer insulating layer 44 is deposited on the gate electrode 42 by a method such as CVD. Then, on the interlayer insulating layer 44, back gate contact electrodes 45a, 45b are formed, which are buried in the interlayer insulating layer 44 and the support body 56, and connected to the single crystal semiconductor layer 33, and, on the interlayer insulating layer 44, A source contact electrode 46a and a drain contact electrode 46b are formed, which are buried in the interlayer insulating layer 44 and connected to the source layer 43a and the drain layer 43b, respectively.

In this way, the occurrence of defects in the single crystal semiconductor layers 33, 35 can be reduced, the single crystal semiconductor layers 33, 35 can be disposed on the buried oxide films 32, 34, and the rear surface of the single crystal semiconductor layer 35 can be formed without using an SOI substrate. A low-resistance back gate electrode is disposed on the side, and an SOI transistor can be formed on the single crystal semiconductor layer 33 . As a result, an increase in cost can be suppressed, a leakage current when the SOI transistor is off can be reduced, and a higher withstand voltage of the SOI transistor can be achieved.

In addition, the gate electrode 42 may be electrically connected to the single crystal semiconductor layer 35 via the back gate contact electrodes 45a and 45b. Therefore, the back gate electrode and the gate electrode 42 can be adjusted to have the same potential, improving the ability to control the potential of the channel region. Therefore, increase in chip size can be suppressed, leakage current at off time can be reduced, power consumption during operation or standby can be reduced, and a high withstand voltage of the field effect transistor can be realized.

Claims (5)

1. semiconductor device has:

The back-gate electrode that constitutes by the 1st single-crystal semiconductor layer that is formed on the 1st insulating barrier;

Be formed on the 2nd insulating barrier on described the 1st single-crystal semiconductor layer;

Be formed on described the 2nd insulating barrier, and the 2nd thin single-crystal semiconductor layer of described the 1st single-crystal semiconductor layer of Film Thickness Ratio;

Be formed on the gate electrode on described the 2nd single-crystal semiconductor layer; With

Be formed on described the 2nd single-crystal semiconductor layer, and be configured in the source of described gate electrode side respectively.

2. semiconductor device according to claim 1 is characterized in that also having:

The wiring layer that described back-gate electrode is electrically connected with described gate electrode.

3. the manufacture method of a semiconductor device comprises:

The operation of film forming the 1st single-crystal semiconductor layer on single crystalline semiconductor substrate;

On described the 1st single-crystal semiconductor layer, the operation of the 2nd single-crystal semiconductor layer that the film forming etch-rate is littler than described the 1st single-crystal semiconductor layer;

On described the 2nd single-crystal semiconductor layer, film forming has the operation with the 3rd single-crystal semiconductor layer of the same composition of described the 1st single-crystal semiconductor layer;

On described the 3rd single-crystal semiconductor layer, film forming has and the same composition of described the 2nd single-crystal semiconductor layer, and the operation of thin the 4th single-crystal semiconductor layer of described the 2nd single-crystal semiconductor layer of Film Thickness Ratio;

Form to connect described the 1st to the 4th single-crystal semiconductor layer, and make the operation of the 1st groove that described single crystalline semiconductor substrate exposes;

In described the 1st groove, form the operation that the described the 2nd and the 4th single-crystal semiconductor layer is supported on the supporter on the described single crystalline semiconductor substrate;

Form the operation of the 2nd groove, the 2nd groove makes at least a portion of the described the 1st and the 3rd single-crystal semiconductor layer that have formed described supporter, exposes from the described the 2nd and the 4th single-crystal semiconductor layer;

By the 1st and the 3rd single-crystal semiconductor layer being carried out selective etch, thereby respectively the described the 1st and the 3rd single-crystal semiconductor layer is removed, formed the operation of the 1st and the 2nd blank part via described the 2nd groove;

By described semiconductor substrate, the described the 2nd and the 4th single-crystal semiconductor layer are carried out thermal oxidation, thereby form the operation of imbedding oxide-film that is embedded in the described the 1st and the 2nd blank part respectively;

By described the 4th single-crystal semiconductor layer is carried out thermal oxidation, thereby on described the 4th single-crystal semiconductor layer, form the operation of gate insulating film;

Across described gate insulating film, on described the 4th single-crystal semiconductor layer, form the operation of gate electrode; With

Inject by described gate electrode is carried out ion as mask, thereby form the operation of the source that is configured in described gate electrode side respectively at described the 4th single-crystal semiconductor layer.

4. the manufacture method of semiconductor device according to claim 3 is characterized in that,

Described single crystalline semiconductor substrate and described the 2nd, the 4th single-crystal semiconductor layer are Si, and the described the 1st and the 3rd single-crystal semiconductor layer is SiGe.

5. according to the manufacture method of claim 3 or 4 described semiconductor devices, it is characterized in that,

Have the operation that foreign ion is injected into described the 2nd single-crystal semiconductor layer, the stroke distances of this impurity is set at the position darker than the central authorities of the film thickness direction of described the 2nd single-crystal semiconductor layer.

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