CN105489546B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The method includes: providing a semiconductor substrate; forming a stack of a first semiconductor layer and a second semiconductor layer on the substrate, and forming the stack Layer isolation structure; forming a device structure on the second semiconductor layer; etching the second semiconductor layer on both sides of the device to form an etching hole; performing etching through the etching hole to remove at least the first semiconductor under the gate of the device structure layer to form a cavity; a dielectric layer is formed on the inner surface of the cavity and the etching hole, and the cavity and the etching hole are filled with a conductor layer. The invention can realize the SOI device through the bulk substrate, form the dielectric layer in the cavity and the etching hole and fill the conductor layer as the back gate, realize the adjustment of the threshold voltage of the device, and the process is simple and easy.

Description

A kind of semiconductor device and its manufacturing method

technical field

The invention belongs to the field of semiconductor manufacturing, and in particular relates to a semiconductor device and a manufacturing method thereof.

Background technique

With the continuous reduction of the feature size of the device, after entering the nanometer scale, especially the size below 22nm, the problems close to the limit of semiconductor physical devices come one after another, such as capacitance loss, leakage current increase, noise promotion, latch-up effect and short channel In order to overcome these problems, SOI (Silicon-On-Insulator, Silicon-On-Insulator) technology came into being.

The SOI substrate is divided into thick layer and thin layer SOI. The thickness of the top layer silicon of the thin layer SOI device is smaller than the width of the maximum depletion layer under the gate. When the thickness of the top layer silicon becomes thinner, the device changes from partially depleted (Partially Depletion) to fully depleted Fully Depletion transition, when the top silicon is less than 50nm, it is ultra-thin SOI (Ultra thin SOI, UTSOI), the SOI device is completely depleted, and the fully depleted device has a large current drive capability, a steep sub-threshold slope, The advantages of smaller short channel, narrow channel effect and complete elimination of Kink effect are especially suitable for high-speed, low-voltage, low-power circuit applications. Ultra-thin SOI has become an ideal solution for processes below 22nm.

However, currently, the cost of SOI substrates is relatively high, and the specifications of the provided SOI substrates are relatively simple, so the thickness of each layer cannot be adjusted according to the needs of the device.

Contents of the invention

The object of the present invention is to overcome the deficiencies in the prior art, and provide a semiconductor device and its manufacturing method, which can realize an SOI device by using a bulk substrate, have adjustable buried oxide thickness, and are easy to form a back gate.

To achieve the above object, the technical solution of the present invention is:

A method of manufacturing a semiconductor device, comprising the steps of:

Provide semiconductor substrates;

forming a stack of the first semiconductor layer and the second semiconductor layer on the substrate, and an isolation structure of the stack is formed in the substrate;

forming a device structure on the second semiconductor layer;

etching the second semiconductor layer on both sides of the device to form etching holes;

removing at least the first semiconductor layer under the gate of the device structure by etching the hole to form a cavity;

A dielectric layer is formed on the inner surface of the cavity and the etching hole, and the cavity and the etching hole are filled with the conductor layer.

Optionally, the step of forming a stack of the first semiconductor layer and the second semiconductor layer on the substrate is specifically:

sequentially epitaxially growing a first semiconductor layer and a second semiconductor layer on a semiconductor substrate;

The first semiconductor layer, the second semiconductor layer and the substrate are patterned and filled to form an isolation structure.

Optionally, the substrate is a silicon substrate, the first semiconductor layer is G _x Si _1-x , where 0<x<1, and the second semiconductor layer is silicon.

Optionally, the step of forming a dielectric layer on the inner surface of the cavity and the etching hole, and filling the cavity and the etching hole with a conductor layer specifically includes:

The ALD process is used to form a dielectric layer on the inner surface of the cavity and the etching hole, and fill the cavity and the etching hole with a conductor layer.

Optionally, the dielectric layer is a high-k dielectric material.

Optionally, the step of forming the cavity specifically includes: removing the first semiconductor layer under the gate of the device structure by etching holes to form a cavity, leaving only the first semiconductor layer near the isolation structure.

Optionally, the first semiconductor layer near the remaining isolation structure and the second semiconductor layer on it are etched to form trenches, and oxides are filled in the trenches.

In addition, the present invention also provides a semiconductor device formed by the above method, including:

semiconductor substrate;

a cavity on a semiconductor substrate and a second semiconductor layer thereon;

a device structure on the second semiconductor layer, the cavity is located at least below a gate of the device structure;

Etching holes through the second semiconductor layer to the cavity;

Wherein, a dielectric layer is formed on the inner surface of the cavity and the etching hole, and the cavity and the etching hole are filled with an interconnected conductor layer.

Optionally, the dielectric layer is a high-k dielectric material.

Optionally, the conductor layer includes a first conductor layer formed on the dielectric layer of the etching hole and filling the cavity, and a second conductor layer formed on the first conductor layer and filling the etching hole.

In the manufacturing method of the semiconductor device of the present invention, the first semiconductor layer and the second semiconductor layer are formed on the substrate, and the device is formed thereon, and then the first semiconductor layer is removed by etching an etching hole in the second semiconductor layer. layer, and refill the dielectric layer and the conductor layer, the SOI device can be realized through the bulk substrate, and the thickness of the second semiconductor layer realizes the control of the channel. In addition, by forming the dielectric layer and filling the conductor layer in the cavity and the etching hole It is used as the back gate to adjust the threshold voltage of the device. The process is simple and easy, and the back gate threshold voltage can be adjusted by changing the thickness and k value of the formed dielectric layer, and the process is highly controllable.

Description of drawings

In order to more clearly illustrate the technical solutions implemented by the present invention, the following will briefly introduce the accompanying drawings that need to be used in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those skilled in the art Ordinary technicians can also obtain other drawings based on these drawings on the premise of not paying creative work.

Fig. 1 shows the flowchart of the manufacturing method of semiconductor device of the present invention;

2-13 are schematic cross-sectional structure diagrams of various manufacturing processes for manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do it without departing from the meaning of the present invention. By analogy, the present invention is therefore not limited to the specific examples disclosed below.

Secondly, the present invention is described in detail in combination with schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, and it should not be limited here. The protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

Referring to Fig. 1, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate; forming a stack of a first semiconductor layer and a second semiconductor layer on the substrate, and forming a semiconductor layer in the substrate The isolation structure of the stack; forming a device structure on the second semiconductor layer; etching the second semiconductor layer on both sides of the device to form an etching hole; performing etching through the etching hole to remove at least the part under the gate of the device structure The first semiconductor layer is used to form a cavity; a dielectric layer is formed on the inner surface of the cavity and the etching hole, and the cavity and the etching hole are filled with the conductor layer.

In the manufacturing method of the present invention, by forming first and second semiconductor layers on a semiconductor substrate, and forming a semiconductor device thereon, and then removing the first semiconductor layer by forming an etching hole in the second semiconductor layer , and re-form the dielectric material and conductor material filling in it, so that silicon-on-insulator devices, especially ETSOI devices, can be realized through the bulk substrate, and the control of the channel can be realized through the thickness of the second semiconductor layer. In addition, through The dielectric layer is formed in the cavity and the etching hole and filled with the conductor layer as the back gate to adjust the threshold voltage of the device. The process is simple and easy, and the back gate can be adjusted by changing the thickness of the formed dielectric layer and the k value Gate threshold voltage adjustment, strong process controllability.

In order to better understand the technical solutions and technical effects of the present invention, a detailed description will be given below in conjunction with the flow chart of the semiconductor device manufacturing method of the present invention FIG. 1 and specific embodiments.

First, in step S01 , a semiconductor substrate 100 is provided, as shown in FIG. 2 .

In the embodiment of the present invention, the semiconductor substrate 100 may be a Si substrate, a Ge substrate or the like. In other embodiments, it may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., and may also be a stacked structure, such as Si/SiGe, etc. In this embodiment, the semiconductor substrate 100 is a bulk silicon substrate.

Then, in step S02, a stack of the first semiconductor layer 102 and the second semiconductor layer 104 is formed on the substrate 100, and the isolation structure 106 of the stack is formed in the substrate 100, as shown in FIGS. 2-3 Show.

In this embodiment, an epitaxial growth (EPI) process may be used. As shown in FIG. The layer can be G _x Si _1-x , where 0<x<1, and the thickness can be 1-200nm, typically 10nm or 200nm; the second semiconductor layer can be silicon, and the thickness can be 3-200nm, typically Can be 10nm or 15nm. The epitaxial process can form a semiconductor layer of crystalline structure, which is a higher quality semiconductor layer, so as to improve the performance of the formed device. After the epitaxial formation of the first and second semiconductor layers, the first semiconductor layer 102, the second semiconductor layer 104 and the substrate 100 can be etched and filled with a dielectric material such as silicon oxide, thereby forming an isolation structure 106 and isolating The second semiconductor layer between the structures 106 is the active region of the device, as shown in FIG. 3 . Of course, other methods can be used to form the second semiconductor layer according to the specific requirements of the device.

In the present invention, the thickness of the second semiconductor layer can be selected according to the needs of the device, and its thickness determines the thickness of the channel for subsequent formation of the device structure, which is equivalent to the role of the top layer silicon in the SOI substrate. When the thickness of the layer is less than 50nm, it can be used to form UTSOI devices.

Next, in step S03 , a device structure 110 is formed on the second semiconductor layer 104 , as shown in FIG. 3 .

The device structure 110 can be formed according to a conventional process, and a gate-first or gate-last process can be used. In this embodiment, the gate-last process is used to form the device structure. First, a gate dielectric layer, a dummy gate (not shown) and its sidewalls are formed on the second semiconductor layer 104. The gate dielectric layer may be a thermal oxide layer. Or other suitable dielectric materials, such as silicon oxide, silicon nitride, etc., in one embodiment, may be silicon dioxide, which may be formed by thermal oxidation. The dummy gate can be amorphous silicon, polysilicon or silicon oxide, etc., and in one embodiment, it can be amorphous silicon. The sidewall 114 can have a single-layer or multi-layer structure, and can be made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluoride-doped silicon glass, low-k dielectric materials and combinations thereof, and/or other suitable materials In one embodiment, the spacer 114 may be a two-layer structure of silicon nitride and silicon oxide.

Then, source and drain regions are formed on both sides of the dummy gate. In one embodiment, silicon source and drain regions 116 are formed on the second semiconductor layer 104 by epitaxial doping. Of course, the source and drain regions can also be formed in the second semiconductor layer by ion implantation.

Next, cover the interlayer dielectric layer on both sides of the dummy gate and remove the dummy gate and the gate dielectric layer by wet etching, and re-form the gate dielectric layer and the gate 112. The gate dielectric layer can be a high-k dielectric material (for example, Compared with silicon oxide, a material with a high dielectric constant) or other suitable dielectric materials, high-k dielectric materials such as hafnium-based oxides, the gate can be a metal gate electrode can be a one-layer or multi-layer structure, and can include Metal material or polysilicon or their combination, metal material such as Ti, TiAl _x , TiN, TaN _x , HfN, TiC _x , TaC _x and so on.

Thus, a device structure is formed on the second semiconductor layer. Referring to FIG. 3 , the embodiment of forming the device structure here is only an example, and any desired device structure can be formed as required.

Then, in step S04 , the second semiconductor layer 104 on both sides of the device is etched to form etching holes 124 , as shown in FIG. 5 .

After the device structure is formed, continue to cover the interlayer dielectric layer 120 on the device, as shown in FIG. 4 . In the present invention, the etching hole 124 is formed before the step of forming the contact hole. In this embodiment, the etching hole is formed above the source and drain regions and in the second semiconductor layer on both sides of the gate. Specifically, a first mask layer 122 is formed on the interlayer dielectric layer 120, as shown in FIG. The second semiconductor layer 104 and the first semiconductor layer 102 may further over-etch part of the substrate 100 to form an etching hole 124, as shown in FIG. 5 . In other embodiments, when forming the etching hole, etching can also be performed from the interlayer dielectric layer 120 until the first semiconductor layer is exposed, that is, the first semiconductor layer 102 is not etched, but is subsequently removed. The first semiconductor layer is removed together in the step of forming the cavity.

Next, in step S05 , at least the first semiconductor layer 102 under the gate 112 of the device structure is removed by etching the hole 124 to form a cavity 130 , as shown in FIGS. 6 and 7 .

In one embodiment, wet etching can be carried out, for example, using the etching method of HF (49%):H ₂ O ₂ (30%):CH ₃ COOH (99.8%):H ₂ O=1:18:27:8 etchant, set the etching time according to the etching rate, so that after etching, only the first semiconductor layer 102 near the isolation structure 106 remains, as shown in FIG. . In this embodiment, wet etching may also be used to completely remove the first semiconductor layer 102 to form a cavity 130 , as shown in FIG. 7 .

Then, a dielectric layer 131 is formed on the inner surfaces of the cavity 130 and the etching hole 124, and the cavity 130 and the etching hole 124 are filled with conductor layers 132, 133 to form back gates 131, 132 and connection holes 133. Figure 9 shows.

In this embodiment, first, as shown in FIG. 8, the dielectric layer 131 can be deposited by ALD (atomic layer deposition) process, and the dielectric layer can be a high-k dielectric material, a dielectric material such as oxide or nitride; Next, the deposition of the conductor layer is carried out, and the material and structure of the conductor layer are determined according to the thickness of the cavity, the width of the etching hole and the needs of the device. In this embodiment, the deposition of the first conductor layer 132 is carried out first, The ALD process can be used, and the material can be TIN, TaN or TiAl, etc., the first conductor layer 132 fills the cavity and is simultaneously formed on the dielectric layer on the inner surface of the etching hole 124, as shown in FIG. 8; and then , depositing the second conductor layer 133 to fill the etching hole, and performing planarization until the interlayer dielectric layer 120 is exposed, as shown in FIG. 9 . Therefore, a back gate is formed in the cavity under the gate, and a bias voltage can be applied through the connection hole formed by etching the conductor in the hole, thereby adjusting the threshold voltage of the back gate. In a specific device, the threshold voltage of the back gate can be adjusted by changing the thickness of the formed dielectric layer and the k value, and the process is highly controllable.

In other embodiments, other methods may be used to fill the cavity, for example, a thermal oxidation method may be used to oxidize, so that an oxide is formed on the inner surface of the etching hole and the cavity, and then, the conductor layer is filled.

Then, more preferably, for this embodiment and the embodiment of the remaining first semiconductor layer near the isolation structure (refer to FIG. 6 ), an isolation trench can be re-formed between the isolation and the back gate, and the cavity near the isolation trench and its filling material are removed to avoid device leakage caused by the residue of the first semiconductor layer at the edge of the cavity. Specifically, a second mask layer 135 is formed on the interlayer dielectric layer, and the interlayer dielectric layer 120, the source and drain regions 116, the second semiconductor layer 104, and part of the isolation structure 106 are etched under the cover of the second mask layer 135. and the cavity near the isolation structure and the filling in the cavity to form a trench 134, so that the first semiconductor layer 102 near the isolation structure is further removed, as shown in FIG. 10; then, the trench is oxidized The dielectric material 136 of the object is filled, such as silicon oxide, etc., and the second mask layer 135 is removed, as shown in FIG. 11 .

Then, other necessary processes can be performed.

A third mask layer 140 can be formed on the interlayer dielectric layer 120 according to a conventional process, and under the mask of the third mask layer 140, etching of the interlayer dielectric layer is performed to form a contact hole 142, referring to FIG. 12 shown; then, fill with metal material and planarize until the interlayer dielectric layer 120 is exposed to form source-drain contacts 144 and gate contacts (not shown), as shown in FIG. 13 .

So far, the semiconductor device according to the manufacturing method of the present invention is formed. 7 and 13, the semiconductor device includes: a semiconductor substrate 100; a cavity 130 on the semiconductor substrate and a second semiconductor layer 104 thereon; a device structure 110 on the second semiconductor layer, the cavity The cavity is located at least below the gate 112 of the device structure; the etching hole 124 penetrates the second semiconductor layer to the cavity; wherein, a dielectric layer 131 is formed on the inner surface of the cavity and the etching hole, and the cavity and the etching hole The holes are filled with interconnected conductor layers 132 , 133 .

In the semiconductor device of the present invention, the source-drain contact 144 is formed on the source-drain region 116 on the side of the etched hole.

In an embodiment of the present invention, the back gate formed by the cavity is formed under the entire device, that is, the back gate is formed under the second semiconductor layer, and the dielectric layer is a high-k dielectric material.

The conductor layer includes a first conductor layer 131 formed on the dielectric layer of the etching hole and filling the cavity, and a second conductor layer 132 formed on the first conductor layer and filling the etching hole.

In an embodiment of the present invention, as shown in FIG. 13 , the first isolation 106 of the second semiconductor layer is formed on the substrate, and the first isolation 106 is formed on the substrate between the first isolation and the back gate 131, 132. A second isolation 136, the second isolation penetrates the interlayer dielectric layer into the substrate.

In the semiconductor device of the present invention, a cavity is formed under the gate, and a dielectric layer is formed in the cavity and an etching hole and a conductive layer is filled as a back gate to realize adjustment of the threshold voltage of the device. The process is simple and easy, Moreover, the threshold voltage of the back gate can be adjusted by changing the thickness of the formed dielectric layer and the k value, and the process is highly controllable.

The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (8)

1. A method for manufacturing a semiconductor device, comprising the steps of: Provide semiconductor substrates; forming a stack of the first semiconductor layer and the second semiconductor layer on the substrate, and forming an isolation structure of the stack in the substrate; forming a device structure on the second semiconductor layer; etching the second semiconductor layer on both sides of the device to form etching holes; removing at least the first semiconductor layer under the gate of the device structure by etching the hole to form a cavity; forming a dielectric layer on the inner surface of the cavity and the etching hole, and filling the cavity and the etching hole with a conductor layer; The step of forming the cavity specifically includes: removing the first semiconductor layer under the gate of the device structure by etching the hole to form a cavity, leaving only the first semiconductor layer near the isolation structure; Etching the remaining first semiconductor layer near the isolation structure and the second semiconductor layer thereon to form a trench, and filling the trench with oxide. 2. The manufacturing method according to claim 1, wherein a stack of the first semiconductor layer and the second semiconductor layer is formed on the substrate, and the step of forming the isolation structure of the stack in the substrate is specifically for: sequentially epitaxially growing a first semiconductor layer and a second semiconductor layer on a semiconductor substrate; The first semiconductor layer, the second semiconductor layer and the substrate are patterned and filled to form an isolation structure. 3. The manufacturing method according to claim 2, wherein the substrate is a silicon substrate, the first semiconductor layer is Ge _x Si _1-x , where 0<x<1, and the second The semiconductor layer is silicon. 4. The manufacturing method according to claim 1, wherein the step of forming a dielectric layer on the inner surface of the cavity and the etching hole, and filling the cavity and the etching hole with the conductor layer specifically comprises: The ALD process is used to form a dielectric layer on the inner surface of the cavity and the etching hole, and fill the cavity and the etching hole with a conductor layer. 5. The manufacturing method according to claim 1, wherein the dielectric layer is a high-k dielectric material. 6. A semiconductor device, characterized in that, comprising: semiconductor substrate; a cavity on a semiconductor substrate and a second semiconductor layer thereon; a device structure on the second semiconductor layer, the cavity is located at least below a gate of the device structure; Etching holes through the second semiconductor layer to the cavity; Wherein, a dielectric layer is formed on the inner surface of the cavity and the etching hole, and the cavity and the etching hole are filled with an interconnected conductor layer; A first isolation of the second semiconductor layer is formed on the substrate and a second isolation is formed on the substrate between the first isolation and the back gate, and the second isolation penetrates the interlayer dielectric layer to the substrate middle. 7. The semiconductor device according to claim 6, wherein the dielectric layer is a high-k dielectric material. 8. The semiconductor device according to claim 6, wherein the conductor layer comprises a first conductor layer formed on the dielectric layer of the etched hole and filling the cavity, and a first conductor layer formed on the first conductor layer The second conductor layer that fills the etched hole.