CN108305835A - Method for manufacturing fin type transistor device - Google Patents

Abstract

The invention provides a method for manufacturing a fin-type transistor device. A first epitaxial layer is epitaxially grown on a substrate, and then a second epitaxial layer is epitaxially grown on the first epitaxial layer, and then the second epitaxial layer is etched to form a fin. Since the first epitaxial layer has different materials from the second epitaxial layer, the two have etching selectivity. In the etching process of forming the fin, the first epitaxial layer is used as an etching stop layer, so that the formed The fins are all stopped on the first epitaxial layer, and the etching depth is effectively controlled, so that the height of the fins is controllable, thereby improving the uniformity of the fins.

Description

A method of manufacturing a fin transistor device

technical field

The invention relates to the field of semiconductor devices and their manufacture, in particular to a method for manufacturing a fin transistor device.

Background technique

With the continuous development of integrated circuit technology, the feature size of devices continues to decrease and the integration level continues to increase. As the short channel effect becomes more and more significant, it becomes the dominant factor affecting device performance. It is difficult for traditional planar devices to continue to reduce size.

At present, the three-dimensional device structure of the fin transistor device (FIN-FET) is proposed. The short channel effect can increase the working current at the same time.

In the formation process of fin-type transistor devices, the fins are formed by etching the substrate, and as the density of the fins increases, the etching process becomes more and more difficult to control, resulting in the difficulty of controlling the height of the fins after etching. There is non-uniformity in the height of the fins, making the leakage current between the fins uncontrollable.

Contents of the invention

In view of this, the object of the present invention is to provide a method for manufacturing a fin transistor device, which can effectively control the height of the fin and improve the uniformity of the fin.

To achieve the above object, the present invention has the following technical solutions:

A method of manufacturing a fin transistor device, comprising:

Provide semiconductor substrates;

epitaxially growing a first epitaxial layer of semiconductor material on said semiconductor substrate;

epitaxially growing a second epitaxial layer of semiconductor material on the first epitaxial layer, the first epitaxial layer having a different material than the second epitaxial layer;

using the first epitaxial layer as an etching stop layer, etching the second epitaxial layer to form fins;

An isolation structure is formed between the fins, and a gate is formed on the fins.

Optionally, after forming the fins and before forming the isolation structure, further comprising:

removing the first epitaxial layer on both sides of the fin;

The first epitaxial layer under the fin is oxidized to a buried oxide layer.

Optionally, oxidizing the first epitaxial layer under the fins to a buried oxide layer includes:

forming a protective layer on sidewalls of the fin;

performing an oxidation process, forming a surface oxide layer on the surface of the fin and the exposed substrate surface, and oxidizing the first epitaxial layer under the fin into a buried oxide layer;

removing the surface oxide layer and the protection layer.

Optionally, the thickness of the first epitaxial layer is 2-20 nanometers.

Optionally, the thickness of the second epitaxial layer is 50-500 nanometers.

Optionally, the semiconductor substrate and the second epitaxial layer have the same material.

Optionally, the semiconductor substrate is a silicon substrate, the second epitaxial layer is epitaxial silicon, and the first epitaxial layer is silicon germanium.

Optionally, forming a gate on the fin includes:

forming a dummy gate on the fin in the middle of the fin;

forming sidewalls on sidewalls of the dummy gate;

forming source and drain regions in the fins on both sides of the dummy gate;

forming an interlayer dielectric layer covering the fins on both sides of the dummy gate;

removing dummy gates to form openings;

A replacement gate is formed in the opening.

Optionally, the replacement gate includes a high-k dielectric material and a metal gate electrode thereon.

In the method for manufacturing a fin transistor device provided by an embodiment of the present invention, a first epitaxial layer is epitaxially grown on a substrate, and then a second epitaxial layer is epitaxially grown on the first epitaxial layer, and then, the second epitaxial layer is etched to form a fin . Since the first epitaxial layer has different materials from the second epitaxial layer, the two have etching selectivity. In the etching process of forming the fin, the first epitaxial layer is used as an etching stop layer, so that the formed The fins are all stopped on the first epitaxial layer, and the etching depth is effectively controlled, so that the height of the fins is controllable, thereby improving the uniformity of the fins.

Further, the first epitaxial layer can be further etched to form a buried oxide layer between the fin and the substrate, so as to form a fully depleted ETSOI fin transistor device and improve the performance of the device

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present invention, those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 shows a flowchart of a method for manufacturing a fin transistor device according to an embodiment of the present invention;

2-8 are schematic cross-sectional diagrams illustrating device structures during the process of forming a fin transistor device according to a method according to an embodiment of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do it without departing from the meaning of the present invention. By analogy, the present invention is therefore not limited to the specific examples disclosed below.

Secondly, the present invention is described in detail in combination with schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, and it should not be limited here. The protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

As described in the background art, in the formation process of fin-type transistor devices, fins are formed by etching the substrate, and as the density of fins continues to increase, the etching process is becoming more and more difficult to control, resulting in etching The height of the rear fin is not easy to control, and there is non-uniformity in the height of the fins, which makes the leakage current between the fins uncontrollable.

For this reason, the present application proposes a manufacturing method of a fin-type transistor device, in which a first epitaxial layer is epitaxially grown on a substrate, and then a second epitaxial layer is epitaxially grown on the first epitaxial layer, and then, the second epitaxial layer is etched. , forming fins. Since the first epitaxial layer has different materials from the second epitaxial layer, the two have etching selectivity. In the etching process of forming the fin, the first epitaxial layer is used as an etching stop layer, so that the formed The fins are all stopped on the first epitaxial layer, and the etching depth is effectively controlled, so that the height of the fins is controllable, thereby improving the uniformity of the fins.

In order to better understand the technical solutions and technical effects of the present application, the specific embodiments will be described in detail below in conjunction with the flow chart Figure 1 and accompanying drawings 2-8, wherein accompanying drawings 2-8 are devices in each manufacturing process Schematic cross-section along the width of the fin.

Referring to FIG. 1 , in step S01 , a semiconductor substrate 100 is provided, as shown in FIG. 2 .

In the embodiment of the present invention, the semiconductor substrate 100 may be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator, Silicon On Insulator) or GOI (Germanium On Insulator, Germanium On Insulator) and the like. In other embodiments, the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., or a stacked structure, such as Si/SiGe, etc., or other epitaxial Structures, such as SGOI (silicon germanium on insulator), etc.

In this embodiment, the semiconductor substrate 100 is a bulk silicon substrate, as shown in FIG. 2 .

In step S02 , a first epitaxial layer 110 of semiconductor material is epitaxially grown on the semiconductor substrate 100 , as shown in FIG. 3 .

In step S03 , a second epitaxial layer 120 of semiconductor material is epitaxially grown on the first epitaxial layer 110 , and the first epitaxial layer 110 has a material different from that of the second epitaxial layer 120 , as shown in FIG. 3 .

In the embodiment of the present invention, the second epitaxial layer is used to form fins, and the first epitaxial layer is an etching stop layer when etching the second epitaxial layer to form fins, and both the first epitaxial layer and the second epitaxial layer can be grown by epitaxy process (EPI) to ensure that the formed second epitaxial layer has a better crystal orientation and can form high-quality fins. The first epitaxial layer 110 and the second epitaxial layer 120 are made of different semiconductor materials, so that there is etching selectivity between them.

In a specific application, according to different substrate materials, the first and second epitaxial layers of suitable materials can be selected and grown, so that the second epitaxial layer can be used as a fin formation, and the first epitaxial layer can be used as an etching stop layer. Their thicknesses can be set according to specific needs. In some applications, the thickness of the first epitaxial layer can be in the range of about 2-20 nm, and the thickness of the second epitaxial layer can be in the range of about 50-500 nm.

In this embodiment, the first epitaxial layer 110 is epitaxial silicon germanium (G _x S _1-x , 0<x<1), the second epitaxial layer 120 is epitaxial silicon, and silicon germanium and silicon have close The crystal orientation facilitates the formation of better-quality epitaxial silicon for the formation of fins, and has better etching selectivity with silicon.

In step S04 , using the first epitaxial layer 110 as an etching stop layer, the second epitaxial layer 120 is etched to form fins 122 , as shown in FIG. 4 .

In the process of etching the second epitaxial layer 120, the first epitaxial layer is used as an etching stop layer, that is, the etching of the second epitaxial layer stops on the first epitaxial layer, so that the height of the formed fin The thickness of the second epitaxial layer is basically the thickness of the second epitaxial layer, which effectively controls the etching depth, so that the height of the fin can be controlled, thereby improving the uniformity of the fin.

In a specific application, a mask layer (not shown) can be formed on the second epitaxial layer 120 first, and anisotropic etching, for example, RIE (reactive ion etching) can be used to perform the second epitaxial layer 120. The etching of layer 120 stops when the first epitaxial layer is etched.

In a more preferred embodiment, the second epitaxial layer 120 can also be further etched to form an oxide layer between the fin and the substrate, thereby forming a buried oxide layer so as to form a fully depleted epitaxial layer. ETSOI (eltra thin Siliconon insulator) fin transistor device improves device performance.

In this preferred embodiment, the thickness of the first epitaxial layer 110 can be 2-20 nm, more preferably, it can be 2-5 nm, and the step of forming the buried oxide layer can include:

First, remove the first epitaxial layer 120 on both sides of the fin 122 as shown in FIG. 5 .

The first epitaxial layer 120 on both sides of the fin 122 may be removed by dry or wet etching, leaving only the first epitaxial layer 112 under the fin 120 .

In this embodiment, the first epitaxial layer 120 of SiGe on both sides of the fin 122 may be removed by using an acetic acid mixed solution.

Then, the first epitaxial layer 112 under the fin 122 is oxidized into the buried oxide layer 114 , as shown in FIG. 6 .

An oxidation process may be performed first, and after the oxidation, the first epitaxial layer under the fin is completely oxidized to form a buried oxide layer, and at the same time, the surface of the fin and the exposed substrate surface are also oxidized to form a surface oxide layer. Afterwards, the surface oxide layer may be removed by rinsing with an acid solution, such as hydrofluoric acid, thereby forming the buried oxide layer 112 between the fin 122 and the substrate 100 . By controlling the thickness of the first epitaxial layer and the oxidation time, a sufficiently thin buried oxide layer 122 can be formed to facilitate the formation of a fully depleted ETSOI (eltra thin Silicon on insulator) fin transistor device and improve device performance.

More preferably, before performing the oxidation process, a protective layer can be formed on the sidewall of the fin. In this embodiment, a protective layer of silicon nitride can be deposited by CVD, and then dry-etched to separate the top and bottom The silicon nitride protective layer is only formed on the sidewall of the fin, so that the subsequent oxidation process does not consume the sidewall of the fin. After the oxidation process, the protective layer can be removed with hot phosphoric acid.

So far, the fin of the embodiment of the present invention has been formed. The height of the fin formed by this method is controllable, the uniformity of the fin is good, and an ultra-thin buried oxide layer can be formed. After that, an appropriate process can be selected according to the needs Other device structures are formed on the fins.

In step S05 , an isolation structure 130 is formed between the fins 122 , and gates 140 and 142 are formed on the fins 122 , as shown in FIG. 8 .

The isolation structure 130 separates the isolation material from the fin hook, which may be silicon oxide in this embodiment.

The gate includes a gate dielectric layer 140 and a gate electrode 142, and the gate dielectric layer 140 can be silicon oxide or a high-k gate dielectric material (for example, a material with a high dielectric constant compared with silicon oxide) or other suitable dielectric materials , High-k dielectric materials such as hafnium-based oxides, HFO2, HfSiO, HfSiON, HfTaO, HfTiO, etc. The gate electrode 142 can be a metal gate electrode, can be a one-layer or multi-layer structure, can include metal materials or polysilicon or their combination, metal materials such as Ti, TiAl _x , TiN, TaN _x , HfN, TiC _x , TaC _x , etc. .

In this embodiment, a silicon dioxide-filled isolation material (not shown in the figure) can be used to perform chemical mechanical planarization; then, a certain thickness of the isolation material can be removed by hydrofluoric acid etching, and a part of the isolation material remains in the Between the fins, an isolation structure 130 is formed, as shown in FIG. 7 .

In this embodiment, the gate may be formed by a gate-last process, specifically, the following steps are included.

First, a dummy gate on the fin is formed in the middle of the fin.

The dummy gate may include a dummy dielectric layer and a dummy gate, and the region where the dummy gate is located is the gate region of the final device. The dummy gate can be formed by sequentially depositing a dummy dielectric layer and a dummy gate. The dummy dielectric layer can be, for example, silicon oxide, and the dummy gate can be, for example, polysilicon, and then patterned by using an etching technique.

Then, sidewalls are formed on the sidewalls of the dummy gates.

The sidewall can be a single-layer or multi-layer structure, and can be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluoride-doped silicon glass, low-k dielectric materials and combinations thereof, and/or other suitable materials . The sidewall can be formed by depositing the sidewall material and then performing an anisotropic etching process.

Next, source and drain regions are formed in the fins on both sides of the dummy gate.

The source and drain regions can be formed by ion implantation or other suitable methods. In order to improve the mobility of carriers in the channel region of the device, epitaxy is used to grow the source and drain regions with stress.

When forming the source and drain regions with stress, specifically, firstly, an etching process, such as a dry etching process, may be used to form recessed regions on the fins on both sides of the dummy gate. Then, through a selective epitaxial growth process, a source and drain region with stress is formed in the recessed region, wherein, for a PMOS device, the material of the source and drain region provides compressive stress, and for an NMOS device, the material of the source and drain region provides Tensile stress. In this embodiment, the fin is made of epitaxial silicon material. For NMOS devices, the source and drain regions can be SiC; for PMOS devices, the source and drain regions can be SiGe, Ge, GeSn or III-V materials.

Then, an interlayer dielectric layer covering the fins on both sides of the dummy gate is formed.

Dielectric materials can be deposited by suitable deposition methods, such as undoped silicon oxide (SiO ₂ ), doped silicon oxide (such as borosilicate glass, borophosphosilicate glass, etc.), silicon nitride (Si ₃ N ₄ ) or other low-k dielectric materials, and then planarized, such as CMP (Chemical Mechanical Polishing), to form an interlayer dielectric layer.

Then, the dummy gate is removed to form an opening.

The dummy gate can be removed using wet etch and/or dry etch, thereby forming an opening exposing the fin in the area of the original dummy gate

Finally, a replacement gate is formed in the opening.

A gate dielectric layer of a high-k dielectric material can be formed by using a suitable deposition technique, and then the opening is filled to form a metal gate electrode with a one-layer or multi-layer structure.

So far, the fin transistor device of the embodiment of the present invention is formed.

The above descriptions are only preferred implementations of the present invention. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent of equivalent change Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (9)

1. A method for manufacturing a fin transistor device, comprising: Provide semiconductor substrates; epitaxially growing a first epitaxial layer of semiconductor material on said semiconductor substrate; epitaxially growing a second epitaxial layer of semiconductor material on the first epitaxial layer, the first epitaxial layer having a different material than the second epitaxial layer; using the first epitaxial layer as an etching stop layer, etching the second epitaxial layer to form fins; An isolation structure is formed between the fins, and a gate is formed on the fins. 2. The manufacturing method according to claim 1, further comprising: after forming the fins and before forming the isolation structure: removing the first epitaxial layer on both sides of the fin; The first epitaxial layer under the fin is oxidized to a buried oxide layer. 3. The manufacturing method according to claim 2, wherein oxidizing the first epitaxial layer under the fin into a buried oxide layer comprises: forming a protective layer on sidewalls of the fin; performing an oxidation process, forming a surface oxide layer on the surface of the fin and the exposed substrate surface, and oxidizing the first epitaxial layer under the fin into a buried oxide layer; removing the surface oxide layer and the protection layer. 4. The manufacturing method according to any one of claims 1-3, characterized in that, the thickness of the first epitaxial layer is 2-20 nanometers. 5. The manufacturing method according to any one of claims 1-3, characterized in that, the thickness of the second epitaxial layer is 50-500 nanometers. 6. The manufacturing method according to any one of claims 1-3, wherein the semiconductor substrate and the second epitaxial layer have the same material. 7. The manufacturing method according to claim 6, wherein the semiconductor substrate is a silicon substrate, the second epitaxial layer is epitaxial silicon, and the first epitaxial layer is silicon germanium. 8. The manufacturing method according to claim 1, wherein forming a gate on the fin comprises: forming a dummy gate on the fin in the middle of the fin; forming sidewalls on sidewalls of the dummy gate; forming source and drain regions in the fins on both sides of the dummy gate; forming an interlayer dielectric layer covering the fins on both sides of the dummy gate; removing dummy gates to form openings; A replacement gate is formed in the opening. 9. The manufacturing method according to claim 8, wherein the replacement gate comprises a high-k dielectric material and a metal gate electrode thereon.