CN105489610A - Thin-film transistor array substrate, display panel and display device - Google Patents

Abstract

A thin film transistor array substrate, comprising a plurality of scanning lines, a plurality of data lines, a plurality of TFTs and a plurality of pixel electrodes arranged on a base substrate, and each pixel electrode is connected to a corresponding scanning line and data line through a TFT; The thin film transistor array substrate has a double scan line pixel array structure, and each of the multiple data lines is divided into a plurality of first scan segments connected to TFTs and a plurality of first scan segments not connected to TFTs. The second scanning segment, the first scanning segment and the second scanning segment are located between two adjacent data lines, the first scanning segment and the second scanning segment on each scanning line alternate along the length direction of the scanning line distribution, the line width of the second scan segment is smaller than the line width of the first scan segment. The present invention can relatively increase the area of the pixel electrode and increase the aperture ratio of the pixel by reducing the line width of the second scanning segment. The invention also provides a display panel and a display device with the thin film transistor array substrate.

Description

Thin film transistor array substrate, display panel and display device

technical field

The invention relates to the field of display technology, in particular to a thin film transistor array substrate, a display panel and a display device having the thin film transistor array substrate.

Background technique

With the development of large-sized display panels, there is a so-called half source driving (HSD) structure in the pixel array of the array substrate. In the pixel array of the HSD structure, two columns of adjacent pixels share one data line, which can halve the number of data lines. For display panels, driver chips including gate driver chips (gate driver) and source driver chips (source driver) are essential, and source driver chips are more expensive than gate driver chips due to their complex structure, while gate driver chips are more expensive than gate driver chips. Since the HSD architecture can halve the number of data lines, the cost of the source driver chip can be reduced.

Although the display panel adopting the HSD architecture can halve the number of driving channels of the source driver chip, since the odd-numbered pixels and even-numbered pixels in the same row of pixels are respectively connected to different scanning lines, the number of scanning lines in the HSD architecture Therefore, the pixel array of the HSD architecture is also called a double-scanning line pixel array.

FIG. 1 is a schematic plan view of an existing array substrate. FIG. 2 is an equivalent circuit diagram of the array substrate in FIG. 1. Please refer to FIGS. A plurality of data lines 12, a plurality of TFTs 13 and a plurality of pixel electrodes 14, each pixel electrode 14 is connected to a corresponding scanning line 11 and a data line 12 through a TFT 13, and every two adjacent pixel electrodes 14 in the same row of pixel electrodes are respectively It is connected to the upper and lower scanning lines 11 of the row of pixel electrodes through TFT13.

In order to ensure the normal manufacturing process of each TFT13, the gate metal layer of each TFT13 needs to ensure a certain line width, so that the line width of the entire scanning line 11 is the same as the line width of the gate metal layer of TFT13, and the scanning line 11 occupies an area Larger, resulting in a low aperture ratio of the pixel, affecting the optical characteristics of the display panel.

Contents of the invention

The object of the present invention is to provide a thin-film transistor array substrate, and a display panel and a display device having the thin-film transistor array substrate, so as to solve the problem that the scanning line occupies a large area and the pixel opening is large in the double-scanning line pixel array structure of the existing array substrate. low rate problem.

The present invention provides a thin film transistor array substrate, which includes a plurality of scanning lines, a plurality of data lines, a plurality of TFTs and a plurality of pixel electrodes arranged on the base substrate, and each pixel electrode is connected to the corresponding scanning line and data through the TFT. Lines are connected; two columns of pixel electrodes are arranged between two adjacent data lines, and each data line is connected to two columns of pixel electrodes located on both sides of the data line; between two adjacent data lines, located in the same row The two pixel electrodes of the same row are connected to the same scanning line; the pixel electrodes of the same row are alternately connected to the two scanning lines on the upper and lower sides of the row of pixel electrodes respectively; Each of the plurality of scanning lines is divided into a plurality of first scanning segments connected with TFTs and a plurality of second scanning segments not connected with TFTs, and the first scanning segments and the second scanning segments are located at two Between adjacent data lines, the first scanning segment and the second scanning segment on each scanning line are alternately distributed along the length direction of the scanning line, and the line width of the second scanning segment is smaller than the line width of the first scanning segment; Two adjacent scanning lines are arranged between the pixel electrodes of the upper and lower adjacent rows, and the two adjacent scanning lines are respectively connected with the pixel electrodes of the upper and lower adjacent rows. The scan segments are alternately distributed along the length direction of the scan lines, and the second scan segments on the two adjacent scan lines are also alternately distributed along the length direction of the scan lines.

Further, among the pixel electrodes in the same row, the odd-numbered pixel electrode groups are connected to the scanning lines on the lower side of the row of pixel electrodes, and the even-numbered pixel electrode groups are connected to the scanning lines on the upper side of the row of pixel electrodes, wherein each A pixel electrode group includes two pixel electrodes located in the same row between two adjacent data lines.

Further, among the pixel electrodes in the same row, the even-numbered pixel electrode groups are connected to the scanning lines on the lower side of the row of pixel electrodes, and the odd-numbered pixel electrode groups are connected to the scanning lines on the upper side of the row of pixel electrodes, wherein each A pixel electrode group includes two pixel electrodes located in the same row between two adjacent data lines.

Further, the line width of the second scanning segment is one-third of the line width of the first scanning segment.

Further, the gate metal layer of each TFT is connected to the corresponding scan line, the source metal layer of each TFT is connected to the corresponding data line, and the drain metal layer of each TFT is connected to the corresponding pixel electrode.

Further, the thin film transistor array substrate also includes a passivation protection layer covering the source metal layer and the drain metal layer of each TFT, the passivation protection layer is provided with a through hole, and the drain metal layer of each TFT The layer is connected to the corresponding pixel electrode through the through hole.

Further, the line width of the first scanning segment is the same as the width of the gate metal layer of each TFT.

The present invention also provides a display panel, including the above thin film transistor array substrate.

The present invention also provides a display device, including the above-mentioned display panel.

The thin film transistor array substrate provided by the present invention, the thin film transistor array substrate has a double scanning line pixel array structure, so that the number of data lines is halved, which is conducive to reducing the cost of the source driver chip. The two pixel electrodes located in the same row are collectively connected on the same scanning line, which can greatly reduce the line width of the scanning segment not connected to the TFT on each scanning line, thereby relatively increasing the area of the pixel electrode and improving the pixel density. Aperture ratio, in order to solve the problem that the scanning line occupies a large area and the pixel aperture ratio is low in the dual-scanning line pixel array structure of the existing array substrate, and every two pixel electrodes are evenly distributed in pairs on the array substrate, When the array substrate is combined with a color filter substrate to form a liquid crystal panel, the color mixing of the present invention is more uniform, and the display quality effect is better.

Description of drawings

FIG. 1 is a schematic plan view of a conventional array substrate.

FIG. 2 is an equivalent circuit diagram of the array substrate of FIG. 1 .

FIG. 3 is a schematic plan view of a thin film transistor array substrate in an embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of the thin film transistor array substrate in FIG. 3 .

FIG. 5 is a schematic partial cross-sectional view of a thin film transistor array substrate in an embodiment of the present invention.

detailed description

In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the specific implementation, structure, features and effects of the present invention will be described in detail below in conjunction with the accompanying drawings and examples.

3 is a schematic plan view of a thin film transistor array substrate in an embodiment of the present invention, FIG. 4 is an equivalent circuit diagram of the thin film transistor array substrate in FIG. 3 to 5, the thin film transistor array substrate has a dual scanning line pixel array structure, the thin film transistor array substrate includes a base substrate 20 and a plurality of scanning lines 21, a plurality of data lines 22, A plurality of TFTs 23 and a plurality of pixel electrodes 24 , each pixel electrode 24 is connected to the corresponding scanning line 21 and data line 22 through a TFT 23 .

The plurality of pixel electrodes 24 are distributed in an array on the base substrate 20. For the convenience of description, P _MN represents a pixel electrode below, wherein M represents the number of rows where the pixel electrode is located, and N represents the number of columns where the pixel electrode is located. .

Two columns of pixel electrodes 24 are arranged between two adjacent data lines 22 , and each data line 22 is connected to two columns of pixel electrodes 24 on both sides of the data line 22 . As shown in Figure 3 and Figure 4, taking the second data line and the third data line in the figure as an example, there are two columns of pixel electrodes between the second data line and the third data line, which are respectively the third The second row of pixel electrodes and the fourth row of pixel electrodes, wherein the second data line is connected to the second row of pixel electrodes and the third row of pixel electrodes on both sides of the data line, and the third data line is connected to the second row of pixel electrodes on both sides of the data line. The fourth row of pixel electrodes on the side is connected to the fifth row of pixel electrodes.

Two pixel electrodes 24 in the same row between two adjacent data lines 22 are connected to the same scan line 21 . As shown in Figure 3 and Figure 4, taking the pixel electrodes in the first row in the figure as an example, the two pixel electrodes P ₁₁ and P ₁₂ located between the first data line and the second data line are connected in the same scan line (that is, the scanning line located on the lower side of the pixel electrode in the first row), and the two pixel electrodes P ₁₃ and P ₁₄ located between the second data line and the third data line are connected to the same scanning line (that is, located in On the scanning line on the upper side of the pixel electrode in the first row), the rest of the analogy will not be repeated.

The pixel electrodes 24 in the same row are alternately connected to the two scan lines 21 located on the upper and lower sides of the row of pixel electrodes. In this embodiment, among the pixel electrodes 24 in the same row, the odd-numbered pixel electrode groups are connected to the scanning lines 21 on the lower side of the row of pixel electrodes, and the even-numbered pixel electrode groups are connected to the scanning lines 21 on the upper side of the row of pixel electrodes. The lines 21 are connected, wherein each pixel electrode group includes two pixel electrodes 24 located in the same row between two adjacent data lines. As shown in Figure 3 and Figure 4, taking the pixel electrodes in the first row in the figure as an example, the two pixel electrodes P ₁₁ and P ₁₂ located between the first data line and the second data line are connected to the first On the scanning line 21 on the lower side of the row of pixel electrodes, the two pixel electrodes _P13 and _P14 between the second data line and the third data line are connected to the scanning line on the upper side of the first row of pixel electrodes. 21, the two pixel electrodes P ₁₅ and P ₁₆ located between the third data line and the fourth data line are connected to the scanning line 21 located on the lower side of the first row of pixel electrodes, and so on for the rest, so that Among the pixel electrodes in the same row, the odd-numbered pixel electrode groups are connected to the scanning lines 21 below the row of pixel electrodes, and the even-numbered pixel electrode groups are connected to the scanning lines 21 above the row of pixel electrodes. Wherein, P ₁₁ , P ₁₂ and P ₁₅ , P ₁₆ are odd-numbered pixel electrode groups of the first row of pixel electrodes, and P ₁₃ , P ₁₄ are even-numbered pixel electrode groups of the first row of pixel electrodes.

Understandably, in other embodiments, among the pixel electrodes 24 in the same row, the even-numbered pixel electrode groups may also be connected to the scanning line 21 below the row of pixel electrodes, and the odd-numbered pixel electrode groups may be connected to the scanning line 21 below the row of pixel electrodes. The scanning lines 21 on the upper side of the pixel electrodes are connected, and each pixel electrode group includes two pixel electrodes 24 located in the same row between two adjacent data lines, which will not be repeated here.

In this embodiment, the multiple data lines 22 divide each scan line 21 of the multiple scan lines 21 into multiple first scan segments 211 connected to the TFT 23 and multiple second scan segments 211 not connected to the TFT 23 Segment 212, the first scanning segment 211 and the second scanning segment 212 are located between two adjacent data lines 22, the first scanning segment 211 and the second scanning segment 212 on each scanning line 21 are along the scanning line Alternately distributed along the length direction, the line width of the second scanning segment 212 is smaller than the line width of the first scanning segment 211 . As mentioned above, since the two pixel electrodes 24 located in the same row between two adjacent data lines 22 are collectively connected to the same scanning line 21, specifically, connected to the first scanning segment 211 connected to the TFT 23 Therefore, the line width of the second scanning segment 212 not connected to the TFT 23 can be greatly reduced.

Two adjacent scanning lines 21 are arranged between the pixel electrodes 24 of two adjacent rows up and down, and the two adjacent scanning lines 21 are respectively connected with the pixel electrodes 24 of the two adjacent rows up and down. The first scan segments 211 on 21 are alternately distributed along the length direction of the scan lines, and the second scan segments 212 on the two adjacent scan lines 21 are also alternately distributed along the length direction of the scan lines. Specifically, as shown in FIG. 3 and FIG. 4 , taking the pixel electrodes in the first row and the second row in the figure as an example, there are two adjacent scanning lines 21 between the pixel electrodes in the first row and the second row of pixel electrodes. , for the convenience of description, the two adjacent scanning lines 21 are temporarily referred to as the upper scanning line 21a and the lower scanning line 21b, and the two pixel electrodes P ₁₁ and P ₁₂ in the first row are connected to the two adjacent scanning lines. On the upper scanning line 21a in line 21, the two pixel electrodes P ₂₃ and P ₂₄ in the second row are connected to the lower scanning line 21b in the two adjacent scanning lines 21, and the two pixel electrodes in the first row The electrodes P ₁₅ and P ₁₆ are connected to the upper scanning line 21 a of the two adjacent scanning lines 21 , and so on for the rest. So that on the two adjacent scanning lines 21, the first scanning segments 211 of the upper scanning line 21a and the first scanning segments 211 of the lower scanning line 21b are alternately distributed along the length direction of the scanning lines, and the upper scanning lines 21a The second scanning segments 212 and the second scanning segments 212 of the lower scanning line 21b are also alternately distributed along the length direction of the scanning line. In this way, the second scanning segment 212 with a smaller width can be used to increase the pixel aperture ratio, and at the same time, the first scanning segment 211 with a larger width is uniformly and alternately distributed on the entire array substrate, so that every two pixel electrodes 24 Evenly distributed in groups of two on the array substrate, when the array substrate is made into a liquid crystal panel with a color filter substrate (colerfilter, CF), the color mixing of the present invention is more uniform, and the display quality effect is better.

In this embodiment, the line width of the second scanning segment 212 not connected to the TFT 23 is about one-third of the line width of the first scanning segment 211 connected to the TFT 23 . For example, if the line width of the first scanning segment 211 is 30 um, the line width of the second scanning segment 212 is at most 10 um. Since the line width of the scanning line 21 is greatly reduced, the area of the pixel electrode 24 can be relatively increased, thereby increasing the aperture ratio of the pixel. In this embodiment, the aperture ratio can be increased by more than 20%.

Please refer to FIG. 5 , in this embodiment, the thin film transistor array substrate further forms a gate metal layer 231 on the base substrate 20, a gate insulating layer 232 is formed on the gate metal layer 231, and a gate insulating layer 232 is formed on the gate insulating layer 232. A semiconductor layer 233 is formed, a source metal layer 234 and a drain metal layer 235 are formed on the semiconductor layer 233, a passivation protection layer 25 is formed on the source metal layer 234 and the drain metal layer 235, and a passivation protection layer 25 is formed on the passivation protection layer 25. A pixel electrode 24 is formed. Wherein, the gate metal layer 231, the gate insulating layer 232, the semiconductor layer 233, the source metal layer 234 and the drain metal layer 235 form a TFT 23, and the gate metal layer 231 of each TFT 23 is connected to the corresponding scanning line 21. The source metal layer 234 of each TFT 23 is connected to the corresponding data line 22 , and the drain metal layer 235 of each TFT 23 is connected to the corresponding pixel electrode 24 . The passivation protection layer 25 is provided with a through hole (not shown) exposing a part of the drain, and the drain metal layer 235 of each TFT 23 is connected to the corresponding pixel electrode 24 through the through hole.

In this embodiment, the line width of the first scanning segment 211 connected to the TFT23 is the same as the width of the gate metal layer 231 of each TFT23, so that the connection of the TFT23 to the corresponding scanning line 21 is not affected, and the structure of the TFT23 does not need to be changed. and process.

The present invention also provides a display panel, which includes the above-mentioned thin film transistor array substrate, a color filter substrate (not shown in the figure), and a liquid crystal layer (not shown in the figure) between the thin film transistor array substrate and the color filter substrate. .

The present invention also provides a display device, which includes the above-mentioned display panel.

The thin film transistor array substrate provided by the above embodiment has a double scanning line pixel array structure, so that the number of data lines is halved, which is beneficial to reduce the cost of the source driver chip. In addition, by connecting two adjacent data lines The two pixel electrodes located in the same row are collectively connected on the same scanning line, which can greatly reduce the line width of the scanning segment not connected to the TFT on each scanning line, thereby relatively increasing the area of the pixel electrode and improving The aperture ratio of the pixel is to solve the problem that the scanning line occupies a large area and the pixel aperture ratio is low in the dual-scanning line pixel array structure of the existing array substrate, and every two pixel electrodes are evenly distributed in pairs on the array substrate When the array substrate is combined with a color filter substrate to make a liquid crystal panel, the color mixing of the present invention is more uniform, and the display quality effect is better.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the technical content disclosed above to make some changes or modify them into equivalent embodiments with equivalent changes, but as long as they do not depart from the technical solution of the present invention, the Technical Essence Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solution of the present invention.

Claims (9)

1. A thin film transistor array substrate, comprising a plurality of scanning lines, a plurality of data lines, a plurality of TFTs and a plurality of pixel electrodes arranged on the base substrate, each pixel electrode is connected with corresponding scanning lines and data lines through TFTs Connected, characterized by: Two columns of pixel electrodes are arranged between two adjacent data lines, and each data line is connected to two columns of pixel electrodes located on both sides of the data line; Two pixel electrodes located in the same row between two adjacent data lines are connected to the same scanning line; The pixel electrodes in the same row are alternately connected to the two scanning lines on the upper and lower sides of the row of pixel electrodes; The plurality of data lines divides each of the plurality of scanning lines into a plurality of first scanning segments connected to TFTs and a plurality of second scanning segments not connected to TFTs, the first scanning segments and the first scanning segments The two scanning segments are located between two adjacent data lines, the first scanning segment and the second scanning segment on each scanning line are alternately distributed along the length direction of the scanning line, and the line width of the second scanning segment is smaller than that of the first scanning segment. The line width of a scan segment; Two adjacent scanning lines are arranged between the pixel electrodes of the upper and lower adjacent rows, and the two adjacent scanning lines are respectively connected with the pixel electrodes of the upper and lower adjacent rows. The scan segments are alternately distributed along the length direction of the scan lines, and the second scan segments on the two adjacent scan lines are also alternately distributed along the length direction of the scan lines. 2. The thin film transistor array substrate according to claim 1, wherein among the pixel electrodes in the same row, the odd-numbered pixel electrode groups are connected to the scanning lines on the lower side of the row of pixel electrodes, and the even-numbered pixel electrode groups are It is connected to the scanning line on the upper side of the row of pixel electrodes, wherein each pixel electrode group includes two pixel electrodes in the same row between two adjacent data lines. 3. The thin film transistor array substrate according to claim 1, wherein, among the pixel electrodes in the same row, the even-numbered pixel electrode groups are connected to the scanning lines on the lower side of the row of pixel electrodes, and the odd-numbered pixel electrode groups are It is connected to the scanning line on the upper side of the row of pixel electrodes, wherein each pixel electrode group includes two pixel electrodes in the same row between two adjacent data lines. 4 . The thin film transistor array substrate according to claim 1 , wherein the line width of the second scanning segment is one-third of the line width of the first scanning segment. 5. The thin film transistor array substrate according to any one of claims 1 to 4, wherein the gate metal layer of each TFT is connected to the corresponding scanning line, and the source metal layer of each TFT is connected to the corresponding data The drain metal layer of each TFT is connected to the corresponding pixel electrode. 6. The thin film transistor array substrate according to claim 5, characterized in that, the thin film transistor array substrate further comprises a passivation protection layer covering the source metal layer and the drain metal layer of each TFT, the passivation A through hole is provided on the protection layer, and the drain metal layer of each TFT is connected to the corresponding pixel electrode through the through hole. 7. The thin film transistor array substrate according to claim 5, wherein the line width of the first scanning segment is the same as the width of the gate metal layer of each TFT. 8. A display panel, comprising the thin film transistor array substrate according to any one of claims 1 to 7. 9. A display device, comprising the display panel according to claim 8.