CN103163697A - Pixel array structure - Google Patents

Abstract

A pixel array structure, comprising: the display device comprises a plurality of sub-pixels arranged in rows and columns, scanning lines arranged in the row direction and data lines arranged in the column direction, wherein at least two rows of the sub-pixels share one scanning line, and in each column of the sub-pixels, the plurality of sub-pixels connected to the same scanning line are respectively connected with a plurality of different data lines. The number of scanning lines is reduced compared with the prior art under the condition of the same resolution; or under the condition of using the same number of scanning lines, the resolution of the display panel can be doubled, and the problem that the resolution of the display panel is limited due to the fact that the charging time of a TFT switch is ensured in the prior art is effectively solved.

Description

Pixel Array Structure

technical field

The invention relates to the field of displays, in particular to an arrangement method of a pixel array.

Background technique

In the prior art, pixel arrays can be divided into strip RGB (StripRGB) mode pixel arrays, RGBW mode pixel arrays, and 3D display mode pixel arrays according to different sub-pixels in the pixel arrays. In the pixel array of the strip RGB mode, the R, G, and B sub-pixels are arranged in a row in the direction of the scanning line. In the pixel array of the RGBW mode, the R, G, B, and W sub-pixels are arranged in two rows and two columns. The pixels in the 3D display mode The R, G, and B sub-pixels in the array are arranged in a row in the direction of the data line.

Fig. 1 is a schematic diagram of the pixel array of the RGBW mode of the prior art, referring to Fig. 1, the R, G, B, W sub-pixels of the pixel array of the RGBW mode of the prior art are arranged in two rows and two columns, and each row has a The scan line 11 is electrically connected to the gate of the TFT switch of the corresponding sub-pixel; each column has a data line 12 electrically connected to the source of the TFT switch of the corresponding sub-pixel. Based on the pixel array with this structure, each row of sub-pixels needs to be driven by a separate scanning line.

Fig. 2 is a schematic diagram of a pixel array in a 3D display mode in the prior art. Referring to Fig. 2, the R, G, and B sub-pixels of the pixel array in a 3D display mode in the prior art are arranged in a column in the direction of data lines, and each row has a The scan line 21 is electrically connected to the gate of the TFT switch of the corresponding sub-pixel, and each column has a data line 22 electrically connected to the source of the TFT switch of the corresponding sub-pixel. Based on such a pixel array substrate, each row of sub-pixels also needs to be driven by a separate scanning line.

In the prior art, the active region in the TFT switch is usually amorphous silicon. Due to the low mobility of amorphous silicon, the display device usually only allows 1280 scanning lines. If the number of scanning lines is increased, the TFT switch will be damaged. Insufficient charging will affect the display. For the pixel array substrate in RGBW mode, the line resolution of the display device is only 640 lines at most; for the pixel array substrate in 3D display mode, the line resolution of the display device is only 427 lines at most. For mobile phones and small portable display devices, the line resolution is required to be at least 800 lines. For the display device of RGBW mode pixel array substrate, 1600 scan lines are required; for the display device of 3D display mode pixel array substrate, the scan line needs 2400 lines; for the display devices of the two modes of pixel array substrates, the number of scanning lines exceeds 1280 lines, which will cause insufficient charging of the TFT switch and affect the display.

Contents of the invention

The problem solved by the present invention is the problem of small row resolution in the display device of RGBW mode pixel array substrate and the display device of 3D display mode pixel array substrate in the prior art.

In order to solve the above problems, the present invention provides a pixel array structure, including: a plurality of sub-pixels arranged in rows and columns, and scanning lines arranged in the row direction and data lines arranged in the column direction, at least two rows of the sub-pixels share For one scanning line, in each column of sub-pixels, multiple sub-pixels connected to the same scanning line are respectively connected to different data lines.

Optionally, the aspect ratio of the sub-pixel is less than or equal to 1, wherein the length refers to the length along the data line direction, and the width refers to the length along the scan line direction.

Optionally, the aspect ratio of the sub-pixels is 1:1˜1:4.

Optionally, each sub-pixel includes a TFT switch, the gate of the TFT switch is connected to the corresponding scan line, the source is connected to the corresponding data line, and the drain is connected to the pixel electrode of the sub-pixel.

Optionally, the different data lines are respectively located on two sides of the column of sub-pixels.

Optionally, the different data lines are located on the same side of the column of sub-pixels.

Optionally, two adjacent rows of sub-pixels share one scan line, and in each column of sub-pixels, two sub-pixels connected to the same scan line are connected to two different data lines.

Optionally, the same scanning line shared by the two adjacent rows of sub-pixels is located between the two rows of adjacent sub-pixels.

Optionally, the plurality of sub-pixels are R, G, B, and W sub-pixels respectively, and four adjacent R, G, B, and W sub-pixels form a pixel unit, and in each pixel unit, R, G, B, and W sub-pixels form a pixel unit. B and W sub-pixels are arranged in two rows and two columns.

Optionally, the aspect ratio of the R, G, B, and W sub-pixels is 1:1, where the length refers to the length along the data line direction, and the width refers to the length along the scan line direction.

Optionally, three rows of adjacent sub-pixels share one scan line, and in each column of sub-pixels, three sub-pixels connected to the same scan line are connected to three different data lines.

Optionally, the plurality of sub-pixels are R, G, and B sub-pixels respectively, and three adjacent R, G, and B sub-pixels form a pixel unit, and in each pixel unit, the R, G, and B sub-pixels are in the form of Arranged in three rows and one column.

Optionally, the aspect ratio of the R, G, and B sub-pixels is 1:3, where the length refers to the length along the data line direction, and the width refers to the length along the scan line direction.

Optionally, the scan line is located between two adjacent rows of sub-pixels.

The pixel array structure provided by the present invention can reduce the number of scanning lines compared with the prior art in the case of the same resolution; or in the case of using the same number of scanning lines, the resolution of the display panel can be doubled, effectively It solves the problem in the prior art that the resolution of the display panel is limited due to the need to ensure the charging time of the TFT switch. The present invention has significant significance in improving the resolution of the display panel. Using the pixel array structure of the present invention, the displayed line resolution will no longer be limited by the number of scanning lines that cannot exceed 1280, and can provide clearer and delicate display effect.

Description of drawings

FIG. 1 is a schematic diagram of an RGBW mode pixel array substrate in the prior art;

2 is a schematic diagram of a 3D display mode pixel array substrate in the prior art;

3 is a schematic layout diagram of a pixel array substrate according to a first embodiment of the present invention;

4 is a schematic layout diagram of a pixel array substrate according to a second specific embodiment of the present invention;

FIG. 5 is a schematic layout diagram of a pixel array substrate according to a third embodiment of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

In the following description, specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways than those described here, and those skilled in the art can make similar extensions without departing from the connotation of the present invention. Accordingly, the present invention is not limited to the specific embodiments disclosed below.

A liquid crystal display generally includes: a pixel array substrate, a color filter plate, and a liquid crystal layer between the pixel array substrate and the color filter plate.

Among them, the pixel array structure of the pixel array substrate in the display device according to the specific embodiment of the present invention is: a plurality of sub-pixels arranged in rows and columns, and scanning lines arranged in the row direction and data lines arranged in the column direction, at least two rows The sub-pixels share one scan line, and in each column of sub-pixels, multiple sub-pixels connected to the same scan line are respectively connected to different data lines. The pixel array structure provided by the present invention can reduce the number of scanning lines, or drive the pixel array with fewer scanning lines under the same row resolution, thereby improving the row resolution of display.

first embodiment

FIG. 3 is a schematic diagram of the pixel array structure of the first specific embodiment of the present invention. With reference to FIG. 3 , the pixel array structure 20 of the first embodiment includes a plurality of sub-pixels arranged in rows and columns, and a plurality of sub-pixels arranged in the row direction One scan line 21 and a plurality of data lines 221, 222, 223, 224... arranged in the column direction, in this embodiment, the first row of sub-pixels and the second row of sub-pixels share one scan line Line 21; in each column of sub-pixels, multiple sub-pixels connected to the same scan line are respectively connected to different data lines. In this embodiment, for example: two sub-pixels connected to the same scan line 21 in the same column of sub-pixels are respectively Connect to data line 221 and data line 222 .

Specifically, each sub-pixel includes a TFT switch 25 , the gate of the TFT switch 25 is connected to the corresponding scan line 21 , the source is connected to the corresponding data line, and the drain is connected to the pixel electrode of the sub-pixel.

In this embodiment, two sub-pixels connected to the same scanning line 21 in the same column of sub-pixels are respectively connected to the data line 221 and the data line 222, and the data line 221 and the data line 222 are respectively arranged on the sub-pixels of the column. On both sides, the source of the TFT switch 25 of each sub-pixel is connected to the pixel electrode of each sub-pixel to provide data signals thereto.

In other embodiments of the present invention, one scan line can also control more than two rows of sub-pixels, for example, one scan line can control three or four rows of sub-pixels, and in one column of sub-pixels, the sub-pixels connected to the same scan line The pixels transmit data signals through different data lines respectively, and then display.

The pixel array structure provided by the present invention can reduce the number of scanning lines compared with the prior art in the case of the same resolution; or in the case of using the same number of scanning lines, the resolution of the display panel can be doubled, effectively It solves the problem in the prior art that the resolution of the display panel is limited due to the need to ensure the charging time of the TFT switch. The present invention has significant significance in improving the resolution of the display panel. Using the pixel array structure of the present invention, the displayed line resolution will no longer be limited by the number of scanning lines that cannot exceed 1280, and can provide clearer and delicate display effect.

second embodiment

FIG. 4 is a schematic layout diagram of a pixel array according to a second specific embodiment of the present invention. With reference to FIG. 4 , the pixel array structure of the second embodiment includes: a plurality of sub-pixels arranged in rows and columns, and the plurality of sub-pixels are R, G, B. The W sub-pixel further includes a plurality of scanning lines 31a arranged in the row direction and a plurality of data lines 33a, 32a, 36a, 35a and the like arranged in the column direction. In the second embodiment, four adjacent R, G, B, and W sub-pixels form a pixel unit, and in a pixel unit, the R, G, B, and W sub-pixels are arranged in two rows and two columns, and the The rows are parallel to the directions of the scan lines, and the columns are parallel to the directions of the data lines. In addition, the R, G, B, and W sub-pixels of a pixel unit share one scan line, and the scan line is located between two adjacent rows of sub-pixels, and in the same column of sub-pixels, multiple sub-pixels connected to the same scan line connected to two different data lines, and the two data lines are located on the same side of the column of sub-pixels.

Specifically, in the specific embodiment shown in FIG. 4 , the R, G, B, and W sub-pixels of a pixel unit share one scanning line 31a, and the scanning line 31a is located between two adjacent rows of sub-pixels, that is, scanning The line 31a is located between the R, G sub-pixels and the B, W sub-pixels. The four sub-pixels that share the same scanning line 31a are connected to different data lines, specifically, the first data line 32a, the second data line 33a, the third data line 35a and the fourth data line 36a respectively connect to four W, The G, B, and R sub-pixels transmit data voltages. B and R sub-pixels are sub-pixels in the same column, and the third data line 35a and the fourth data line 36a that transmit data voltage to them are located on the same side of the sub-pixel in the column, specifically on the left side; the sub-pixels in W and G are in the same column of sub-pixels , the first data line 32a and the second data line 33a to which the data voltage is transmitted are located on the same side of the column of sub-pixels, specifically on the left side thereof.

In the present invention, each sub-pixel is R, G, B, W sub-pixel respectively, and the aspect ratio of the sub-pixel is less than or equal to 1, which can be 1:1 to 1:4, specifically in this embodiment: 1:1. The length refers to the length in the direction of the data line, and the width refers to the length in the direction of the scanning line, that is, the ratio of the length of the sub-pixel along the direction of the data line to the length of the sub-pixel along the direction of the scanning line is less than or equal to 1.

In the pixel array structure provided by the present invention, since multiple data lines need to be provided to respectively transmit data voltages to multiple sub-pixels connected to the same scan line in each column of sub-pixels, the number of data lines is greater than the number of scan lines. Setting the side length of the sub-pixel along the data line direction to be smaller than or equal to the side length along the scan line direction can reduce the aperture ratio occupied by the data line.

In the second embodiment, the TFT switch 34a of each sub-pixel is located on the side of the corresponding sub-pixel close to the scan line. The source of the TFT switch 34a of the G subpixel is connected to the second data line 33a next to the column of subpixels, and the source of the TFT switch 34a of the W subpixel is connected to the first data line 32a on the left side of the second data line 33a. The source of the TFT switch 34a of the G sub-pixel, the source of the TFT switch 34a of the W sub-pixel, the second data line 33a and the first data line 32a are all formed in the same metal layer and in the same process step. The source of the TFT switch 34a of the sub-pixel is short-circuited with the second data line 33a when connected to the first data line 32a, then the first data line and the source of the TFT switch can be connected by a metal bond bridge of a metal layer different from the source of the TFT switch. The data line 32a and the source of the TFT switch 34a of the W sub-pixel. Optionally, the metal key bridge can be made of the same layer of metal as the scan line. The metal bond bridge electrically connects the first data line 32a and the source of the TFT switch 34a of the W sub-pixel along a direction parallel to the scanning line. In other embodiments of the present invention, the source electrodes of other TFT switches that need to be connected across other data lines and the corresponding data lines can also be connected by the above method of setting metal bond bridges.

It should be noted that in the second embodiment, in the same column of sub-pixels, multiple sub-pixels connected to the same scanning line are connected to two different data lines, and the two data lines can also be located in the same row of sub-pixels. side. In a variation of the second embodiment, the two data lines may also be located on both sides of the column of sub-pixels, and correspondingly, the positions of the TFT switches need to be changed accordingly.

third embodiment

FIG. 5 is a schematic layout diagram of a pixel array according to a third specific embodiment of the present invention. Referring to FIG. 5 , the pixel array structure 40 of the third embodiment includes a plurality of sub-pixels arranged in rows and columns, respectively R, G, and B sub-pixels, The plurality of R sub-pixels, G sub-pixels and B sub-pixels are respectively arranged in rows, and also includes a plurality of scanning lines 41 arranged in the row direction and a plurality of data lines arranged in the column direction. Three adjacent R, G, and B sub-pixels form a pixel unit. In one pixel unit, the three sub-pixels of R, G, and B are arranged in a row. In the example shown in FIG. 5 , the R, G, and B sub-pixels are arranged sequentially, but not limited to this arrangement, and the R, G, and B sub-pixels can be arranged in any order, as long as the three sub-pixels are in the same column.

In this embodiment, three adjacent R sub-pixel rows, G sub-pixel rows and B sub-pixel rows share one scanning line 41, and the scanning line 41 is located between two rows of adjacent sub-pixels, as shown in FIG. 5 In the example shown above, the scan line 41 is located between the adjacent G sub-pixel row and the B sub-pixel row. Of course, the position of the scan line 41 is not limited to this position, and the scan line 41 can also be located between the adjacent G sub-pixel row and the R sub-pixel row. between sub-pixel rows.

The R, G, and B three sub-pixels connected to the same scan line 41 in the same row of sub-pixels are respectively connected to the first data line 42, the second data line 43 and the third data line 44, and the first data line 42, the second data line The line 43 and the third data line 44 are all located on the same side of the column of sub-pixels, specifically in this embodiment, the first data line 42, the second data line 43 and the third data line 44 are all located on the side of the column of sub-pixels Right.

Each sub-pixel has a TFT switch 45. Since the first data line 42, the second data line 43 and the third data line 44 are all located on the same side of the R, G, and B sub-pixels in the same row, each corresponding TFT switch 45 is located on the corresponding sub-pixel. The pixel is close to the first data line 42, the second data line 43, and the third data line 44, and the gates of the TFT switches corresponding to the R, G, and B sub-pixels are electrically connected to the scanning line 41, and the R, G The source electrodes of the TFT switches corresponding to the B subpixels are electrically connected to the first data line 42 , the second data line 43 and the third data line 44 respectively. In the embodiment shown in FIG. 5 , specifically: the source of the TFT switch of the R sub-pixel is electrically connected to the first data line 42, the source of the TFT switch of the G sub-pixel is electrically connected to the second data line 43, and the source of the TFT switch of the B sub-pixel is electrically connected to the second data line 43. The sources of the TFT switches of the sub-pixels are electrically connected to the third data line 44 .

In the third embodiment, three adjacent R sub-pixel rows, G sub-pixel rows, and B sub-pixel rows share one scanning line, which reduces two scanning lines compared with the prior art, and correspondingly improves the performance of the display device. row resolution.

In the third embodiment, the aspect ratio of the sub-pixel is less than 1, wherein the length refers to the length in the direction of the data line, and the width refers to the length in the direction of the scanning line, that is, the ratio of the length of the sub-pixel along the direction of the data line to its length along the direction of the scanning line The ratio is less than or equal to 1. Optionally, the aspect ratio of the sub-pixel is 1:3, that is, the length of the sub-pixel is reduced and the width of the sub-pixel is increased, so as to reduce the influence of increasing the data line on the aperture ratio.

The pixel array substrate in the present invention is not only suitable for liquid crystal display devices, but also can be suitable for electronic paper display devices or other display devices.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can use the methods disclosed above and technical content to analyze the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made in the technical solution. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range.

Claims (14)

1. A pixel array structure, comprising: a plurality of sub-pixels arranged in rows and columns, and scanning lines arranged in the row direction and data lines arranged in the column direction, characterized in that at least two rows of the sub-pixels share one For the scanning line, in each column of sub-pixels, multiple sub-pixels connected to the same scanning line are respectively connected to different data lines. 2. The pixel array structure according to claim 1, wherein the aspect ratio of the sub-pixels is less than or equal to 1, wherein the length refers to the length along the data line direction, and the width refers to the length along the scan line direction. 3. The pixel array structure according to claim 2, wherein the aspect ratio of the sub-pixels is 1:1˜1:4. 4. The pixel array structure according to claim 1, wherein each sub-pixel comprises a TFT switch, the gate of the TFT switch is connected to the corresponding scan line, the source is connected to the corresponding data line, and the drain is Connect to the pixel electrode of the sub-pixel. 5. The pixel array structure according to claim 1, wherein the different data lines are respectively located on two sides of the column of sub-pixels. 6. The pixel array structure according to claim 1, wherein the different data lines are located on the same side of the column of sub-pixels. 7. The pixel array structure according to claim 1, wherein two rows of adjacent sub-pixels share one scan line, and in each column of sub-pixels, two sub-pixels connected to the same scan line are connected to Two different data lines. 8 . The pixel array structure according to claim 7 , wherein the same scanning line shared by the two adjacent rows of sub-pixels is located between the two adjacent rows of sub-pixels. 9. The pixel array structure according to claim 7, wherein the plurality of sub-pixels are respectively R, G, B, and W sub-pixels, and four adjacent R, G, B, and W sub-pixels form one A pixel unit, in each pixel unit R, G, B, W sub-pixels are arranged in two rows and two columns. 10. The pixel array structure according to claim 9, wherein the aspect ratio of the R, G, B, and W sub-pixels is 1:1, where the length refers to the length along the direction of the data line, and the width refers to the length along the direction of the data line. Length in scanline direction. 11. The pixel array structure according to claim 1, wherein three rows of adjacent sub-pixels share one scan line, and in each column of sub-pixels, three sub-pixels connected to the same scan line are connected to Three different data lines. 12. The pixel array structure according to claim 11, wherein the plurality of sub-pixels are respectively R, G, and B sub-pixels, and three adjacent R, G, and B sub-pixels form a pixel unit. The R, G, and B sub-pixels in each pixel unit are arranged in three rows and one column. 13. The pixel array structure according to claim 12, wherein the aspect ratio of the R, G, and B sub-pixels is 1:3, where the length refers to the length along the data line, and the width refers to the length along the scan line. The length of the direction. 14. The pixel array structure according to claim 11, wherein the scan line is located between two adjacent rows of sub-pixels.

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