CN105140124B - A kind of production method of polycrystalline SiTFT - Google Patents

Abstract

The invention discloses a method for manufacturing a polysilicon thin film transistor, which includes: providing a glass substrate, forming a buffer layer and a polysilicon layer sequentially on the glass substrate; coating a photoresist on the polysilicon layer, and using a halftone mask Exposing and etching the photoresist with a mold mask; ion implantation of high-dose P doping to form N+; sequentially forming an insulating layer and a gate layer on the entire surface of the glass substrate; Coating a photoresist and exposing the photoresist with a half-tone mask; ion implantation of high-dose B doping to form P+. The invention can reduce the number of photomasks and effectively reduce the cost.

Description

A method of manufacturing a polysilicon thin film transistor

【Technical field】

The invention relates to the field of display technology, in particular to a method for manufacturing a polysilicon thin film transistor.

【Background technique】

In the current manufacturing process of LTPS (Low Temperature Poly-silicon, low temperature polysilicon technology), in order to complete the definition of CMos (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) and gate (gate), and form LDD (asymmetric lightly doped Miscellaneous leakage), which requires 4 ordinary masks to complete, and for the effect of LDD, a process of 5 masks is used. Therefore, the traditional process will lead to a shortage of PH production capacity, a large number of equipment requirements, and high costs.

Therefore, it is necessary to propose a new technical solution to solve the above technical problems.

【Content of invention】

The object of the present invention is to provide a method for manufacturing a polysilicon thin film transistor, which can reduce the number of photomasks and effectively reduce the cost.

In order to solve the above problems, the technical solution of the present invention is as follows:

A method for manufacturing a polysilicon thin film transistor, the method for manufacturing a polysilicon thin film transistor comprises:

A glass substrate is provided, and a buffer layer and a polysilicon layer are sequentially formed on the glass substrate;

Coating a photoresist on the polysilicon layer, exposing and etching the photoresist by using a half-tone mask;

Ion implantation of high-dose P doping to form N+;

sequentially forming an insulating layer and a gate layer on the entire surface of the glass substrate;

coating a photoresist on the gate layer, and exposing the photoresist with a half-tone mask;

Ion implantation high dose B doping, forming P+.

Preferably, in the method for manufacturing a polysilicon thin film transistor, the step of forming a polysilicon layer on the glass substrate includes:

forming an amorphous silicon layer on the buffer layer;

An excimer laser annealing operation is performed on the amorphous silicon layer to form a polycrystalline silicon layer.

Preferably, in the method for manufacturing a polysilicon thin film transistor, after the step of forming a polysilicon layer on the glass substrate, further comprising:

Ion implantation light dose B doping to form a channel.

Preferably, in the manufacturing method of the polysilicon thin film transistor, the step of exposing and etching the photoresist by using a half-tone mask mask includes:

exposing the photoresist by using a halftone mask;

Etching away excess polysilicon;

The half exposed photoresist is etched away.

Preferably, in the manufacturing method of the polysilicon thin film transistor, after the step of ion implanting high-dose P doping and forming N+, it also includes:

The remaining photoresist is removed.

Preferably, in the manufacturing method of the polysilicon thin film transistor, after the step of coating a photoresist on the gate layer and exposing the photoresist with a half-tone mask mask, it also includes:

Etch away excess gate.

Preferably, in the manufacturing method of the polysilicon thin film transistor, the B dose is lower than the high dose P.

Preferably, in the manufacturing method of the polysilicon thin film transistor, after the step of ion implanting high-dose B doping and forming P+, it also includes:

etching away the half-exposed photoresist;

Etching away the exposed gate;

The remaining photoresist is removed.

Preferably, in the method for manufacturing a polysilicon thin film transistor, after the step of removing the remaining photoresist, it further includes:

Ion implantation low-dose P doping to form N-.

Preferably, in the manufacturing method of the polysilicon thin film transistor, before the step of removing the remaining photoresist, it also includes:

Ion implantation low-dose P doping to form N-.

Compared with the prior art, the present invention uses two half-tone masking masks to complete the definition of CMos (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) and gate, and form LDD. Therefore, the number of masks is reduced from 4 to 2, which greatly improves the competitiveness; therefore, the manufacturing method of the polysilicon thin film transistor provided by the present invention can effectively reduce the number of masks and reduce the cost.

In order to make the above content of the present invention more comprehensible, preferred embodiments are specifically cited below, together with the accompanying drawings, and described in detail as follows.

【Description of drawings】

FIG. 1 is a schematic diagram of the implementation process of a method for manufacturing a polysilicon thin film transistor provided by an embodiment of the present invention;

FIG. 2 is a schematic flow diagram of a method for manufacturing a polysilicon thin film transistor provided in Embodiment 1 of the present invention;

FIG. 3 is a schematic flow diagram of a method for manufacturing a polysilicon thin film transistor provided in Embodiment 2 of the present invention;

FIG. 4 is a schematic structural view of sequentially forming a buffer layer and a polysilicon layer on a glass substrate according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of ion implantation light dose B doping provided by an embodiment of the present invention;

6A and 6B are schematic structural views of coating a photoresist on a polysilicon layer provided by an embodiment of the present invention;

7A and 7B are structural schematic diagrams of etching away redundant polysilicon provided by the embodiment of the present invention;

8A and 8B are structural schematic diagrams of the half-exposed photoresist 13 etched away according to an embodiment of the present invention;

9A and 9B are schematic structural diagrams of forming N+ by ion implantation with high-dose P doping provided by an embodiment of the present invention;

FIG. 10A and FIG. 10B are schematic structural diagrams of removing the remaining photoresist provided by the embodiment of the present invention;

11A and 11B are schematic structural diagrams for forming an insulating layer and a gate layer according to an embodiment of the present invention;

12A and 12B are schematic structural views of coating a photoresist on the gate layer according to an embodiment of the present invention;

FIG. 13A and FIG. 13B are structural schematic diagrams of etching away redundant gates provided by embodiments of the present invention;

Fig. 14A and Fig. 14B are schematic structural diagrams of forming P+ by ion implantation with high dose B doping provided by the embodiment of the present invention;

15A and 15B are structural schematic diagrams of half-exposed photoresist etched away according to an embodiment of the present invention;

16A and 16B are structural schematic diagrams of etching away exposed gates provided by embodiments of the present invention;

Fig. 17A and Fig. 17B are schematic structural diagrams of ion implantation low-dose P doping to form N- provided by the embodiment of the present invention;

FIG. 18A and FIG. 18B are schematic structural diagrams of removing the remaining photoresist provided by the embodiment of the present invention.

【Detailed ways】

The word "embodiment" as used in this specification means serving as an example, instance or illustration. Furthermore, the article "a" as used in this specification and the appended claims may generally be construed to mean "one or more" unless specified otherwise or clear from context to refer to a singular form.

In the embodiment of the present invention, the present invention uses a 2-channel half-tone mask to complete the definition of CMos (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) and gate, and form LDD. Therefore, the number of masks is reduced from 4 to 2, which greatly improves the competitiveness; therefore, the manufacturing method of the polysilicon thin film transistor provided by the present invention can effectively reduce the number of masks and reduce the cost.

Please refer to FIG. 1. FIG. 1 is a schematic flow diagram of a method for manufacturing a polysilicon thin film transistor provided by an embodiment of the present invention; the method for manufacturing a polysilicon thin film transistor mainly includes the following steps:

In step S101, a glass substrate is provided, and a buffer layer and a polysilicon layer are sequentially formed on the glass substrate;

In an embodiment of the present invention, the step of forming a polysilicon layer on the glass substrate includes:

forming an amorphous silicon layer on the buffer layer;

An excimer laser annealing operation is performed on the amorphous silicon layer to form a polycrystalline silicon layer.

In step S102, coating a photoresist on the polysilicon layer, and exposing and etching the photoresist by using a half-tone mask;

In an embodiment of the present invention, the step of exposing and etching the photoresist by using a half-tone mask mask includes:

exposing the photoresist by using a halftone mask;

Etching away excess polysilicon;

The half exposed photoresist is etched away.

In step S103, IMP (IMPLANT, ion implantation) is doped with high dose P to form N+;

In step S104, an insulating layer and a gate layer are sequentially formed on the entire surface of the glass substrate;

In an embodiment of the present invention, the step of forming an insulating layer on the entire surface of the glass substrate includes:

An insulating layer is deposited on the entire surface of the glass substrate by chemical vapor deposition.

The step of forming a gate layer on the entire surface of the glass substrate includes:

A gate layer is deposited on the insulating layer by physical vapor deposition.

In step S105, coating a photoresist on the gate layer, and exposing the photoresist by using a halftone mask;

In step S106, the IMP ion-implants high-dose B doping to form P+.

In the embodiment of the present invention, the dose of B is lower than the high dose of P, so as not to cause the disappearance of N+.

In order to illustrate the technical solutions of the present invention, specific examples are used below to illustrate.

Embodiment one

Please refer to FIG. 2. FIG. 2 is a schematic flow diagram of a method for manufacturing a polysilicon thin film transistor provided in Embodiment 1 of the present invention; it mainly includes the following steps:

In step S201, a glass substrate is provided, and a buffer layer and a polysilicon layer are sequentially formed on the glass substrate;

In an embodiment of the present invention, the step of forming a polysilicon layer on the glass substrate includes:

forming an amorphous silicon layer on the buffer layer;

An excimer laser annealing operation is performed on the amorphous silicon layer to form a polycrystalline silicon layer.

In step S202, the IMP ion is implanted with a light dose of B doping to form a channel;

In step S203, coating a photoresist on the polysilicon layer, and exposing and etching the photoresist by using a half-tone mask;

In an embodiment of the present invention, the step of exposing and etching the photoresist by using a half-tone mask mask includes:

exposing the photoresist by using a halftone mask;

Etching away excess polysilicon;

The half exposed photoresist is etched away.

In step S204, IMP ion-implants high-dose P doping to form N+;

In step S205, removing the remaining photoresist;

In step S206, an insulating layer and a gate layer are sequentially formed on the entire surface of the glass substrate;

In an embodiment of the present invention, the step of forming an insulating layer on the entire surface of the glass substrate includes:

An insulating layer is deposited on the entire surface of the glass substrate by chemical vapor deposition.

The step of forming a gate layer on the entire surface of the glass substrate includes:

A gate layer is deposited on the insulating layer by physical vapor deposition.

In step S207, coating a photoresist on the gate layer, and exposing the photoresist with a half-tone mask;

In step S208, etching off redundant gates;

In step S209, the IMP ion-implants high-dose B doping to form P+.

In the embodiment of the present invention, the dose of B is lower than the high dose of P, so as not to cause the disappearance of N+.

In step S210, etching away the half-exposed photoresist;

In step S211, the exposed gate is etched away.

In step S212, the remaining photoresist is removed.

In step S213, the IMP ion-implants low-dose P doping to form N-.

Embodiment two

Please refer to FIG. 3. FIG. 3 is a schematic flow diagram of a method for manufacturing a polysilicon thin film transistor provided in Embodiment 2 of the present invention; it mainly includes the following steps:

In step S301, a glass substrate is provided, and a buffer layer and a polysilicon layer are sequentially formed on the glass substrate;

Please refer to FIG. 4 , which is a schematic structural diagram of sequentially forming a buffer layer and a polysilicon layer on a glass substrate according to an embodiment of the present invention. Firstly, a buffer layer 11 is formed on the glass substrate 10 , and then an amorphous silicon layer is formed on the buffer layer 11 ; an excimer laser annealing operation is performed on the amorphous silicon layer to form a polysilicon layer 12 .

In an embodiment of the present invention, the step of forming a polysilicon layer on the glass substrate includes:

forming an amorphous silicon layer on the buffer layer;

An excimer laser annealing operation is performed on the amorphous silicon layer to form a polycrystalline silicon layer.

In step S302, the IMP ion is implanted with a light dose of B doping to form a channel;

Please refer to FIG. 5 , which is a schematic structural diagram of ion implantation light dose B doping provided by an embodiment of the present invention. In this embodiment, under the condition that NTFT (N+) and PTFT (P+) are not defined, a small amount of boron is implanted by ion implantation process to adjust the voltage of TFT (Thin Film Transistor, thin film transistor). Specifically, a small amount of boron is implanted into the polysilicon on the entire glass substrate.

In step S303, coating a photoresist on the polysilicon layer, and exposing and etching the photoresist by using a half-tone mask;

Please refer to FIG. 6A and FIG. 6B , which are schematic structural diagrams of coating a photoresist on the polysilicon layer according to an embodiment of the present invention. Firstly, a photoresist 13 is coated on the polysilicon layer 12, and then, the photoresist 13 is exposed and etched using a half-tone mask. In this embodiment, Cmos is composed of NTFT (N+) and PTFT (P+) on a glass substrate. Therefore, when one of the TFTs is fabricated, the area of the other TFT needs to be blocked by photoresist. In this embodiment, the patterns of the active layer NTFT and PTFT are defined in one exposure and development of the halftone mask.

7A and 7B are structural schematic diagrams of etching away excess polysilicon provided by an embodiment of the present invention. In this embodiment, an etching process is adopted, and two kinds of TFTs on a glass substrate are simultaneously etched to remove excess polysilicon, thereby forming patterns of the active layer NTFT and PTFT.

8A and 8B are schematic structural diagrams of the half-exposed photoresist etched out according to an embodiment of the present invention. In this embodiment, an ashing process (photoresist etching) is used to uniformly thin the photoresist to form a photoresist pattern as shown in FIG. 8A and FIG. 8B .

In an embodiment of the present invention, the step of exposing and etching the photoresist by using a half-tone mask mask includes:

exposing the photoresist by using a halftone mask;

Etching away excess polysilicon;

The half exposed photoresist is etched away.

In step S304, IMP ion-implants high-dose P doping to form N+;

Please refer to FIG. 9A and FIG. 9B , which are schematic structural diagrams of ion implantation of high-dose P doping to form N+ according to an embodiment of the present invention. In this embodiment, the NTFT (N+) is formed by an ion implantation process. In this process, the PTFT (P+) region needs to be shielded by a photoresist to avoid ion implantation.

In step S305, removing the remaining photoresist;

Please refer to FIG. 10A and FIG. 10B , which are schematic diagrams of removing the remaining photoresist provided by the embodiment of the present invention. In this embodiment, all the photoresist on the NTFT and PTFT of the active layer is washed off by using the strip cleaning process, so far the regions of the NTFT and PTFT have been defined, and the N+ position of the NTFT region has been implanted with ions to form an N+ region.

In step S306, an insulating layer and a gate layer are sequentially formed on the entire surface of the glass substrate;

Please refer to FIG. 11A and FIG. 11B , which are schematic structural diagrams for forming an insulating layer and a gate layer according to an embodiment of the present invention. First, an insulating layer 14 is formed on the entire surface of the glass substrate 10 , and then a gate layer 15 is formed on the insulating layer 14 . In this embodiment, a chemical vapor deposition process is used to deposit an insulating film (insulation layer) on the entire glass substrate, and then a physical vapor deposition process is used to deposit a metal film (gate layer).

In an embodiment of the present invention, the step of forming an insulating layer on the entire surface of the glass substrate includes:

An insulating layer is deposited on the entire surface of the glass substrate by chemical vapor deposition.

The step of forming a gate layer on the entire surface of the glass substrate includes:

A gate layer is deposited on the insulating layer by physical vapor deposition.

In step S307, coating a photoresist on the gate layer, and exposing the photoresist by using a halftone mask;

Please refer to FIG. 12A and FIG. 12B , which are schematic structural diagrams of coating a photoresist on the gate layer according to an embodiment of the present invention. Firstly, a photoresist 16 is coated on the gate layer 15, and then, the photoresist 16 is exposed by using a half-tone mask. In this embodiment, the scanning line patterns of NTFT and PTFT are defined in one exposure and development of a halftone mask.

In step S308, etching off redundant gates;

Please refer to FIG. 13A and FIG. 13B , which are structural schematic diagrams of etching away redundant gates provided by an embodiment of the present invention. In this embodiment, an etching process is adopted, and scanning lines of two kinds of TFTs on a glass substrate are simultaneously etched to remove redundant metal films, thereby forming scanning line patterns of NTFTs and PTFTs.

In step S309, the IMP ion-implants high-dose B doping to form P+.

Please refer to FIG. 14A and FIG. 14B , which are schematic structural diagrams of ion implantation of high-dose B doping to form P+ according to an embodiment of the present invention. In this embodiment, the ion implantation process is used to form the PTFT (P+). In this process, the channel position of the NTFT (N+) region needs to be blocked by photoresist to avoid ion implantation (the NTFT region is not completely blocked because it needs to reduce the illumination once define all scanlines). Because N+ and P+ can neutralize and offset each other, the ion implantation dose of the PTFT this time is less than the ion implantation dose of the previous NTFT formation.

In the embodiment of the present invention, the dose of B is lower than the high dose of P, so as not to cause the disappearance of N+.

In step S310, etching away the half-exposed photoresist;

Please refer to FIG. 15A and FIG. 15B , which are schematic structural diagrams of etching half-exposed photoresist provided by an embodiment of the present invention. In this embodiment, an ashing process (photoresist etching) is used to uniformly thin the photoresist to form a photoresist pattern as shown in FIG. 15A and FIG. 15B .

In step S311, the exposed gate is etched away.

Please refer to FIG. 16A and FIG. 16B , which are structural schematic diagrams of etching away exposed gates provided by an embodiment of the present invention. In this embodiment, an etching process is used to further remove excess metal on both sides of the NTFT scan line to form the final scan line pattern of the NTFT.

In step S312, the IMP ion-implants low-dose P doping to form N-.

Please refer to FIG. 17A and FIG. 17B , which are schematic structural diagrams of ion implantation of low-dose P doping to form N − according to an embodiment of the present invention. In this embodiment, a self-align ion implantation process is used to form the N-position of the NTFT region, where the ion implantation dose of the process will strengthen the N+ and weaken the P+ region, so the dose will be much smaller than the ion implantation dose of the P+ region .

In step S313, the remaining photoresist is removed.

Please refer to FIG. 18A and FIG. 18B , which are schematic structural diagrams of removing the remaining photoresist provided by the embodiment of the present invention. In this embodiment, the strip process is used to wash off all the photoresist on the glass substrate, and thus the CMOS fabrication is completed.

To sum up, the present invention uses two half-tone masks to complete the definition of CMos (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) and gate, and form LDD. Therefore, the number of masks is reduced from 4 to 2, which greatly improves the competitiveness; therefore, the manufacturing method of the polysilicon thin film transistor provided by the present invention can effectively reduce the number of masks and reduce the cost.

While the invention has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. The present invention includes all such modifications and variations and is limited only by the scope of the appended claims. With particular reference to the various functions performed by the components described above, terminology used to describe such components is intended to correspond to any component that performs the specified function (eg, which is functionally equivalent) of the described component (unless otherwise indicated). , even if not structurally equivalent to the disclosed structures that perform the functions shown herein in the exemplary implementations of the specification. Furthermore, although a particular feature of this specification has been disclosed with respect to only one of several implementations, such feature may be combined with one or more other implementations as may be desirable and advantageous for a given or particular application. other feature combinations. Moreover, to the extent the terms "comprises", "has", "comprising" or variations thereof are used in the detailed description or the claims, such terms are intended to be encompassed in a manner similar to the term "comprising".

In summary, although the present invention has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present invention, and those of ordinary skill in the art can make various modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the claims.

Claims (9)

1. a fabrication method of polysilicon thin film transistor, is characterized in that, the fabrication method of described polysilicon thin film transistor comprises: A glass substrate is provided, and a buffer layer and a polysilicon layer are sequentially formed on the glass substrate; A small amount of boron is implanted by an ion implantation process to adjust the voltage of the TFT thin film transistor, wherein a small amount of boron is implanted in the polysilicon on the entire glass substrate; Coating a photoresist on the polysilicon layer, and exposing and etching the photoresist with a half-tone mask; defining the patterns of the active layer NTFT and PTFT in one exposure and development of the half-tone mask ; Ion implantation of high-dose P doping to form N+, so that the photoresist blocks a channel position of a region of the PTFT; sequentially forming an insulating layer and a gate layer on the entire surface of the glass substrate; Coating a photoresist on the gate layer, and exposing the photoresist with a half-tone mask; defining the scanning line patterns of NTFT and PTFT in one half-tone mask exposure and development; and Ion implantation of high-dose B doping to form P+, wherein the ion implantation dose of PTFT is less than the ion implantation dose of NTFT, so that the photoresist blocks a region of the channel position of NTFT, wherein the B The dose was lower than the high dose P. 2. The method for manufacturing a polysilicon thin film transistor according to claim 1, wherein the step of forming a polysilicon layer on the glass substrate comprises: forming an amorphous silicon layer on the buffer layer; and An excimer laser annealing operation is performed on the amorphous silicon layer to form a polycrystalline silicon layer. 3. The method for manufacturing a polysilicon thin film transistor according to claim 1 or 2, characterized in that, after the step of forming a polysilicon layer on the glass substrate, further comprising: Ion implantation light dose B doping to form a channel. 4. The method for manufacturing a polysilicon thin film transistor according to claim 1, wherein the step of exposing and etching the photoresist by using a half-tone mask mask comprises: exposing the photoresist by using a halftone mask; etching away excess polysilicon; and The half exposed photoresist is etched away. 5. The manufacturing method of polysilicon thin film transistor according to claim 1, characterized in that, after the ion implantation of high-dose P doping, after the step of forming N+, further comprising: The remaining photoresist is removed. 6. The manufacturing method of the polysilicon thin film transistor according to claim 1, characterized in that, coating a photoresist on the gate layer, and exposing the photoresist by using a half-tone mask mask After that, also include: Etch away excess gate. 7. The manufacturing method of polysilicon thin film transistor according to claim 1, characterized in that, after the ion implantation of high-dose B doping, after the step of forming P+, further comprising: etching away the half-exposed photoresist; etching away the exposed gate; and The remaining photoresist is removed. 8. The manufacturing method of polysilicon thin film transistor according to claim 7, characterized in that, after the step of removing the remaining photoresist, further comprising: Ion implantation low-dose P doping to form N-. 9. The manufacturing method of polysilicon thin film transistor according to claim 7, characterized in that, before the step of removing the remaining photoresist, further comprising: Ion implantation low-dose P doping to form N-.