CN108807281B - Semiconductor device and method of forming the same - Google Patents

Abstract

A semiconductor device and a method for forming the same, the method comprising: providing a semiconductor substrate, the semiconductor substrate includes a first region, a second region and a third region, the second region is located between the first region and the third region; first ion doping is performed on the bottom of the semiconductor substrate, a first well region is formed in the semiconductor substrate, and the first well region is doped with first ions; an initial gate layer covering the surface of the third region is formed on the semiconductor substrate; The semiconductor substrates in the second region and the third region are subjected to second ion doping, the first well region in the second region is inverted into the second well region, and the first well region in the third region is inverted into the first well region. In the triple well region, the second well region and the third well region are doped with second ions, the conductivity type of the second ions is opposite to that of the first ions, and the ion concentration of the second well region is greater than that of the third well region; A first gate structure is formed on the second well region; the initial gate layer is etched to form a second gate structure on the third well region. The method reduces the number of masks and costs.

Description

Semiconductor device and method of forming the same

technical field

The present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a method for forming the same.

Background technique

With the continuous advancement of semiconductor technology, the integration level of semiconductor devices is continuously improved, which requires that more transistors can be formed on a chip.

Threshold voltage is an important property of a transistor and has a significant impact on the performance of the transistor. Transistors with different functions often have different requirements on threshold voltages, and in the process of forming different transistors, the threshold voltages of different transistors need to be adjusted.

In order to adjust the threshold voltage of different transistors, the channel region of the transistor is doped to form a threshold voltage adjustment region. The concentration of threshold voltage adjusting ions of the high threshold voltage transistor is lower than the concentration of threshold voltage adjusting ions of the low threshold voltage transistor. The threshold voltage of a transistor can be adjusted by forming different concentrations of threshold voltage adjusting ions in different transistors.

However, the multi-threshold voltage transistors formed in the prior art are complicated in process flow, the patterning process is used many times, and the cost is high.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, which can simplify the process flow, reduce the usage times of the patterning process, and reduce the cost.

In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor device, including: providing a semiconductor substrate, the semiconductor substrate includes a first region, a second region and a third region, and the second region is located in the between the first region and the third region; first ion doping is performed on the first region, the second region and the third region of the semiconductor substrate, in the first region, the second region and the third region A first well region is formed in the semiconductor substrate, and the first well region is doped with first ions; an initial gate layer is formed on the third region of the semiconductor substrate; after the initial gate layer is formed, the The semiconductor substrates in the second region and the third region are subjected to second ion doping, the first well region in the second region is inverted into the second well region, and the first well region in the third region is inverted into the third well region a well region, the second well region and the third well region are doped with second ions, the conductivity type of the second ions is opposite to that of the first ions, and the doping concentration of the second ions in the second well region is greater than that of the third well region the second ion doping concentration in the region; a first gate structure is formed on the semiconductor substrate, and at least one first gate structure is located on the second well region; after the first gate structure is formed, the initial gate layer is etched , forming a second gate structure on the third well region.

Optionally, the types of devices formed in the first region, the second region and the third region are different;

Optionally, the second ion doping method includes: performing a first ion implantation, where the depth of the first ion implantation is less than the thickness of the initial gate layer; after the first ion implantation, performing a second ion implantation Ion implantation, the depth of the second ion implantation is greater than the thickness of the initial gate layer.

Optionally, the second ion doping method further includes: after the second ion implantation, at least one third ion implantation is performed, and the depth of the third ion implantation is greater than the thickness of the initial gate layer .

Optionally, the implanted ion dose of the first ion implantation is greater than the implanted ion dose of the second ion implantation.

Optionally, the implanted ion dose of the third ion implantation is greater than the implanted ion dose of the second ion implantation.

Optionally, the implanted ion energy of the second ion implantation is greater than the implanted ion energy of the first ion implantation.

Optionally, the implanted ion dose of the third ion implantation is greater than the implanted ion dose of the second ion implantation.

Optionally, the material of the initial gate layer includes: polysilicon, amorphous silicon, microcrystalline silicon, amorphous germanium or metal gate material.

Optionally, before the second ion doping, the method further includes forming a first mask layer on the surface of the first well region; using the initial gate layer and the first mask layer as masks to perform masking on the semiconductor substrate in the second region. The second ion doping.

Optionally, the first ion doping process includes an ion implantation process or a solid state source doping process.

Optionally, after the first ion doping and before forming the initial gate layer, the method further includes: forming a gate dielectric layer on the surfaces of the first region, the second region and the third region of the semiconductor substrate, the initial gate layer on the surface of the gate dielectric layer.

Optionally, the method for forming the first gate structure includes: removing the gate dielectric layer on the surface of the second well region to expose the surface of the second well region; forming a first gate dielectric layer on the surface of the second well region; A first gate film is formed on the surface of a gate dielectric layer; a second mask layer is formed on the surface of the first gate film, and the second mask layer is used as a mask to etch the first gate film; A first gate layer is formed on the surface of the two well regions to form the first gate structure.

Optionally, the method for forming the second gate structure includes: after forming the first gate structure, etching the initial gate layer and the gate dielectric layer, and forming a second gate structure on the third well region .

Optionally, it further includes: forming a fourth well region in the semiconductor substrate of the first region, the fourth well region is adjacent to the first well region, and the fourth well region has first ions, so The ion concentration in the fourth well region is higher than the ion concentration in the first well region.

Optionally, the method for forming the fourth well region includes: before performing the second ion doping, performing third ion doping in part of the semiconductor substrate of the first region and the second region, and performing third ion doping in the first region A fourth well region is formed.

Optionally, the method further includes: forming the second gate structure on the first well region, and forming the first gate structure on the fourth well region.

Correspondingly, the present invention also provides a semiconductor device formed by any one of the above methods.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In the method for forming a semiconductor device provided by the technical solution of the present invention, the first region, the second region and the third region of the semiconductor substrate are doped with the first ions by the first ion doping, and the first region, the second region and the third region of the semiconductor substrate are doped with the first ions. A first well region is formed in the second region and the third region; the second region and the third region of the semiconductor substrate are doped with second ions. The ion conductivity types are opposite, so that the semiconductor substrates in the second region and the third region realize inversion. At this time, the first region of the first semiconductor substrate needs to be protected, and a patterning process is required; at the same time, the initial gate layer is used as the second ion doping The second well region in the second region of the semiconductor substrate and the third well region in the third region of the semiconductor substrate are used by using the height difference of the initial gate layer. The formation of the initial gate layer requires a patterning process; The doped ion conductivity type of one well region is different from that of the second well region and the third well region, the doped ion conductivity type of the second well region and the third well region is the same, the second well region It is different from the doping ion concentration of the well region of the third well region, so only two patterning processes are required to form the first well region, the second well region and the third well region, and the first gate structure is formed on the second well region and the second gate structure on the third well region each requires a patterning process, which reduces the number of patterning processes, causes less damage to the semiconductor substrate, simplifies the process flow, and improves the performance of the semiconductor device. , optimize the process flow.

Further, the semiconductor device further includes a fourth well region, using the initial gate layer as a mask, and forming the fourth well region through the third ion implantation; using the first mask layer as a mask, performing the second ion implantation to form the fourth well region The second well region and the third well region; therefore, the formation of the four well regions requires two masks, and two patterning processes are performed, which reduces the number of patterning times, causes less damage to the semiconductor substrate, and saves the process. The process improves the performance of semiconductor devices and optimizes the process flow.

Description of drawings

1 is a schematic structural diagram of a semiconductor device;

2 to 14 are schematic structural diagrams of a semiconductor device forming process in an embodiment of the present invention.

Detailed ways

As mentioned in the background, prior art semiconductor devices have poor performance.

FIG. 1 is a schematic structural diagram of a semiconductor device.

1, a semiconductor substrate 100, a first well region 111, a second well region 112, a third well region 113 and a fourth well region 114 located in the semiconductor substrate 100, the first well region 111 and the second well region 114 The well region 112 has first trap ions, the ion concentration of the first well region 111 is greater than that of the second well region 112, the third well region 113 and the fourth well region 114 have second trap ions, the second The trap ions have opposite conductivity types to the first trap ions, and the ion concentration of the third well region 113 is greater than that of the fourth well region 114; the first gate structure is located on the first well region; a second gate structure on the second well region; a third gate structure on the third well region; and a fourth gate structure on the fourth well region.

Wherein, the first well region is used to form a low threshold voltage PMOS transistor; the second well region is used to form a high threshold voltage PMOS transistor; the third well region is used to form a low threshold voltage NMOS transistor; The quad well region is used to form a high threshold voltage NMOS transistor.

When forming the first well region 111 , the second well region 112 , the third well region 113 and the fourth well region 114 in the semiconductor substrate 100 , during the formation of each well region, a patterning needs to be formed once. Four patterning steps are required to form four well regions. Four gate structures are respectively formed on the four well regions, and each of the gate structures includes a gate dielectric layer and a gate layer. In order to form gate dielectric layers with different thicknesses in different regions, the material layer for forming the gate dielectric layers needs to be patterned at least once. In order to form gate layers on different gate dielectric layers respectively, at least one patterning is required, and at least six patterns are required in the semiconductor formation process. Excessive patterning process is complicated, and the semiconductor substrate is etched. Too much etch, resulting in poor semiconductor device formation.

In the embodiment of the present invention, the doping concentration of different well regions is different by using the initial gate layer as a mask, and at the same time as the material layer of the subsequent gate structure, the method has less patterning times and less damage to the semiconductor substrate. The performance of the semiconductor device is improved and the process is simplified.

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

2 to 14 are schematic structural diagrams of a semiconductor device forming process in an embodiment of the present invention.

Referring to FIG. 2 , a semiconductor substrate 200 is provided.

The semiconductor substrate 200 includes a first area A, a second area B and a third area C, the second area B is located between the first area A and the third area C; The device types formed by the second region B and the third region C are different.

When the first area A is used to form P-type devices, the second area B and the third area C are used to form N-type devices; when the first area A is used to form N-type devices, the second area B and the third area C are used to form N-type devices. Region B and third region C are used to form P-type devices.

In this embodiment, the first region A is used to form N-type devices, and the second region B and the third region C are used to form P-type devices.

In one embodiment, the first region A is used to form P-type devices, and the second region B and the third region C are used to form N-type devices.

In this embodiment, the material of the semiconductor substrate 200 is single crystal silicon. The semiconductor substrate 200 may also be polysilicon or amorphous silicon. The material of the semiconductor substrate 200 may also be semiconductor materials such as germanium, silicon germanium, and gallium arsenide. The semiconductor substrate 200 can also be a semiconductor-on-insulator structure, and the semiconductor-on-insulator structure includes an insulator and a semiconductor material layer on the insulator, and the material of the semiconductor material layer includes silicon, germanium, silicon germanium, gallium arsenide or gallium arsenide. Indium Gallium Arsenide and other semiconductor materials.

Continuing to refer to FIG. 2 , first ion doping is performed on the semiconductor substrate 200 to form a first well region 211 in the first region A, the second region B and the third region C, and the doping ions are the first ion.

The first ion doping provides dopant ions for forming the first well region and the subsequent fourth well region.

When the first region A is used to form an N-type device, the first ions are P-type ions, and the first ions include: boron ions, BF ^2- ions or indium ions.

When the first region A is used to form a P-type device, the first ions are N-type ions, and the first ions include phosphorus ions, arsenic ions or antimony ions.

In this embodiment, the first region A is used to form an N-type device, and the first ions are boron ions.

In one embodiment, the first region A is used to form a P-type device, and the first ions are phosphorus ions.

The first ion doping process includes an ion implantation process or a solid state source doping process.

In this embodiment, the first ion doping process is an ion implantation process, and the ion implantation parameters include: the implanted ions are boron ions, the implantation energy is 100KeV to 200KeV, the implantation depth is 0.3 μm to 0.6 μm, and the implantation dose The range is 5.0×10 ¹² atom/cm ² to 5.0×10 ¹³ atom/cm ² .

Referring to FIG. 3 , an initial gate material layer 240 is formed on the semiconductor substrate 200 ; a patterned layer 205 is formed on the initial gate material layer 240 .

The patterned layer 205 covers part of the surface of the initial gate material layer 240 .

The patterned layer 205 is a mask layer for forming an initial gate layer.

The material of the patterned layer 205 includes photoresist.

In this embodiment, before forming the initial gate layer material layer 240 , the method further includes: forming a gate dielectric layer 241 on the surface of the semiconductor substrate 200 , and the initial gate layer material layer 240 is located on the surface of the gate dielectric layer 241 .

The material of the gate dielectric layer 241 includes: silicon oxide, silicon oxynitride or high dielectric constant material.

The gate dielectric layer 241 provides material for the gate dielectric layer of the second gate structure to be formed subsequently, and serves as a protective layer during ion implantation.

Referring to FIG. 4 , the initial gate material layer 240 is etched using the patterned layer 205 as a mask, and an initial gate layer 242 is formed on the surface of the semiconductor substrate 200 , and the initial gate layer 242 covers the semiconductor substrate of the third region. bottom surface.

In this embodiment, the initial gate layer 241 also covers part of the surface of the semiconductor substrate in the first region A. As shown in FIG.

The initial gate layer 242 provides a gate layer for the subsequent formation of the second gate structure, and serves as a mask layer for the subsequent second ion doping and third ion doping.

The material of the initial gate layer 242 includes: polysilicon, amorphous silicon, microcrystalline silicon, amorphous germanium or metal gate material.

The metal gate material includes: aluminum, tantalum, tungsten, tantalum nitride or titanium nitride.

In this embodiment, the material of the initial gate layer 242 is polysilicon.

The thickness of the initial gate layer 242 is 0.1 μm to 0.2 μm.

The thickness of the initial gate layer 242 determines the depth of the implanted ions in the subsequent first ion implantation, the second ion implantation and the third ion implantation, and the implanted ion depth of the first ion implantation is smaller than the thickness of the initial gate layer. , the depth of the second ion implantation and the third ion implantation need to be larger than the thickness of the initial gate layer. If the thickness of the initial gate layer 242 is too low, the quality of the first ion implantation cannot be guaranteed; if the thickness of the initial gate layer 242 is too thick, the implanted ion energy of the second ion implantation and the third ion implantation needs to be too high, and the process is difficult. In addition, the damage to the semiconductor substrate is relatively large, which is not conducive to the performance of the device.

In this embodiment, a barrier layer is also formed on the surface of the initial gate layer 242, and the barrier layer serves as a barrier layer during ion implantation and a stop layer for subsequent etching.

The material of the barrier layer includes: silicon nitride, silicon nitride carbide, silicon boron nitride, silicon oxycarbide or silicon oxynitride.

In this embodiment, the material of the barrier layer is silicon nitride.

In other embodiments, the barrier layer is not formed on the surface of the initial gate layer 242 .

In this embodiment, the method further includes: forming a fourth well region in the semiconductor substrate 200 of the first region A, the fourth well region is adjacent to the first well region, and the fourth well region has a fourth well region. an ion.

In this embodiment, the first well region is used to form a low threshold voltage PMOS transistor; the second well region is used to form a high threshold voltage PMOS transistor; the third well region is used to form a low threshold voltage NMOS transistor; The fourth well region is used to form a high threshold voltage NMOS transistor.

Referring to FIG. 5 , after the initial gate layer 242 is formed, a fourth well region 214 is formed in the semiconductor substrate 200 of the first region A.

The method for forming the fourth well region 214 includes: doping part of the semiconductor substrate of the first region A and the second region B with third ions, where the doping ions are first ions and are in the first region A A fourth well region 214 is formed.

The third ion doping process includes an ion implantation process or a solid state source doping process.

In this embodiment, the third ion doping process is an ion implantation process.

Specifically, using the initial gate layer 242 as a mask, a third ion doping is performed on the semiconductor substrate of part of the first region A and the second region B, and the third ion doping is the threshold voltage of the fourth well region 214 Ion doping.

The depth of the third ion implantation is smaller than the thickness of the initial gate layer 242, and the depth of the ion implantation is controlled so that the ions doped by the third ions cannot reach the first well region 211 located under the initial gate layer 242, and only in the first well region 211. Doping regions are formed in the exposed first well region 211 of the region A and in the first well region 211 of the second region B.

After the third ion doping, a fourth well region 214 is formed in the first region A, and the ion concentration of the fourth well region 214 is higher than that of the first well region 211; in the second region B A middle second well region 202 is formed therein, and the ion concentration of the middle second well region 202 is equal to the ion concentration of the fourth well region 214 , and is greater than the ion concentration of the first well region 211 .

The semiconductor devices formed by the first well region 211 and the fourth well region 214 are of the same type but have different functions.

In this embodiment, the first well region 211 is used to form a high threshold voltage semiconductor device, and the fourth well region 214 is used to form a low threshold voltage semiconductor device.

The dopant ion concentration of the well region of the high threshold voltage semiconductor device is lower than the dopant ion concentration of the well region of the low threshold voltage semiconductor device.

The third ion doping is the threshold voltage ion doping of the fourth well region, which forms the threshold voltage adjustment region of the fourth well region.

In this embodiment, the first region A is used to form an N-type device, and the first ions are boron ions.

In this embodiment, the third ion doping process includes an ion implantation process, and the parameters of the ion implantation include: the implanted ions are boron ions, the implantation energy is 10KeV to 30KeV, the implantation depth is 0.03 μm to 0.1 μm, and the implantation dose range is It is 1.0×10 ¹² atom/cm ² to 1.0×10 ¹³ atom/cm ² .

After forming the first well region 211 and the fourth well region 214, a second well region is formed in the second region B of the semiconductor substrate 200, and a third well region is formed in the third region C of the semiconductor substrate 200, and the second well region is and the method for forming the third well region includes: after forming the initial gate layer 242, second ion doping is performed on the semiconductor substrate 200 of the second region B and the third region C, A well region inversion is the second well region 212, and the first well region 211 in the third region C is inverted into a third well region 213. The second well region 212 and the third well region 213 are doped with the For two ions, the conductivity type of the second ions is opposite to that of the first ions, and the second ion doping concentration of the second well region 212 is greater than the second ion doping concentration of the third well region 213 .

The second ion doping process includes an ion implantation process.

The method for the second ion doping includes: performing a first ion implantation, where the depth of the first ion implantation is smaller than the thickness of the initial gate layer 242; after the first ion implantation, performing a second ion implantation, The depth of the second ion implantation is greater than the thickness of the initial gate layer 242 .

The second ion doping method further includes: after the second ion implantation, at least one third ion implantation is performed, and the depth of the third ion implantation is greater than the thickness of the initial gate layer.

For specific methods of forming the second well region 212 and the third well region 213 , please refer to FIGS. 6 to 8 .

Referring to FIG. 6 , after the first well region 211 and the fourth well region 214 are formed, the first ion implantation is performed on the semiconductor substrate 200 in the second region B by using the initial gate layer 242 as a mask. is a second ion of opposite conductivity type to the first ion.

Specifically, the first ion implantation is performed on the middle second well region 202 by using the initial gate layer 242 as a mask, so that part of the middle second well region 202 is inverted, and a second region B is formed in the semiconductor substrate 200 of the second region B. A doped region 207 .

In this embodiment, before the first ion implantation, the method further includes: forming a first mask layer 206 on the semiconductor substrate of the first region A, the first mask layer 206 covering the surface of the first well region 211 Initial gate layer 242 .

The first mask layer 206 is a mask layer doped with second ions, and protects the first well region 211 and the fourth well region 214 when the second ion is doped.

The material of the first mask layer 206 is photoresist.

In one embodiment, the first mask layer 206 is not formed, and selective ion implantation is used to perform ion implantation on the semiconductor substrate 200 in the second region B.

The conductive ion type of the first doped region 207 is the same as the second ion conductivity type.

The first ion implantation is the threshold voltage ion implantation of the second well region, which is to form the threshold voltage region of the second well region.

The type of the semiconductor device formed in the second region B is different from that of the semiconductor device formed in the first region A, and the well region in the first region A and the well region in the second region B have different types of doped ions.

When the conductivity type of the first ion is N type, the conductivity type of the second ion is P type, and the second ion includes phosphorus ion, arsenic ion or antimony ion.

When the conductivity type of the first ion is P type, the conductivity type of the second ion is N type, and the second ion includes: boron ion, BF ^2- ion or indium ion.

In this embodiment, the first region A is used to form an N-type device, the first ions are boron ions, the type of the second ions is N-type ions, and the second ions are phosphorus ions.

In one embodiment, the first region A is used to form a P-type device, the first ions are phosphorus ions, the type of the second ions is P-type ions, and the second ions are boron ions.

In this embodiment, the dopant ions in the middle second well region 202 are phosphorus ions, and the conductivity type of the dopant ions in the middle second well region 202 is P-type. The implanted ions of the first ion implantation are second ions, and the conductivity type of the second ions is N-type ions. Part of the ions are counter-doped, so that the conductivity type of the doped ions in the first doped region 207 in the middle second well region 202 is N-type.

Since the initial gate layer 241 is located on the surface of the third region C of the semiconductor substrate 200, during the first ion implantation, the depth of the first ion implantation is controlled so that the implanted ions of the first ion implantation cannot reach the semiconductor substrate 200. On the surface of the three regions C, the first doped region 207 is only formed in the middle second well region 202 .

The parameters of the first ion implantation include: the implanted ions are arsenic ions, the implantation energy is 30KeV to 150KeV, the implantation depth is 0.02 μm to 0.08 μm, and the implantation dose range is 5.0×10 ¹² atom/cm ² ～5.0×10 ¹³ atom /cm ² .

Referring to FIG. 7 , after the first ion implantation, a second ion implantation is performed on the semiconductor substrate 200 in the second region B and the third region C, and the implanted ions are second ions.

The second ion implantation is the threshold voltage ion implantation of the third well region, which is to form the threshold voltage region of the third well region.

Specifically, the second ion implantation is performed on the middle second well region 202 and the first well region 211 in the third region C, so that part of the first well region 211 in the third region C A third doped region 209 is formed in the semiconductor substrate of B, and at the same time, part of the middle second well region 202 is inverted, and a second doped region 208 is formed in the semiconductor substrate of the second region B.

The third doping region 209 is a threshold voltage doping region of the third well region.

The conductive ion type of the third doped region 209 is the same as that of the second ion conductivity type.

The conductivity ion type of the second doped region 208 is the same as the second ion conductivity type.

In this embodiment, the dopant ions in the first well region 211 in the third region C are phosphorus ions, and the conductivity type of the dopant ions in the first well region 211 in the third region C is P-type. The implanted ions of the second ion implantation are second ions, and the conductivity type of the second ions is N-type ions. Part of the ions in the first well region 211 in the region C is counter-doped, so that part of the first well region 211 in the third region C is inversion, forming a third doping region 209, and the doping of the third doping region 209 The ionic conductivity type is N-type.

The second ion implantation is performed on the middle second well region 202, that is, part of the ions in the middle second well region 202 are continuously counter-doped, so that the second doping region 208 in the semiconductor substrate of the second region B is not doped. The conductivity type of the dopant ions is N-type.

The first doping region 207 is a threshold voltage doping region in the second well region formed subsequently, and the third doping region 209 is a threshold voltage doping region in the third well region formed subsequently.

The semiconductor devices formed by the second well region and the third well region are of the same type, but have different functions.

In this embodiment, the second well region is used to form a low threshold voltage semiconductor device, and the third well region is used to form a high threshold voltage semiconductor device.

The dopant ion concentration of the well region of the high threshold voltage semiconductor device is lower than the dopant ion concentration of the well region of the low threshold voltage semiconductor device.

The implanted ion dose of the first ion implantation is greater than the implanted ion dose of the second ion implantation, so that the second ion concentration of the first doped region 207 is greater than the second ion concentration of the third doped region 209 .

The implanted ion depth of the second ion implantation is higher than the thickness of the initial gate layer, so that the second ions enter into the middle third well region 203 .

The implanted ion energy of the second ion implantation is greater than the implanted ion energy of the first ion implantation, so that the implanted ions of the second ion implantation penetrate the initial gate layer and reach the middle third well region.

The parameters of the second ion implantation include: the implanted ions are phosphorus ions, the implantation energy is 100KeV to 300KeV, the implantation depth is 0.03 μm to 0.07 μm, and the implantation dose range is 1.0×10 ¹² atom/cm ² ～1.0×10 ¹³ atom /cm ² .

Referring to FIG. 8 , after the second ion implantation, a third ion implantation is performed on the semiconductor substrate 200 in the second region B and the third region C, the implanted ions are second ions, and the intermediate second well The region 202 is inverted to be the second well region 212 , and the first well region 211 in the third region C is inverted to be the third well region 213 .

The third ion implantation is a well implantation for forming the second well region 212 and the third well region 213 , and the well ion conductivity type of the second well region 212 and the third well region 213 is the same as the second ion conductivity type.

In this embodiment, the dopant ions of the first well region 211 in the third region C are phosphorus ions, and the conductivity type of the dopant ions of the first well region 211 in the third region C is P-type. The implanted ions of the third ion implantation are second ions, the conductivity type of the second ions is N-type ions, and the second ions are boron ions.

The third ion implantation is performed on the semiconductor substrate 200 in the second region B and the third region C, that is, the ions in the middle second well region 202 and the first well region 211 in the third region C are counter-doped, so that The conductivity type of the doped ions of the semiconductor substrate 200 in the second region B is N-type, forming the second well region 212; the conductivity type of the doped ions of the semiconductor substrate 200 in the third region C is N-type, forming the third well region District 213.

The implanted ion depth of the third ion implantation is higher than the thickness of the initial gate layer 242 , so that the second ions enter into the first well region 211 of the third region C.

The third ion implantation may be multiple ion implantations.

The third ion implantation parameters include: the implanted ions are phosphorus ions, the implantation energy is 400KeV to 600KeV, the implantation depth is 0.05μm to 1.2μm, and the implantation dose range is 1.0×10 ¹³ atom/cm ² ～1.0×10 ¹⁴ atom/cm ² .

The implanted ion energy of the third ion implantation is greater than the implanted ion energy of the second ion implantation, so that the implanted ions of the third ion implantation can reach the middle second well region 202 below the second doping region 208 , and in the first well region 211 of the third region C below the third doped region 209 .

After the second well region 212 and the third well region 213 are formed, the first mask layer 206 is removed,

The process of removing the first mask layer 206 is an ashing process or a wet process.

The first well region 211 , the fourth well region 214 , the second well region 212 and the third well region 213 are formed, the mask layer is only formed twice, and the patterning process is performed twice, which causes less damage to the semiconductor substrate At the same time, the process flow is saved, the performance of the semiconductor device is improved, and the process flow is optimized.

After forming the first well region 211, the fourth well region 214, the second well region 212 and the third well region 213, a first gate structure is formed on the semiconductor substrate, and at least one first gate structure is located in the second well region on; after the first gate structure is formed, the initial gate layer is etched, and a second gate structure is formed on the third well region.

In this embodiment, the method further includes: forming the second gate structure on the first well region, and forming the first gate structure on the fourth well region.

In other embodiments, the first gate structure is formed on the first well region; the second gate structure is formed on the second well region; the third gate structure is formed on the third well region; A fourth gate structure is formed.

After the second well region 212 and the third well region 213 are formed, a second gate structure is formed on the surface of the second well region.

Referring to FIG. 9, after forming the second well region 212 and the third well region 213, the gate dielectric layer 241 on the surface of the second well region 212 is removed; the first gate dielectric layer 251 is formed on the surface of the second well region 212, A first gate film 252 is formed on the surface of the gate dielectric layer 251 , and the first gate film 252 also covers the top surface of the initial gate layer 242 .

In this embodiment, the second well region 212 is used to form a low threshold voltage P-type semiconductor device, and the third well region 213 is used to form a high threshold voltage P-type semiconductor device.

Since the voltage of the high threshold voltage semiconductor device is higher, in order to ensure the performance of the device, the gate dielectric layer of the high threshold voltage semiconductor device is thicker than that of the low threshold voltage semiconductor device.

In this embodiment, the second well region 212 is used to form a low threshold voltage semiconductor device, the third well region 213 is used to form a high threshold voltage semiconductor device, and the thickness of the gate dielectric layer of the first gate structure is lower than that of the first gate structure. The thickness of the gate dielectric layer of the two gate structures requires that the gate dielectric layer of the first gate structure be formed on the surface of the second well region 212 .

The method for forming the first gate dielectric layer 251 includes: removing the gate dielectric layer 241 on the surface of the second well region 212 to expose the top surface of the second well region 212; using an oxidation process to form a first gate on the surface of the second well region 212 Dielectric layer 251 .

In this embodiment, the semiconductor substrate 200 further includes a first well region 211 and a fourth well region 214, the first well region is used for forming a high threshold voltage N-type semiconductor device, and the fourth well region 214 is used for forming a low threshold voltage N-type semiconductor device The second well region 212 and the fourth well region 214 are used to form a low threshold voltage semiconductor device, and the first well region 211 and the third well region 213 are used to form a high threshold voltage semiconductor device.

In this embodiment, the gate dielectric layer on the surface of the second well region 212 is removed at the same time as the gate dielectric layer on the surface of the fourth well region 214 is removed to expose the top surface of the fourth well region 214; The first gate dielectric layer 251 is formed on the surface of the fourth well region 214 while the first gate dielectric layer is formed, and the first gate dielectric layer located on the surface of the fourth well region 214 is the gate dielectric layer of the fourth gate structure.

In this embodiment, the surface of the initial gate layer 242 has a barrier layer, and the barrier layer can protect the top of the initial gate layer from being oxidized, but the sidewalls of the initial gate layer 242 are oxidized to form an oxide layer.

In other embodiments, the barrier layer is not formed on the surface of the initial gate layer 242, while the first gate dielectric layer is formed by oxidation, the top surface and sidewall surface of the initial gate layer 242 above the first well region and the third well region are formed. An oxide layer will also be formed, and the oxide layer will serve as an etch stop layer when the first gate film 252 is subsequently etched to protect the initial gate layer 242 .

Referring to FIG. 10 , after the first gate film 252 is formed, a second mask layer 260 is formed on the surface of the first gate film 252 , and the second mask layer 260 covers part of the first gate on the surface of the second well region 212 the surface of the polar film 252 .

In this embodiment, the second mask layer 260 covers part of the surface of the first gate film 252 on the surface of the fourth well region 214 .

The second mask layer 260 provides a mask layer for the subsequent formation of the first gate structure and the fourth gate structure.

The material of the second mask layer 260 includes: photoresist.

The process of forming the second mask layer 260 includes: forming an initial second mask layer (not shown) by spin coating on the semiconductor substrate 200 , the initial second mask layer covering the first gate film 252 surface; exposing the initial second mask layer, the exposure template during the exposure process exposes part of the initial second mask layer, and developing the exposed initial second mask layer to expose the first mask layer. A portion of the surface of the gate film 252 forms the second mask layer 260 .

Referring to FIG. 11 , the first gate film 252 and the first gate dielectric layer 251 are etched using the first mask layer 260 as a mask until the top surface of the second well region 212 is exposed. A first gate structure is formed on the surface of the second well region 212 .

In this embodiment, the fourth well region 214 is also included, the first gate film 252 and the first gate dielectric layer 251 are also located on the surface of the fourth well region 214 , and the first mask layer 260 is also located on the fourth well region 214 the surface of the first gate film 252 .

Using the first mask layer 260 as a mask to etch the first gate film 252 and the first gate dielectric layer 251 to form the first gate structure, the first gate structure on the surface of the fourth well region is also etched. The gate film 252 and the first gate dielectric layer 251 form a first gate structure on the surface of the fourth well region 214, and at the same time, the surface of the initial gate layer 242 of the first well region 211 and the third well region 213 is removed by etching. The first gate film 252 exposes the surface of the barrier layer on top of the initial gate layer 242 .

In other embodiments, the barrier layer is not formed, the first gate film 252 on the surface of the initial gate layer 242 of the first well region 211 and the third well region 213 and the oxide layer on the surface of the initial gate layer 242 are removed by etching, exposing the The top surface of the initial gate layer 242 .

Referring to FIG. 12 , after the first gate structure is formed, a third mask layer 270 is formed on the semiconductor substrate, and the third mask layer 270 covers part of the top surface of the initial gate layer 242 .

The third mask layer 270 also covers the sidewalls and the top surface of the first gate structure.

The third mask layer 270 is a mask layer for the subsequent formation of the second gate structure.

The material of the third mask layer 270 includes photoresist.

The process of forming the third mask layer 270 includes: forming an initial third mask layer (not shown) by spin coating on the semiconductor substrate 200, the initial third mask layer covering the side of the first gate structure The wall and top surfaces and the top and sidewall surfaces of the initial gate layer 242; the initial third mask layer is subjected to exposure treatment, and the exposure template during the exposure process exposes part of the initial third mask layer, and the exposed third mask layer is exposed. The initial third mask layer is developed to expose part of the surface of the initial gate layer 242 to form the third mask layer 270 .

Referring to FIG. 13 , using the third mask layer 270 as a mask, the initial gate layer 242 and the gate dielectric layer 241 on the surface of the third well region 213 are etched until a part of the top surface of the third well region 213 is exposed. A second gate structure is formed on the surface of the third well region 213 .

In this embodiment, the initial gate layer 242 is also located on the surface of the first well region, the third mask layer 270 is also located on the surface of the initial gate layer 242 of the second well region, and the initial gate layer on the surface of the third well region is etched Layer 242 and gate dielectric layer 241 also etch the initial gate layer 242 and gate dielectric layer 241 on the surface of the first well region 211, exposing part of the surface of the first well region 211, and forming a second gate on the surface of the first well region 211 Extreme structure.

In this embodiment, the surface of the initial gate layer 242 has a barrier layer. Before etching the initial gate layer 242 and the gate dielectric layer 241 on the surface of the third well region 213 , the barrier layer on the surface of the initial gate layer 242 is also etched.

In this embodiment, both the first well region and the third well region are used to form a low threshold voltage semiconductor device, and the second gate structure is formed in the same process, which can save process flow.

Since the initial gate layer is the material layer of the second gate structure and the gate layer of the first gate structure, in the process of forming the first gate structure and the second gate structure, only two masks need to be formed, using The initial gate layer is a mask, and the fourth well region is formed by the third ion implantation; the second ion implantation is performed by using the first mask layer as a mask to form the second well region and the third well region; therefore, the first well is formed The mask region, the second well region, the third well region and the fourth well region need to be masked twice. Therefore, to form four well regions and four gate structures respectively located on the four well regions in the semiconductor substrate, it is necessary to Four times of masking and four times of patterning are performed, which reduces the number of patterning processes, causes less damage to the semiconductor substrate, saves the process flow, improves the performance of the semiconductor device, and optimizes the process flow.

Referring to FIG. 14 , after the second gate structure is formed, spacers are formed on the sidewalls of the first gate structure and the second gate structure, and the spacers cover the sidewalls of the first gate structure and the second gate structure sidewalls; after forming the sidewalls, a second source-drain doped region is formed in the semiconductor substrate 200 on both sides of the first gate structure; a third source is formed in the semiconductor substrate 200 on both sides of the second gate structure Drain doped region.

The method for forming the spacers includes: forming a spacer material layer on the semiconductor substrate 200, the spacer material layer covering the sidewalls and the top surface of the first gate structure and the sidewalls and the top of the second gate structure surface; etch back the spacer material layer until the top surface of the semiconductor substrate 200 is exposed, and form the spacer on the sidewalls of the first gate structure and the second gate structure.

In this embodiment, the method further includes: forming a first source-drain doped region in the semiconductor substrate 200 on both sides of the second gate structure of the first well region 211 ; A fourth source-drain doped region is formed in the side semiconductor substrate 200 .

Before forming the sidewall spacers, it also includes lightly doping the second well region 212 and the third well region 213, forming a second lightly doped region on both sides of the first gate structure on the second well region 212, and forming a second lightly doped region on the third well region 212. A third lightly doped region is formed on both sides of the second gate structure on the well region 213 .

In this embodiment, the first well region 211 and the fourth well region 214 are lightly doped, and the first lightly doped is formed in the semiconductor substrate 200 on both sides of the second gate structure on the first well region 211 A fourth lightly doped region is formed in the semiconductor substrate 200 on both sides of the first gate structure on the fourth well region 214 .

Correspondingly, this embodiment also provides a semiconductor device formed by the above method.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (16)

1. A method of forming a semiconductor device for forming a multiple threshold voltage transistor device, comprising:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region, a second region and a third region, and the second region is positioned between the first region and the third region;

carrying out first ion doping on a first region, a second region and a third region of the semiconductor substrate, and forming a first well region in the first region, the second region and the third region of the semiconductor substrate, wherein first ions are doped in the first well region;

forming an initial gate layer on the third region of the semiconductor substrate;

after the initial gate layer is formed, carrying out second ion doping on the semiconductor substrate of the second region and the semiconductor substrate of the third region, inverting a first well region in the second region into a second well region, inverting the first well region in the third region into a third well region, and doping second ions in the second well region and the third well region, wherein the conductivity type of the second ions is opposite to that of the first ions, and the second ion doping concentration of the second well region is greater than that of the third well region;

forming first gate structures on the semiconductor substrate, wherein at least one first gate structure is positioned on the second well region;

after the first grid structure is formed, etching the initial grid layer, and forming a second grid structure on the third well region;

the second ion doping method comprises the following steps: carrying out first ion implantation, wherein the depth of the first ion implantation is less than the thickness of the initial gate layer; after the first ion implantation, performing second ion implantation, wherein the depth of the second ion implantation is greater than the thickness of the initial gate layer; and after the second ion implantation, performing at least one third ion implantation, wherein the depth of the third ion implantation is greater than the thickness of the initial gate layer.

2. The method according to claim 1, wherein the first region is formed in a different type from a device in which the second region and the third region are formed.

3. The method of claim 1, wherein the first ion implantation has an implant ion dose greater than an implant ion dose of the second ion implantation.

4. The method of claim 1, wherein the third ion implantation has an implant ion dose greater than the second ion implantation.

5. The method of claim 1, wherein the second ion implantation has an implanted ion energy greater than that of the first ion implantation.

6. The method of claim 1, wherein the third ion implantation has an implant ion dose greater than the second ion implantation.

7. The method of claim 1, wherein the material of the initial gate layer comprises: polycrystalline silicon, amorphous silicon, microcrystalline silicon, amorphous germanium, or a metal gate material.

8. The method of claim 1, further comprising forming a first mask layer on the surface of the first well region before the second ion doping; and carrying out second ion doping on the semiconductor substrate in the second area by taking the initial gate layer and the first mask layer as masks.

9. The method of claim 1, wherein the first ion doping process comprises an ion implantation process or a solid-state source doping process.

10. The method of claim 1, wherein after the first ion doping and before the initial gate layer forming, further comprising: and forming gate dielectric layers on the surfaces of the first region, the second region and the third region of the semiconductor substrate, wherein the initial gate layer is positioned on the surface of the gate dielectric layer.

11. The method for forming a semiconductor device according to claim 10, wherein the method for forming the first gate structure comprises: removing the gate dielectric layer on the surface of the second well region to expose the surface of the second well region; forming a first gate dielectric layer on the surface of the second well region; forming a first gate electrode film on the surface of the first gate dielectric layer; and forming a second mask layer on the surface of the first gate film, etching the first gate film by taking the second mask layer as a mask, and forming a first gate layer on the surface of the second well region to form the first gate structure.

12. The method according to claim 11, wherein the method for forming the second gate structure comprises: and after the first grid structure is formed, etching the initial grid layer and the grid dielectric layer, and forming a second grid structure on the third well region.

13. The method for forming a semiconductor device according to claim 1 or 12, further comprising: and forming a fourth well region in the semiconductor substrate of the first region, wherein the fourth well region is adjacent to the first well region, the fourth well region is internally provided with first ions, and the ion concentration of the fourth well region is higher than that of the first well region.

14. The method according to claim 13, wherein the method for forming the fourth well region comprises: and before the second ion doping, third ion doping is carried out in the semiconductor substrate of partial first region and second region, and a fourth well region is formed in the first region.

15. The method for forming a semiconductor device according to claim 13, further comprising: and forming the second gate structure on the first well region, and forming the first gate structure on the fourth well region.

16. A semiconductor device formed by the method of any one of claims 1 to 15, said semiconductor device being a multi-threshold voltage transistor device.

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