CN105022441A - Temperature-independent current reference - Google Patents

Abstract

The present invention proposes a temperature-independent integrated circuit current reference source. The integrated circuit current reference source includes: a first current generating circuit, a second current generating circuit, and a current summation circuit; the first current generating circuit is used for Generate a negative temperature coefficient current; the second current generating circuit is used to generate a positive temperature coefficient current; the output end of the first current generating circuit is connected to an input end of the current summation circuit, and the output end of the second current generating circuit is connected to the current summation circuit. Connected to the other input terminal of the circuit, the current summation circuit is used to superimpose the respective output currents of the first current generating circuit and the second current generating circuit according to a set ratio, and the output current generated by it is temperature-independent IC current reference output current.

Description

A Temperature-Independent Current Reference Source

technical field

The invention relates to the field of analog integrated circuit design, and more particularly relates to a temperature-independent integrated circuit current reference source realized by using current superposition technology.

Background technique

The current reference source is a commonly used module in analog integrated circuits, and is widely used in various analog integrated circuits and analog/mixed-signal integrated circuits, including data converters, switched capacitor circuits, monolithic image sensors, micro-electromechanical systems (MEMS) interface circuit, etc.

Traditional temperature-independent current reference sources are converted to output current through a resistor on the basis of a voltage source. Figure 1 is a traditional temperature-independent current reference source. This circuit converts the temperature-independent output voltage V _REF generated by the bandgap reference voltage source into a reference current through an operational amplifier and resistors. Although the bandgap reference voltage V _REF has the advantage of being independent of process, voltage and temperature, the output current is also affected by amplifier offset and resistance temperature characteristics, so the reference current generated by this structure cannot meet the characteristics of low temperature coefficient. In some high-end temperature-sensitive integrated circuit applications, these traditional current reference sources cannot meet their needs.

Contents of the invention

The purpose of the present invention is to solve the above-mentioned technical problem that the temperature coefficient of the traditional current reference source is difficult to reduce, and adopt the current summation technique to generate the current reference irrelevant to the temperature.

To achieve the above object, the present invention provides a temperature-independent integrated circuit current reference source, said integrated circuit current reference source comprising: a first current generating circuit 301, a second current generating circuit 302, and a current summation circuit 303;

The first current generating circuit 301 is used to generate a current that decreases with increasing temperature, that is, to generate a negative temperature coefficient current;

The second current generation circuit 302 is used to generate a current that increases with temperature, that is, to generate a positive temperature coefficient current;

The output end of the first current generation circuit 301 is connected to one input end of the current summation circuit 303, and the output end of the second current generation circuit 302 is connected to the other input end of the current summation circuit 303 , the current summation circuit 303 is used to superimpose the respective output currents of the first current generation circuit 301 and the second current generation circuit 302 according to a set ratio, and the output terminal of the current summation circuit 303 is temperature-independent output of the integrated circuit current reference.

Optionally, the above-mentioned first current generating circuit 301 includes: a first P-type current mirror, a first N-type current mirror, a resistor R1 and a first PNP-type transistor;

The first P-type current mirror and the first N-type current mirror are mutual loads, thereby forming a self-bias structure;

The resistor R1 is connected between the source of the output transistor of the first N-type current mirror and the negative power supply;

The emitter of the first PNP transistor is connected to the source of the input transistor of the first N-type current mirror, and the base and collector of the first PNP transistor are connected to the negative power supply;

Wherein, the first PNP transistor is replaced by an NPN transistor or a diode.

Optionally, the above-mentioned second current generating circuit 302 includes: a second P-type current mirror, a second N-type current mirror, a resistor R2, a second PNP-type transistor, and a third PNP-type transistor;

The second P-type current mirror and the second N-type current mirror are mutual loads, thereby forming a self-bias structure;

The resistor R2 is connected between the source of the output tube of the second N-type current mirror and the emitter of the second PNP transistor, and the base and collector of the second PNP transistor are connected to the negative power supply; the third PNP The emitter stage of the type transistor is connected to the source stage of the input tube of the second N-type current mirror, and the collector and base of the third PNP type transistor are connected to the negative power supply;

Wherein, all or one of the second PNP transistor and the third PNP transistor is replaced by an NPN transistor or a diode.

Optionally, the first P-type current mirror and the first N-type current mirror adopt a cascode structure;

The second P-type current mirror and the second N-type current mirror adopt a cascode structure.

Optionally, the current summation circuit 303 includes: two P-type MOS transistors, the gates of the two P-type MOS transistors are respectively connected to the first P-type current mirror and the second P-type current mirror, and The drains of the two P-type MOS transistors are short-circuited to form the output end of the current summation circuit.

Optionally, the above-mentioned first P-type current mirror and the second P-type current mirror have the same structure.

Optionally, the first P-type current mirror includes: a first PMOS transistor and a second PMOS transistor; the N-type current mirror includes: a first NMOS transistor and a second NMOS transistor;

The source of the first PMOS transistor is connected to the positive power supply vdd, the gate and drain of the first PMOS transistor are connected to the A node; the gate of the second PMOS transistor is connected to the node A, and the source of the second PMOS transistor connected to said positive power supply vdd;

The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, the gate of the first NMOS transistor is connected to the gate of the second NMOS transistor, and the source of the first NMOS transistor is connected to the resistor R1 or the One end of resistor R2;

The gate and drain of the second NMOS transistor are connected to the node B, the drain of the second PMOS transistor is connected to the node B, the source of the second NMOS transistor is connected to the emitter of the PNP transistor Q2, and the PNP The base and collector of the type triode Q2 are connected to the negative power supply vss.

Optionally, the above-mentioned first current generating circuit 301 adopts a negative temperature coefficient current generating circuit based on the virtual short-circuit characteristic of the operational amplifier; the second current generating circuit 302 adopts a positive temperature coefficient current generating circuit based on the virtual short-circuit characteristic of the operational amplifier.

Compared with prior art, the technical advantage of the present invention is:

The invention generates a temperature-independent reference current by superimposing the negative temperature coefficient current and the positive temperature coefficient current in a certain ratio. The invention adopts mainstream CMOS integrated circuit technology and bipolar integrated circuit technology to obtain a current reference independent of technology, voltage and temperature.

Description of drawings

Fig. 1 is the schematic diagram of current reference source circuit of prior art;

Fig. 2 is the structure schematic diagram of current reference source independent of temperature of current summation type of the present invention;

Fig. 3 is the circuit diagram of the specific embodiment that provides based on the structural schematic diagram of the current reference source that has nothing to do with temperature;

Figure 4-a is a circuit diagram of a negative temperature coefficient current generating circuit (that is, a first current generating circuit) used in an embodiment of the present invention;

FIG. 4-b is a circuit diagram of a positive temperature coefficient current generating circuit (ie, a second current generating circuit) used in an embodiment of the present invention.

Detailed ways

The technical solution of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

In the following embodiments, the first current generating circuit is named as a negative temperature coefficient current generating circuit, and the second current generating circuit is named as a positive temperature coefficient current generating circuit.

The temperature-independent current reference source provided by the present invention is shown in Figure 2, including: a negative temperature coefficient current generation circuit I _CTAT , a positive temperature coefficient current generation circuit I _PTAT and a current summation circuit I _TOTAL , and the connection relationship of each circuit Figure 2.

As shown in FIG. 3 , the temperature-independent current reference source circuit in this embodiment includes: a negative temperature coefficient current generating circuit 301 , a positive temperature coefficient current generating circuit 302 and a current summation circuit 303 .

As shown in Figure 4-a, the negative temperature coefficient current generating circuit 301 further includes: two PMOS transistors MP1 and MP2 (forming a P-type current mirror 401), two NMOS transistors MN1 and MN2 (forming an N-type current mirror 402), one Resistor R1 and a PNP transistor Q1. The connection relationship of each device is as follows: the source of PMOS transistor MP1 is connected to the positive power supply vdd, the gate is connected to its drain and connected to the gate of PMOS transistor MP2, the source of MP2 is connected to vdd, MP1 and MP2 form a P type current mirror, the drain of NMOS transistor MN1 is connected to the drain of PMOS transistor MP1, the gate of MN1 is connected to the gate of MN2, the source of MN1 is connected to one end of resistor R1, the other end of R1 is connected to the negative power supply vss, and the NMOS transistor MN2 The gate of MN2 is connected to its drain and is connected to the drain of PMOS transistor MP2, the source of MN2 is connected to the emitter of PNP transistor Q2, the base and collector of Q2 are connected to vss, MN1 and MN2 form an N-type current mirror, The N-type current mirror and the P-type current mirror are connected into a self-biased structure. The current ratio of the P-type current mirror formed by MP1 and MP2 is 1:1, and the current ratio of the N-type current mirror formed by MN1 and MN2 is 1:1.

The positive temperature coefficient current generation circuit 302 shown in Figure 4-b further includes: two PMOS transistors MP4 and MP5 (forming a P-type current mirror 401), two NMOS transistors MN3 and MN4 (forming an N-type current mirror 402), A resistor R2 and two PNP transistors Q2, Q3. The connection relationship of each device is as follows: the source of PMOS transistor MP4 is connected to vdd, the gate is connected to its drain and connected to the gate of PMOS transistor MP5, the source of MP5 is connected to vdd, MP4 and MP5 form a P-type current mirror , the drain of the NMOS transistor MN3 is connected to the drain of MP4, the gate of MN3 is connected to the gate of the NMOS transistor MN4, the source of MN3 is connected to one end of the resistor R2, and the other end of R2 is connected to the emitter of the PNP transistor Q2. The base and collector are connected to vss, the gate of NMOS transistor MN4 is connected to its drain and connected to the drain of MP5, the source of MN4 is connected to the emitter of PNP transistor Q3, the base and collector of Q3 are connected to vss, MN3 An N-type current mirror is formed with MN4, and the N-type current mirror and the P-type current mirror are connected to form a self-bias structure. The current ratio of the P-type current mirror formed by MP4 and MP5 is 1:1, and the current ratio of the N-type current mirror formed by MN3 and MN4 is 1:1. The emitter junction area of Q2 is designed to be n times the emitter junction area of Q3, and the value range of n is: a positive integer greater than 1. In the above technical solution, the P-type current mirror 401 can also use a P-type current mirror with a cascode structure or a current mirror composed of a PNP transistor; the N-type current mirror 402 can also use an N-type current mirror with a cascode structure Or use a current mirror composed of NPN transistors.

The specific structure of the negative temperature coefficient current generation circuit 301 and the positive temperature coefficient current generation circuit 302 can also adopt the negative temperature coefficient current generation circuit using the virtual short circuit characteristic of the operational amplifier and the positive temperature coefficient current generation circuit using the virtual short circuit characteristic of the operational amplifier.

The current summation circuit 303 further includes: two PMOS transistors MP3, MP6 and two NMOS transistors MN5, MN6. The connection relationship of each device is as follows: the gate of the PMOS transistor MP3 is connected to the gate of the PMOS transistor MP1 in the negative temperature coefficient current generation circuit, the source of MP3 is connected to vdd, and the gate of the PMOS transistor MP6 is connected to the PMOS transistor in the positive temperature coefficient current generation circuit. The gate of MP4, the source of MP6 are connected to vdd, the drains of MP3 and MP6 are connected, the drain of NMOS transistor MN5 is connected to the drains of MP3 and MP6, the drain of MN5 is also connected to its gate, and the drain of MN5 The source is connected to vss, the gate of the NMOS transistor MN6 is connected to the gate of MN5, the source of MN6 is connected to vss, and the drain of MN6 is the output of the current summation circuit. The positive temperature coefficient current and the negative temperature coefficient current are summed through MP3 and MP6, and the function of the N-type current mirror formed by MN5 and MN6 is to reverse the summed current.

The principle of the temperature-independent current reference source of this embodiment is as follows: the P-type current mirror and the N-type current mirror in the negative temperature coefficient current generation circuit form a self-bias structure. Since the current ratio of the two current mirrors is 1:1, the NMOS The source voltages of the tubes MN1 and MN2 are basically equal, and the voltage drop across the resistor R1 is the emitter junction voltage of the PNP transistor Q1, and the negative temperature coefficient current is shown in formula (1):

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; CTAT</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

The P-type current mirror and the N-type current mirror in the positive temperature coefficient current generation circuit form a self-bias structure. Since the current ratio of the two current mirrors is 1:1, the source voltages of the NMOS transistors MN3 and MN4 are basically equal, and the resistor R2 The voltage drop at both ends is the emitter junction voltage difference between PNP transistors Q3 and Q2, and the positive temperature coefficient current is shown in formula (2):

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; PTAT</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

In the current summation circuit, the width-to-length ratio of the PMOS transistors MP3 and MP6 is L:K (here the ratio of L to K is set according to the ratio of the absolute value of the temperature coefficient of the two input currents, so that the total current temperature coefficient is 0), then the summed current is:

I _TOTAL = L·I _CTAT +K·I _PTAT (3)

Reasonable selection of the ratio of L and K, the ratio of R1 and R2 can adjust the output current IOUT to zero temperature coefficient.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than limit them. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent replacements to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all of them should be included in the scope of the present invention. within the scope of the claims.

Claims (8)

1. a temperature independent integrated circuit current reference source, it is characterized in that, described integrated circuit current reference source comprises: the first current generating circuit (301), the second current generating circuit (302) and electric current summing circuit (303);

Described first current generating circuit (301), the electric current reduced for generation of raising with temperature, namely for generation of negative temperature parameter current;

Described second current generating circuit (302), the electric current raised for generation of raising with temperature, namely for generation of positive temperature coefficient (PTC) electric current;

The output terminal of described first current generating circuit (301) is connected with an input end of described electric current summing circuit (303), the output terminal of described second current generating circuit (302) is connected with another input end of described electric current summing circuit (303), this electric current summing circuit (303) superposes in a setting ratio for the electric current the first current generating circuit (301) and the second current generating circuit (302) exported separately, and the output terminal of described electric current summing circuit (303) is the output terminal of temperature independent integrated circuit current reference source.

2. temperature independent integrated circuit current reference source according to claim 1, is characterized in that, described first current generating circuit (301) comprises: a P type current mirror, the first N-type current mirror, resistance R1 and the first PNP type triode;

A described P type current mirror and described first N-type current mirror load each other, thus form automatic biasing structure;

Between the source class that described resistance R1 is connected to the efferent duct of described first N-type current mirror and negative supply;

The emitter of described first PNP type triode is connected to the source class of the input pipe of described first N-type current mirror, and the base stage of this first PNP type triode and collector connect described negative supply;

Wherein, described PNP type triode adopts NPN type triode or diode to replace.

3. temperature independent integrated circuit current reference source according to claim 1, it is characterized in that, described second current generating circuit (302) comprises: the 2nd P type current mirror, the second N-type current mirror, resistance R2, the second PNP type triode and the 3rd PNP type triode;

Described 2nd P type current mirror and the second N-type current mirror load each other, thus form automatic biasing structure;

Between the source class that described resistance R2 is connected to the efferent duct of described second N-type current mirror and the emitter of the second PNP type triode, base stage and the collector of the second PNP type triode connect negative supply; The emitting stage of the 3rd PNP type triode is connected to the source class of the input pipe of described second N-type current mirror, and collector and the base stage of this second PNP type triode are connected to negative supply;

Wherein, described second PNP type triode and the 3rd PNP type triode all or one of them adopt NPN type triode or diode to replace.

4. the temperature independent integrated circuit current reference source according to Claims 2 or 3, is characterized in that, a described P type current mirror and the first N-type current mirror adopt cascode structure;

Described 2nd P type current mirror and the second N-type current mirror adopt cascode structure.

5. the temperature independent integrated circuit current reference source according to Claims 2 or 3, it is characterized in that, described electric current summing circuit (303) comprises: two P type metal-oxide-semiconductors, the grid of described two P type metal-oxide-semiconductors is connected with the 2nd P type current mirror with a described P type current mirror respectively, and the drain electrode short circuit of described two P type metal-oxide-semiconductors forms the output terminal of electric current summing circuit.

6. the temperature independent integrated circuit current reference source according to Claims 2 or 3, is characterized in that, a described P type current mirror is identical with the 2nd P type current-mirror structure.

7. the temperature independent integrated circuit current reference source according to Claims 2 or 3, is characterized in that,

A described P type current mirror comprises: the first pmos type transistor and the second pmos type transistor; Described N-type current mirror comprises: the first nmos type transistor and the second nmos type transistor;

The source class of the first PMOS transistor connects positive supply vdd, and the grid of this first PMOS transistor and drain electrode are connected in A node; The grid of the second PMOS transistor is connected with described node A, and the source class of this second PMOS transistor is connected to described positive supply vdd;

The drain electrode of the first nmos pass transistor connects the drain electrode of described first PMOS transistor, and the grid of this first nmos pass transistor connects the grid of the second nmos pass transistor, and the source class of the first nmos pass transistor connects one end of described resistance R1 or described resistance R2;

Grid and the drain electrode of the second nmos pass transistor are connected in Node B, the drain electrode of described second PMOS transistor is connected with described Node B, the source class of this second nmos pass transistor connects the emitter of PNP type triode Q2, and the base stage of this PNP type triode Q2 and collector meet negative supply vss.

8. temperature independent integrated circuit current reference source according to claim 1, is characterized in that,

Described first current generating circuit (301) adopts the negative temperature parameter current based on operational amplifier imaginary short characteristic to produce circuit;

Described second current generating circuit (302) adopts the positive temperature coefficient (PTC) current generating circuit based on operational amplifier imaginary short characteristic.