CN108427468A - A kind of Low Drift Temperature fast transient response high PSRR bandgap voltage reference - Google Patents

Abstract

The invention belongs to the technical field of analog integrated circuits, in particular to a bandgap reference voltage source with low temperature drift, fast transient response and high power supply rejection ratio. The circuit includes three parts: bandgap reference generating circuit, error amplifier and start-up circuit. The present invention utilizes the base-emitter voltage VBE with negative temperature coefficient of two bipolar transistors and the linear superposition of positive temperature coefficient difference ΔVBE of VBE to generate a bandgap reference voltage with zero temperature coefficient. Compared with the traditional structure, the temperature coefficient of the bandgap reference voltage generated by this circuit is smaller, and the startup circuit is novel and has better transient response.

Description

A Low Temperature Drift Fast Transient Response High Power Supply Rejection Ratio Bandgap Voltage Reference Source

technical field

The invention belongs to the technical field of analog integrated circuits, in particular to a bandgap reference voltage source with low temperature drift, fast transient response and high power supply rejection ratio.

Background technique

With the development of Moore's law for integrated circuits, integrated circuits are becoming more and more integrated, feature sizes are getting smaller, and power supply voltages are getting lower and lower, which puts forward higher requirements for chip performance and power consumption. At the same time, the bandgap reference is a part of the chip that provides a reference for the entire circuit, and its slight disturbance will seriously affect the stability of the entire system, resulting in large deviations. Therefore, the immunity of the bandgap reference to temperature and supply voltage is particularly important. When the temperature and power supply voltage fluctuate in a wide range, the output of the reference voltage source is required to hardly change, thus providing a very stable voltage value.

Figure 1 shows the traditional bandgap reference voltage source, which is composed of NPN transistors Q1, Q2, Q3, Q4, resistors R1, R2, R3 and DC current source I. The circuit uses a feedback loop to make the circuit work at a specific operating point, and the output voltage at this point is equal to the base-emitter voltage VBE of Q1 plus a voltage value proportional to the base-emitter differential voltage of Q1Q2. Among them, Q1, Q2 and R3 generate a current IPTAT proportional to the absolute temperature, and Q3 clamps the voltage at point X by amplifying the change of the voltage at point X.

The disadvantage of this kind of reference source is that the current I is determined by the power supply, and it will change with the change of the power supply voltage; the feedback loop has only one single transistor Q3, the loop gain is small, and the clamping accuracy of point X is low.

Contents of the invention

The technical problem to be solved by the invention is to provide a bandgap reference voltage source with low temperature drift, fast transient response and high power supply rejection ratio.

The present invention adopts following technical scheme:

The invention proposes a bandgap reference voltage source with low temperature drift, fast transient response and high power supply rejection ratio, which is composed of a bandgap reference generating circuit, an error amplifier and a starting circuit. The bandgap reference generation circuit includes: NPN transistor Q1 connected in series with resistor R1, NPN transistor Q2 connected in series with resistor R2, the collector of Q1 connected to the negative terminal of R1, the collector of Q2 connected to the negative terminal of R2, and the base of Q2 connected to The collector of Q1, the emitter of Q1 and the emitter of Q2 are shorted together and then connected to the positive end of resistor R4. The ratio of the emitter area of Q1 to Q2 is 1:8, and the negative end of R4 is connected to the power ground; R1 The positive end of R2 is short-circuited with the positive end of R2, and then connected to the negative end of resistor R3, and the positive end of R3 is connected to the source of NMOS transistor MN5, which is used as the output node VREF of the bandgap reference voltage; the drain of MN5 is connected to the PMOS transistor MP6 Drain stage, the gate of MN5 is shorted with the drain stage of NMOS transistor MN2 as the output node VE of the error amplifier; the source stage of MP6 is connected with the negative end of resistor R7 as the voltage node VDD, and the positive end of resistor R7 is connected Positive power supply VIN, the gate of MP6 is short-circuited with the gate of PMOS transistor MP9 and then connected to the output terminal of the inverter INV, and the input terminal of INV is connected to VDD.

The error amplifier includes: the collector of the NPN transistor Q3 is connected to the source of the NMOS transistor MN1, the base of Q3 is connected to the collector of Q1, the collector of the NPN transistor Q4 is connected to the source of the NMOS transistor MN2, and the base of Q4 is connected to the source of the NMOS transistor MN2. The collector of Q2, the emitter of Q3 and the emitter of Q4 are short-circuited and then connected to the positive terminal of resistor R5, and the negative terminal of R5 is connected to the power ground; the gate of MN1 and the gate of MN2 are short-circuited and then connected to the voltage node VREF, and the The drain is connected to the drain of MP3 of the PMOS transistor, the drain of MN2 is connected to the drain of MP4 of the PMOS transistor, the gate of MP3 is short-circuited, and the gate is connected to the gate of MP4, and the source of MP3 is shorted to the source of MP4 Connect to VDD.

The starting circuit includes: the source of the PMOS transistor MP9 is connected to VDD, the drain of MP9 is connected to the positive end of the resistor R6, the negative end of R6 is short-circuited to the drains of the NMOS transistors MN11 and MN13, and the gate of the NMOS transistor MN7, The drain of MN7 is shorted to the drain of MP3, the source of MN7 is connected to the drain of NMOS transistor MN8, the gate of MN8 is connected to VDD, the drain of MN8 is shorted to the negative terminals of resistors R5 and R6 to ground; the gate of MN11 is connected to the drain After short-circuiting, the gate is connected to the gate of NMOS transistor MN12, the drain of MN12 is connected to the source of MN11, the drain of NMOS transistor M10 is connected to the source of MN13, the gate of MN10 is short-circuited to the gate of MN13 and then connected to VREF, The source of MN10 is shorted to the source of MN12 and grounded.

Description of drawings

Figure 1 shows a traditional bandgap voltage reference

Fig. 2 is the overall circuit diagram of the low temperature drift fast transient response high power supply rejection ratio bandgap reference voltage source of the present invention

Fig. 3 is the bandgap reference generation circuit diagram of the present invention

Fig. 4 is the starting circuit diagram of the present invention

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings.

Fig. 2 shows the overall circuit diagram of the low-temperature drift fast transient response high power supply rejection ratio bandgap reference voltage source of the present invention. The bandgap reference is composed of a bandgap reference generating circuit, an error amplifier and a starting circuit. The error amplifier is composed of NPN transistors Q3, Q4, NMOS transistors MN1, MN2, MP3, MP4 and resistor R5. The function of the amplifier is to form a negative feedback loop between the voltage nodes A, B and the output node VREF to increase the loop gain, thereby clamping the voltages of the two points A and B to make them approximately equal. The gain of this amplifier is:

A _V =g _3,4 {[g _m1,2 (r _CE3,4 ‖r _o1,2 )]‖r _o3,4 } (1)

The supply voltage rejection ratio is:

(3) T is the loop gain in the formula. It can be seen from (1) that the loop gain is very high, so the power supply voltage rejection ratio is very small.

Figure 3 shows the circuit diagram of the bandgap reference generation, which is composed of NPN transistors Q1, Q2, resistors R1, R2, R3, R4 and NMOS transistor MN5. The reference utilizes the linear superposition of the negative temperature coefficient base-emitter voltage VBE of two bipolar transistors Q1, Q2 and the positive temperature coefficient difference ΔVBE of VBE to generate a zero temperature coefficient bandgap reference voltage. n is the emitter area ratio of Q2 and Q1, so the expression of ΔV _BE is:

The current flowing through R2 is This current is the PTAT current. The resistance values of R1 and R2 are equal. As mentioned earlier, the voltages of nodes A and B through the clamping effect of the amplifier are the same, so the currents flowing through R1 and R2 are equal, so the expression of VREF is:

From formula (5), it can be seen that choosing the appropriate A bandgap reference voltage with almost zero temperature drift can be obtained.

4 is a partial circuit diagram of the start-up circuit of the present invention, which is composed of NMOS transistors MN7, MN8, MN10, MN11, MN12, MN13, resistor R6 and PMOS transistor MP6. When the reference works in the state of zero current, VREF is 0, MN10 and MN13 work in the cut-off region, but because MN11 and MN12 are in the conduction state at this time, the current flows through MN11 and MN12, and the potential of node C is greater than a threshold voltage. MN8 works in the deep triode area, so MN7 is turned on, the potential of point D is pulled down, MP3 and MP4 are turned on, the gate potential of MN5 is pulled up, and the current flows into the bandgap reference generating circuit.

The bandgap reference voltage gradually increases with the increase of the current, the gate voltage of MN10 and MN13 is turned on after rising, the potential of point C is pulled down, MN7 is cut off, the current of the branch where MN7 is located is 0, and the op amp works normally , until the value of VREF stabilizes. The gain of this structure is:

A _Vstart-up ＝g _m13 (r _o13 ‖r _R6 ) (6)

(6) The resistance value of R6 in the formula is the same order of magnitude as the small signal resistance value of MN13, so the gain of the starting circuit is very large, and a fast transient response is realized.

Claims (4)

1. a kind of Low Drift Temperature, fast transient response, the bandgap voltage reference of high PSRR, which is characterized in that voltage source By band-gap reference generation circuit (Bandgap Core), error amplifier (Error Amplifier), start-up circuit (start- Up it) constitutes.

2. a kind of Low Drift Temperature according to claim 1, fast transient response, the bandgap voltage reference of high PSRR Source, which is characterized in that the band-gap reference generation circuit includes：NPN triode Q1 is connected with resistance R1, NPN triode Q2 with Resistance R2 series connection, the collector of Q1 connect the negative terminal of R1, and the collector of Q2 connects the negative terminal of R2, and the base stage of Q2 meets the collector of Q1, Q1 Emitter be shorted together the anode of rear connecting resistance R4 with the emitter of Q2 and connect, the emitter area ratio of Q1 and Q2 are 1:8, The negative terminal of R4 connects power ground；The negative terminal of connecting resistance R3 after the anode of R1 and the anode short circuit of R2, the positive termination NMOS tube MN5's of R3 Source level, and as the output node VREF of bandgap voltage reference；The drain of MN5 connects the drain of PMOS tube MP6, the grid of MN5 with The drain of NMOS tube MN2 is shorted together the output node VE as error amplifier；The source level of MP6 connects the negative terminal with resistance R7 Short circuit as voltage node VDD, the grid of positive termination positive supply VIN, MP6 of resistance R7 with after the grid short circuit of PMOS tube MP9 The output end of phase inverter INV is connect, the input of INV terminates VDD.

3. a kind of Low Drift Temperature according to claim 2, fast transient response, the bandgap voltage reference of high PSRR Source, which is characterized in that the error amplifier includes：The collector of NPN triode Q3 connects the source level of NMOS tube MN1, the base of Q3 Pole connects the collector of Q1, and the collector of NPN triode Q4 connects the source level of NMOS tube MN2, and the base stage of Q4 meets the collector of Q2, Q3 Emitter and Q4 emitter short circuits after connecting resistance R5 anode, the negative terminal of R5 connects power ground；The grid of MN1 and the grid of MN2 Short circuit be followed by voltage node VREF, MN1 drain connect PMOS tube MP3 drain, the drain of MN2 connects the leakage of the MP4 of PMOS tube Grade, MP3 grid leak short circuit post tensioned unbonded prestressed concretes connect the grid of MP4, and the source level of MP3 and the source level short circuit of MP4 are followed by VDD.

4. a kind of Low Drift Temperature according to claim 3, fast transient response, the bandgap voltage reference of high PSRR Source, which is characterized in that the start-up circuit includes：The source level of PMOS tube MP9 meets VDD, the anode of the drain connecting resistance R6 of MP9, The grid short circuit of the negative terminal of R6 and the MN7 of the drain of NMOS tube MN11 and MN13, NMOS tube, the drain of MN7 and the drain of MP3 are short It connects, the source level of MN7 connects the drain of NMOS tube MN8, and the grid of MN8 meets VDD, and the drain of MN8 connects with the negative terminal short circuit of resistance R5, R6 Ground；MN11 grid leak short circuit post tensioned unbonded prestressed concretes connect the grid of NMOS tube MN12, and the drain of MN12 connects the source level of MN11, the leakage of NMOS tube M10 Grade connects the source level of MN13, and the grid of MN10 and the grid short circuit of MN13 are followed by VREF, the source level of MN10 and the source level short circuit of MN12 After be grounded.